On Mon, Feb 8, 2016 at 9:46 AM Nico Huber wrote:
> On 08.02.2016 12:10, Patrick Georgi via coreboot wrote:
> > 2016-02-04 10:35 GMT+01:00 Patrick Georgi :
> >> during the review of some commits that are in the process of being
> >> upstreamed from Chrome OS, people noticed that chipset drivers li
makes sense to me.
On Mon, Feb 8, 2016 at 3:10 AM Patrick Georgi via coreboot <
coreboot@coreboot.org> wrote:
> 2016-02-04 10:35 GMT+01:00 Patrick Georgi :
> > during the review of some commits that are in the process of being
> > upstreamed from Chrome OS, people noticed that chipset drivers lik
Nico, I agree with you completely: non-zero is true, zero false. It's C.
But I am starting now to feel like a dinosaur, b/c
"Oh, and I'm trying to hang with the cool kids and use bool :)" -- Rusty
It makes me want to start an emo coreboot programmer feed like this one:
https://twitter.com/kylor3n?
omething to the coding guide to
> > avoid magic numbers?
> Make that a separate thread please :-)
>
>
> Patrick
>
> > On Thu, Feb 4, 2016 at 6:05 AM, ron minnich wrote:
> >>
> >>
> >> On Thu, Feb 4, 2016 at 2:29 AM Patrick Georgi via coreboot
&g
On Thu, Feb 4, 2016 at 2:29 AM Patrick Georgi via coreboot <
coreboot@coreboot.org> wrote:
>
>
> 1. TRUE/FALSE
> Do we want such defines? If so, TRUE/FALSE, or true/false, or
> True/False, or ...?
>
should we start using bool ...?
>
> 2. BIT16 vs BIT(16) vs (1 << 16) vs 0x1
> I don't think i
On Sat, Jan 30, 2016 at 3:06 PM Alex G. wrote:
> Furthermore, I believe that this arbitrary
> change was done as an act of spite towards a set of engineers.
Well, wow. This just got weird. I think I'm done with this discussion.
ron
--
coreboot mailing list: coreboot@coreboot.org
http://www.c
The requirement for ATT syntax was set informally in 2001, when I had some
partners from U. Md. who were advocating for Intel syntax. We discovered
that having two syntaxes is unworkable.
>From that time we assumed that everyone would use a common syntax. It
certainly never occurred to us that we
I think JELTKA is a model of how it can be done. Consider talking to John
Lewis.
Ron, Satisfied JELTKA user.
On Thu, Jan 21, 2016 at 9:58 AM Patrick Georgi via coreboot <
coreboot@coreboot.org> wrote:
> 2016-01-21 18:49 GMT+01:00 Kitestramuort :
> > Can I compile it 64bit?
> As long as you keep
Just build the coreboot crossbuild chain and you should be fine. I've been
building on 64-bit linux for years.
On Tue, Jan 19, 2016 at 7:39 AM Gregg Levine wrote:
> Hello!
> Not yet. I'm still bringing over my backups from an earlier period of
> time so I can't rightfully say. I can state that S
One thing I think you'd enjoy doing is building the qemu target, setting up
qemu with gdb, and just watching what happens, instruction by instruction,
as the system boots.
ron
On Sun, Jan 10, 2016 at 3:28 AM Rafael Machado <
rafaelrodrigues.mach...@gmail.com> wrote:
> Hi Peter and Rudolf.
> Than
Please see:
https://docs.google.com/document/d/1Pvf9Yxorcd3sbgs8WcomcTl3J4bmX6e1UE0ROCefR88/edit?usp=sharing
corrections welcome.
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On Mon, Dec 7, 2015 at 10:16 PM Peter Stuge wrote:
> ron minnich wrote:
> > nobody cared enough to really do the work
>
> That's the problem - not the solution. Don't build infrastructure to
> support complacency, build infrastructure to support desirable activity
there's another way to do this that few people use.
Back in the E7500 days, the 7505 came along. We experimented with this:
src/northbridge/intel/e750x
and put the common files in there.
Under e750x we had
e7500
e7505
for the different files.
so, src/northbridge/intel/e750x/{e7500,e7505}
worked f
as long as it does not turn into #ifdef spaghetti it's worth a look.
ron
On Sun, Dec 6, 2015 at 8:19 AM Alexander Couzens wrote:
> hi,
>
> baytrail and fsp_baytrail shares a lot of code.
> Any ideas how we can merge these?
>
> best,
> lynxis
>
> --
> Alexander Couzens
>
> mail: lyn...@fe80.eu
>
Let's not do anon service. Our last bug tracker became a transit point for
all kinds of junk.
ron
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Can we calm down? Vladimir, your note came out after I -2'ed Alex's
proposal and we have made it clear that the proposal to "Remove" AGESA is
just that -- a proposal. It's not going to happen.
Thanks
ron
On Sat, Nov 7, 2015 at 6:12 AM Vladimir wrote:
> >
> >>> On 11/07/2015 10:18 AM, Alex Gagn
So, I think in the next day, we should pick the location and date for the
"spring" meeting. I'd also suggest it be a 6 month interval between
meetings, which is the other reason I thought end of january was a bit too
soon.
Sound OK?
What Stefan says is very true. I have friends here in the US wh
yeah, FOSDEM happens at a very unpleasant time of year. Short days, lots of
rain, cold, ...
ron
On Mon, Nov 2, 2015 at 12:07 PM Vadim Bendebury
wrote:
> I just looked at the dates - end of January seems a bit odd time to visit,
> cold nasty weather, higher likelihood of air travel delays, etc.
So, if someone came to me with this problem:
building all the targets is slow
and this solution:
get rid of a bunch of them
I'd tell them to go back for more data, because that's just not enough
information.
Why's it slow? Where's the time going? How many files, on average, are part
of an AGESA b
This sounds like a wonderful idea, and I think I would like to attend and
help out.
On Sun, Nov 1, 2015 at 8:42 AM wrote:
> Dear coreboot friends,
>
> As discussed briefly in the last minutes of the Bonn meeting, I propose
> to organize the next coreboot hackaton in Paris in 2016.
> Here is my p
Nice job all. Patrick, I'm looking forward t the next release detailing how
many files and lines were removed :-)
include, oh sad, the 440lx :-)
ron
On Fri, Oct 30, 2015 at 1:38 PM Patrick Georgi wrote:
> (Halloween 2015 release - just as scary as that sounds)
>
> Dear coreboot community,
>
>
On Fri, Oct 30, 2015 at 10:59 AM Alex Gagniuc wrote:
>
> I think historically, it has been assumed that everything in blobs is
> open up for RE and modification.
>
History? What? Only if your timeline is really short. We first started
doing the blobs support in 2001 for graphics. We NEVER held i
Possibly an appendix defining coreboot leadership would help.
On Fri, Oct 30, 2015 at 9:51 AM Martin Roth wrote:
> Hi Alex,
> Thanks for voicing your concerns. I do think that most of the
> issues you bring up are handled, or aren't as big issues you make them
> out to be. As always, I cou
On Thu, Oct 29, 2015 at 9:49 PM Alex G. wrote:
> My bad.
>
>
>
Apology accepted.
ron
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On Thu, Oct 29, 2015 at 9:04 PM Alex G. wrote:
> Hi Martin,
>
> It seems that the first part of your document ("Summary", and "More
> detail") is written in direct response to the removal of FSP 1.0 a month
> or so ago.
It might seem that way to you, having been at the eye of that particular
st
IIRC I did the IBM e325/6 back in the day and I'm happy to see it die.
ron
On Wed, Oct 28, 2015 at 8:49 AM Martin Roth wrote:
> It seems that we've got more issues than we can address before the
> proposed 4.2 release date within the next few days - we're trying to
> get this out in October.
>
I think we can make it clear to AMD that we are grateful for AGESA and
their support, and the way they have helped us to get to a good place in
terms of code; and, further, we can now offer a better option, with code
that really fits well into coreboot.
I don't see demoting AGESA as a bad thing; i
The AGESA code was always an awkward fit into coreboot. It was more like a
badly designed artificial limb than a real part of the code base. I
understand the idea of encouraging vendors to commit source but, at this
point, the AMD ship has sailed off to Port Binary Blob. AGESA was helpful
in its ti
On Tue, Oct 27, 2015 at 10:52 AM Nicky Sielicki wrote:
> Hello list,
>
> I'm interested in cleaning up some of the VGA programming in coreboot.
>
Good :-)
>
> I was trying to figure out why GM45 "native" textmode isn't working. I
> noticed the following bit of code
>
> > northbridge/intel/gm45
Aaron is my hero :-)
ron
On Fri, Oct 23, 2015 at 11:35 AM Aaron Durbin wrote:
> This one's for Ron.
>
> On Fri, Oct 23, 2015 at 10:32 AM, ron minnich wrote:
> > Build the tool in go. It's trivial. If you have an idea how it ought to
> work
> > I can se
We'll agree to disagree :-)
ron
On Fri, Oct 23, 2015 at 8:55 AM Patrick Georgi wrote:
> 2015-10-23 17:53 GMT+02:00 ron minnich :
> > Actually the idea crossed my mind because I just saw a different tool hit
> > the tree yesterday that was written in ... guess what languag
On Fri, Oct 23, 2015 at 8:39 AM Patrick Georgi wrote:
> It's more trivial not to have a tool in the first place.
> It's also more trivial not to add a new dependency to our build process.
> Especially a dependency that is lacking in portability (ie. users
> can't build coreboot anymore because th
Build the tool in go. It's trivial. If you have an idea how it ought to
work I can set it up in the playground in a few minutes.
ron
On Fri, Oct 23, 2015 at 8:24 AM Patrick Georgi wrote:
> Hi,
>
> Some mainboards come with soldered-on memory without SPD ROM. For
> these, we carry the SPD data i
ability. I don't really see any NEED to get rid of the second
> paragraph.
>
> Are there any other thoughts either way on getting rid of the second
> paragraph?
>
> Martin
>
>
>
> On Tue, Oct 20, 2015 at 6:47 PM, Alex G. wrote:
> > On 10/20/2015 10:54 AM, r
Eben Moglen, who ought to know, guided us on the release rules for the Plan
9 GPL release.
Here is what he told us could go in each file:
/*
* This file is part of the UCB release of Plan 9. It is subject to the
license
* terms in the LICENSE file found in the top-level directory of this
* dist
I won't say +1, that's so 2014.
Plus Two!
ron
On Mon, Oct 19, 2015 at 11:53 AM Peter Stuge wrote:
> Patrick Georgi wrote:
> > The paragraph in question is:
> >
> > You should have received a copy of the GNU General Public License
> > along with this program; if not, write to the Free Soft
BTW, will you be recording. That's something we've lacked in the past.
ron
On Sun, Oct 4, 2015 at 6:02 AM Alexander Couzens wrote:
> Hi,
>
> I would like to give a talk about my embedded controller programming.
>
> And beside that, I would like to have a talk/workshop something, to
> think abou
What Power board would you recommend for this test?
ron
On Sat, Sep 26, 2015 at 7:07 PM Timothy Pearson <
tpear...@raptorengineeringinc.com> wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA1
>
> On 09/26/2015 03:18 PM, ron minnich wrote:
> > I just joined the op
I just joined the open compute project as an individual member. Anybody
have some idea on what type of their nodes and which vendor are good to
look at for coreboot?
I realize OCP is not a coreboot user (I had that discussion with them about
5 years ago and they went with conventional wisdom, sadl
I'd love the
hat
cpu
magnet
thanks
ron
On Wed, Sep 9, 2015 at 12:30 AM Vladimir 'φ-coder/phcoder' Serbinenko <
phco...@gmail.com> wrote:
> Hello, all. My girlfriend Maria (CC'ed) would like to organize some
> goodies for coreboot meeting. Already available are black T-shirts:
> 2 x M, 8 x L, 1
If people feel strongly enough about this then we can do an external repo
for now.
Nico, do you want to set up a github repo and we can work out procedures
people use to try this out? As you know I'm more interested in Muen as a
replacement for the ramstage but this is a good first step.
ron
--
ng that ugly in the tree, I think we have room for SPARK :-)
I think this could prove to be a very important new direction for coreboot,
and I still think it belongs in the tree.
ron
On Fri, Aug 28, 2015 at 2:07 PM Carl-Daniel Hailfinger <
c-d.hailfinger.devel.2...@gmx.net> wrote:
>
I would really like this to be in the tree. It gives us a chance to do
things in coreboot that go beyond C and assembly. So that's my $.02.
What harm would it do?
ron
On Fri, Aug 28, 2015 at 9:00 AM Nico Huber wrote:
> Am 28.08.2015 17:51, schrieb Patrick Georgi:
> > 2015-08-28 17:35 GMT+02:00
ieb ron minnich:
> > This sounds wonderful. I'm all for it.
> Did you just kill any discussion with that line? :)
>
> Things live currently in a small library that I called `libsparkhw`
> (came spontaneously, I don't care much about the name). It contains
> some frame
This sounds wonderful. I'm all for it.
ron
On Fri, Aug 21, 2015 at 1:46 PM Nico Huber wrote:
> Hi coreboot folks!
>
> I dared to link a coreboot ramstage with, well, not only C but also some
> fancy Ada code. Things worked out well enough and I'd like to release
> the code and upstream it.
>
>
it's an ARM. There was a primitive memory test in the early days of our ARM
ports that might be useful. It was simple but it caught our problems.
On Tue, Aug 4, 2015 at 7:18 AM WANG FEI wrote:
> How about MemTest86? See this link http://www.coreboot.org/Memtest86, I
> never use it before.
>
>
yes, they all *seem* like the ought to end up aligned, but they don't :-(
RISCV changed; they can do unaligned loads now.
On Fri, Jul 31, 2015 at 3:26 PM Julius Werner wrote:
> -mno-unaligned-access is ARM32 only, unfortunately. You'd have to
> convince GCC developers to generalize it.
>
> > Th
2) I wrote in because `xl info` in Xen was reporting
> VT-x, but not VT-d, was activated and I was interested in how I could
> activate the former--isn't 0x3a unrelated to VT-d? Hopefully you can
> clarify this for me.
>
> Noah
>
> On 07/24/2015 11:25 PM, ron minnich wrote:
&
w.r.t. the git question, I cloned it too and poked around, doesn't seem to
be anything there
save a few empy branches and a log with one entry.
ron
On Fri, Jul 24, 2015 at 1:33 PM Denis 'GNUtoo' Carikli
wrote:
> Hi,
>
> I just learned about (and watched) a presentation[1] that is about
> backdo
what does rdmsr 0 0x3a show you?
ron
On Fri, Jul 24, 2015 at 10:06 PM Noah Vesely wrote:
> I've been trying to get VT-d working on John Lewis's build for the 2015
> Pixel (samus). You can see our conversation at
> https://plus.google.com/116173342884039282107/posts/TGA4EXYQMfq and I
> have also
Could you also look for LBIO in the e and f segments?
On Sat, Jul 18, 2015 at 12:34 AM Patrick Georgi wrote:
> 2015-07-18 9:03 GMT+02:00 Kevin Wilson :
> > Is there a way, from a device running Linux, to which I have access
> > to the command line, to know
> > whether the BIOS is coreboot or no
we're going to support unaligned accesses, they make it easy. I think it's
silly that have data structs that are not 64-bit aligned, however :-)
ron
On Fri, Jul 17, 2015 at 3:05 PM Julius Werner wrote:
> Is there no way to make RISCV support unaligned accesses? There's a
> bunch of things in co
architecture we're
not on.
goodbye, a = b
hello, memcpy(&a, &b, sizeof(a));
barf.
ron
On Fri, Jul 17, 2015 at 1:23 PM Aaron Durbin wrote:
> On Fri, Jul 17, 2015 at 2:45 PM, ron minnich wrote:
> > riscv is taking alignment traps reading cbfs.
> >
> > The issue
riscv is taking alignment traps reading cbfs.
The issue is that 64-bit fields are 32-bit aligned, which fails many places.
Thaminda found this comment:
* Since coreboot is usually compiled 32bit, gcc will align 64bit
* types to 32bit boundaries. If the coreboot table is dumped on a
* 64bit s
Coreboot is written in C and assembly, with very little assembly. Your best
bet is to build the QEMU target first and just learn how to build, boot,
and change it.
ron
On Fri, Jul 3, 2015 at 12:36 PM francisco dominguez <
francisco.dominguez.ler...@gmail.com> wrote:
> Hi, I'm new, I would like t
Gee, what fun. There are lots of things that can go wrong, to get some
idea, see the
display handling for HP Falco, in which we managed 4 different types of
displays.
I'll try to take a look later, but just keep in mind that the displays are
frequently not all the same
on different production runs
On Wed, Jul 1, 2015 at 7:46 AM wrote:
> Depends .. if the big software company mentioned in the FA sees UEFI as
> *VERY* strategical for its business, what would be the point to be "nice"
> with a project that provides a competing solution of platform
> initialisation code?..
>
The big company o
I can't see that it matters at all.
ron
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So, can someone remind me, is there no native graphics for the T60? I could
have sworn we got there last time we met. Or even in Berlin.
ron
On Sun, Jun 28, 2015 at 7:52 AM Richard Simpson
wrote:
> Carl-Daniel,
>
> I am back in the factory BIOS. I have gathered the data for Łukasz and
> can up
interesting. Not sure what is up here but I have seen that many VGA bioses
copy themselves to RAM and then modify their own code. Actually, I have
seen many BIOSes that do this self modifying code hack; they use it to
change behavior for a warm restart; copy themselves to shadow RAM and then
change
who knows, but we do things to keep gcc happy anyway.
just set phdr to null in the declaration.
ron
On Sat, May 30, 2015 at 11:50 PM Anatol Pomozov
wrote:
> Hi
>
> I am trying to compile coreboot cbfstool on Arch where gcc 5.1 is used.
> And I see following compilation error. I wonder if it is
On Fri, May 8, 2015 at 8:31 AM Aaron Durbin wrote:
>
> I personally feel that changing device_t type based on stage makes the
> code non-obvious and hard to follow.
>
> I'd rather we *always* provide simple u32 device_t functions in all
> stages while allowing struct device IO functions for use i
Oh, yeah, the history of device_t is as old as coreboot v2. It came in ca.
2002 and was part of what made romcc work.
It's not a recent or ill-considered change, to say the least.
ron
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On Thu, May 7, 2015 at 1:42 PM Patrick Georgi wrote:
>
>
>
> One of these days...
>
>
well, that's kind of key ... one of these days. Once we came to that happy
time it might make sense to make this change, but until then, I think we
have to wait. Now I know how to vote.
ron
--
coreboot mailing
>
> one counter-question: is romcc ever going away, or at least is the usage
> gong to change such that no code would ever use the uint32 version of
> device_t?
If it's *never* going away then I think the change makes no sense. If romcc
is going away, then I would favor the change.
ron
--
coreb
The original use of power_on_after_fail was for HPC server nodes that we
wanted to power on after an external power failure without having to go to
1024 nodes and touch a button (this was a real issue at Los Alamos and IIRC
the fix came from Linux NetworX). This is LONG before laptops were a gleam
Paul, would it work to name the verb tables by the vendor,device standard
we use for vga bios and then be able to pick the right one?
e.g. hda8086,1234.tbl or some such?
On Sat, May 2, 2015 at 2:03 PM Michał Masłowski wrote:
> > One of the major differences between the Lenovo T* models is the H
coreboot is a 32 bit binary on x86, still. You should always build the
coreboot toolchain and use it to compile coreboot. What you are reporting
is a common problem for those who do not use the coreboot toolchain.
On Tue, Apr 28, 2015 at 9:03 PM sibu wrote:
> Greetings,
>
> I am new to this list
Does someone have 1234 as a password?
On Wed, Mar 25, 2015, 23:41 Kushagra Kumar wrote:
> Love u all m dying to cm back
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
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Interesting. I had not used fedora for coreboot for a long time. Nobody I
know in chromeos does either.
On Wed, Mar 25, 2015 at 7:28 PM mrnuke via coreboot
wrote:
> On Thursday, March 26, 2015 07:43:26 AM Kushagra Kumar wrote:
> > Which is the best Linux based os to be worked on with coreboot?
>
On Wed, Mar 25, 2015 at 7:19 PM ron minnich wrote:
> It's been a long time since that mattered. Just be sure to build the linux
> toolchain.
>
>
>
Er, "coreboot toolchain"
sorry
ron
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It's been a long time since that mattered. Just be sure to build the linux
toolchain.
On Wed, Mar 25, 2015 at 7:15 PM Kushagra Kumar
wrote:
> Which is the best Linux based os to be worked on with coreboot?
> --
> coreboot mailing list: coreboot@coreboot.org
> http://www.coreboot.org/mailman/list
On Tue, Mar 24, 2015 at 7:15 AM Kushagra Kumar
wrote:
> Try somehow to check the partions acctually this happens due to error in
> partition loading during booting process in general.a good firmware should
> have capability to repair this error at initial stage
>
I don't understand your descrip
On Mon, Mar 23, 2015 at 4:18 PM Kevin O'Connor wrote:
> Just to be clear, it's fine to try initializing the video card in
> SeaBIOS, it's fine to try initializing the video card in coreboot, and
> it's fine to try and hold off initialization until Linux starts. But,
> definitely don't try bootin
Nice job, documents are almost always full of errors :-)
Any way you can create a patch for some part of some code base? This email
will be forgotten quickly and we want
your hard-earned knowledge :-)
ron
On Mon, Mar 23, 2015 at 10:43 AM Naresh G. Solanki <
naresh.solanki.2...@gmail.com> wrote:
A good first pass is to enable YABEL instead of native execution and watch
what it does. That's how I've had to debug graphics before.
Also, if you can do a serial console only setup, you can run the VBIOS once
linux is booted and try to debug it that way.
It's very hard to debug a VBIOS issue as
On Fri, Mar 13, 2015 at 5:27 AM wrote:
> Ok Ron,
> We all recognise your efforts and don't deny that the question of the
> binary blobs" is a very complex and "politicaly hot" one..
> But (and I speak here from a STRICTLY personal point of view) it is the
> fashion you chose to lecture Paul than
On Fri, Mar 13, 2015 at 4:41 AM wrote:
> Sorry Ron,
> What is his crime?
> Thought crime?..
> Florentin
>
>
The problem with people making comments like this:
> > Sadly, I don’t think Google has understood how much power they have over
> > Intel with their Chromebook and Chromebox success. RAM
On Fri, Mar 13, 2015 at 12:42 AM Paul Menzel <
paulepan...@users.sourceforge.net> wrote:
>
>
> Sadly, I don’t think Google has understood how much power they have over
> Intel with their Chromebook and Chromebox success. RAM initialization is
> for example still a BLOB and, instead of getting Inte
On Thu, Mar 12, 2015 at 3:48 PM Paul Menzel <
paulepan...@users.sourceforge.net> wrote:
>
>
> As this is an Intel device [1] and I am waiting for an AMD based laptop,
> I’d say no. ;-)
>
>
>
I'm not sure AMD improves the situation much any more, and in some ways a
non-chromeos laptop has lots of
I think it would be pretty cool. I think we should try it.
On Thu, Mar 12, 2015 at 1:09 PM Carl-Daniel Hailfinger <
c-d.hailfinger.devel.2...@gmx.net> wrote:
> On 12.03.2015 19:55, ron minnich wrote:
> > Given all the high-tech ability in this group, I wonder if a joint,
> >
Given all the high-tech ability in this group, I wonder if a joint,
transglobal, meeting using gvc from san jose to whereever would work :-)
ron
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I don't understand why you think we need a "legacy BIOS for minnowboard"
given what this group has been doing for the last 15 years.
On Mon, Mar 9, 2015 at 4:24 AM Corey Osgood wrote:
> He's trying to advertise his company's legacy BIOS solution.
>
> -Corey
>
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I don't know what you mean, sorry.
Ron
On Mon, Mar 9, 2015, 00:58 Berth-Olof Bergman
wrote:
> Hi,
>
> Seems you need a legacy BIOS for minnow board max. With legacy BIOS you
> can run 16, 32 and 64 bit operating systems. We have the fastest booting
> BIOS for the Bay Trail architecture and it’s
-- Forwarded message -
From: lowRISC Announcements
Date: Sun, Mar 8, 2015 at 1:52 PM
Subject: lowRISC in Google Summer of Code 2015
To:
We're pleased to announce that lowRISC is taking part in Google Summer of
Code
as a mentoring organisation. We're working with a number of our
>
> Does this count as common sense?
http://review.coreboot.org/#/c/8602/
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>
> http://review.coreboot.org/#/c/8602/
>
If this works I'll update the wiki.
ron
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On Wed, Mar 4, 2015 at 6:10 AM Patrick Georgi via coreboot <
coreboot@coreboot.org> wrote:
> 2015-03-04 14:58 GMT+01:00 Peter Stuge :
> > I haven't gotten the impression that anyone is suggesting to remove
> > or even change any copyright notices.
> >
> > Copyright documents authorship (like git d
On Tue, Mar 3, 2015 at 7:32 PM Julius Werner wrote:
>
>
> IANAL (I'm not giving legal advice, yada yada), but I don't think that is
> how this works. Companies you don't work for can't force you to do X or
> prevent you to do Y with their files.
>
Copyright statements are pretty complicated, and
On Tue, Mar 3, 2015 at 9:42 AM Peter Stuge wrote:
> ron minnich wrote:
>
>
> Every project *does* however get to decide on formal requirements for
> all contributions, and reject contributions which fail to meet those
> requirements.
>
And that's an excellent poin
On Tue, Mar 3, 2015 at 12:06 AM Paul Menzel <
paulepan...@users.sourceforge.net> wrote:
> Am Dienstag, den 03.03.2015, 00:06 -0600 schrieb Alexandru Gagniuc:
>
>
> In the past Ron also disagreed on changing headers by Samsung – taken
> from U-Boot I think – saying their lawyers drafted those and t
We've had this discussion before, many times. I've pointed out many times
it can be easy, using a form that's now over 20 years old. This is taken
from linux.
* * Copyright 1993 United States Government as represented by the
* Director, National Security Agency.
*
* This software
Very nice. I like the one on the left best.
On Tue Feb 24 2015 at 8:52:26 AM Peter Stuge wrote:
> Stefan Tauner wrote:
> > logo with half of the rotation attached (15° instead of 30° backwards).
>
> I really like this one. Nice!
>
>
> //Peter
>
> --
> coreboot mailing list: coreboot@coreboot.org
Wow, I love these, and I agree with peter's ideas too. This is great.
On Sat Feb 21 2015 at 5:27:35 PM Peter Stuge wrote:
> Peter Stuge wrote:
> > Stefan Tauner wrote:
> > > What do you think about my suggestions and the whole matter?
> >
> > soic8_30degrees is really good. I would only suggest
Well, I say it again: it matters not. I don't care how we do it, some ox is
going to get gored.
The order is much less important than consistency. And ox are tasty. So
let's gore one.
The problem for me is not that I have an opinion, but that people I
respect so highly have
different opinions. Ho
Having spent 15 or so years on Plan 9 and Linux, the only conclusion I can
make is that nothing is universal.
Plan 9 is this:
outl(int port, ulong value)
And I used software that came long before Linux (back in the 70s, if you
want to know) that followed that form too. I think Linux got it backwa
This would be a great GSOC project to finish it up.
Really nice work!
ro
On Tue Jan 20 2015 at 9:09:12 PM Scott Duplichan wrote:
> ron minnich [mailto:rminn...@gmail.com] wrote:
>
> ]Sent: Sunday, August 10, 2014 06:34 PM
> ]To: Marc Jones
> ]Cc: Scott Duplichan; coreboot
see it here: https://www.youtube.com/watch?v=yE_PMcwltzo
Great job!
ron
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coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
nvm. bitrot fixed.
On Wed Dec 31 2014 at 7:38:40 PM ron minnich wrote:
> and things are a mess.
>
> Why is ARM_LPAE appearing when I'm selecting riscv?It's at the top level.
>
> Anybody know why, once I have used menuconfig to set things up, and then
> run make, it
and things are a mess.
Why is ARM_LPAE appearing when I'm selecting riscv?It's at the top level.
Anybody know why, once I have used menuconfig to set things up, and then
run make, it starts all over again? This all used to work.
I can't ever get past make config, it seems, each time I run make I
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