Re: [coreboot] coreboot hackaton/meeting in Prague - september 2014 - date shift?

I like that date, it fits really well with ELC. ron On Mon, Jun 30, 2014 at 11:04 PM, Rudolf Marek wrote: > Hi all, > > What about 16 17 18 19 of October then? It is already in the university > semester so there could be trouble with dormitory accommodation, but I > think no trouble with some

Re: [coreboot] coreboot hackaton/meeting in Prague - september 2014

Yeah, that's a great idea. ron On Mon, Jun 30, 2014 at 3:53 PM, David Hendricks wrote: > On Sun, Jun 29, 2014 at 2:06 PM, Rudolf Marek > wrote: > >> Hi all, >> >> First of all sorry that it took so long to get back to this. >> >> I have in plan to organize a coreboot meeting in the Prague on

Re: [coreboot] Improvement of coreboot code (was: latest baytrail fsp on CRB)

On Sat, Jun 21, 2014 at 5:17 AM, Karl-Heinz Nirschl wrote: > But anyway - the real statement of the message meant to be: "thanks for > all the good code". > > > > That's very kind of you. I think you are right about the code, it has improved a lot in the last couple years. ron -- coreboot maili

Re: [coreboot] setting smbios values from the OS

On Fri, Jun 20, 2014 at 11:20 PM, Patrick Georgi wrote: > > > In the end, I pose the question why a serial number must be exported to > the OS in the first place - this looks like a potential privacy issue to > me, while doing nothing for servicing the part (if it's sent back, read > the bar code

Re: [coreboot] setting smbios values from the OS

On Fri, Jun 20, 2014 at 10:00 PM, Scott Duplichan wrote: > > > Putting the serial number in the same flash chip as the main > firmware is a cost reduction measure used with desktop and other > low cost boards. I have even seen a board where the MAC address > lives there. The only protection for t

Re: [coreboot] setting smbios values from the OS

realistically, though, it's hard for me to see how setting the serial # at firmware image build time scales. And setting it after boot makes no real sense either -- it's not really a serial number if you're changing it at that point. But some way to customize the binary images with a serial number

Re: [coreboot] Intel native graphics init: Questions about GTT setup: Decode error on Lenovo X60

Folks, do I correctly understand this regression is X60-only? In that case, I suspect there will not be lots of interest in fixing it from the kernel side :-( sorry ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Intel native graphics init: Questions about GTT setup: Decode error on Lenovo X60

BTW, as you'e seen, the data sheets are less than helpful. But the driver is usually worth looking at. My contact at Intel tells me he's not seeing what you're seeing, so we need a way to reproduce your setup and see what's going on. ron On Mon, Jun 9, 2014 at 7:15 AM

Re: [coreboot] Intel native graphics init: Questions about GTT setup: Decode error on Lenovo X60

It's painful and awful to do, but when you get that error, I suggest you mod the driver to hexdump the ENTIRE gtt. You need to see what's going on there. It's possible that somehow the gtt and gsm are living in the same place and the chipset is corrupting its own gtts. ron -- coreboot mailing li

Re: [coreboot] Intel native graphics init: Questions about GTT setup

On Mon, Jun 9, 2014 at 6:00 AM, Paul Menzel < paulepan...@users.sourceforge.net> wrote: > Dear Ron, > > > > > Please also note, that at least since Linux 3.11, Linux is not able > anymore to set up graphics without the Video ROM or native graphics > init. Unfortunately, nobody bisected this yet or

Re: [coreboot] Intel native graphics init: Questions about GTT setup

Does anybody want to have a go at a further interpration of the errors? That would help. Does this error mean a present bit was not set, or the address was wrong, or ... ron On Sun, Jun 8, 2014 at 4:40 PM, Anthony Martin wrote: > Paul Menzel once said: > > since Linux 3.12+ graphics stolen me

Re: [coreboot] Intel native graphics init: Questions about GTT setup

Paul, many good questions. The problem is I did all this over 2 years ago and the answers won't be as good. Vladimir and Peter will likely do better. And, to reiterate, the 'replay attack' code for Link is not a good example of how to start graphics. It Just Worked, but not well. The second iterati

Re: [coreboot] Intel FSP on Bayley Bay CRB: No output

On Wed, Jun 4, 2014 at 1:57 PM, Martin Roth wrote: > There are a number of issues here: > > > > 3) The way that the microcode is currently being included is (to my > understanding) completely against the Intel licensing. We're compiling a > .h file with a license that says that it *CANNOT* be ma

Re: [coreboot] Intel FSP on Bayley Bay CRB: No output

On Wed, Jun 4, 2014 at 11:59 AM, WANG FEI wrote: > I thought microcode files are kind of patches for CPU, it suppose to be > loaded before MRC just in case it fixes any issues related with CPU. I > actually did encounter an system random halt issue related with no loading > microcode before MRC t

Re: [coreboot] MB-A180 based design - First Light

Congrats! ron On Wed, Jun 4, 2014 at 9:25 AM, Mark C. Mason wrote: > > We are running Linux from Coreboot this morning, after adding > a bootable device on the SATA port. > > The USB boot devices were never seen, so more work to do there. > > Thank you for all your help! > > > Best regards, >

Re: [coreboot] Intel FSP on Bayley Bay CRB: No output

On Wed, Jun 4, 2014 at 1:11 AM, Gerald Otter wrote: > > > Just for my own understanding; is it common for microcode loading to be > required as part of the booting process, as opposed to being optional > updates? > > Yes. Long ago, we let the kernel load microcode. Then, at some point, on some C

Re: [coreboot] Naming for identical chips with different model numbers due to different package variants

Peter, I completely agree. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Naming for identical chips with different model numbers due to different package variants

And never forget, no matter how many times we try to get this right, some vendor will come up with a way to break a naming scheme. Happens every time. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] IMB-A180 based design - help with post codes

I'd drop every other thing you're doing and get that usb debug port going. It will save your mind. But, yes, it seems you're getting pretty far. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] pre-2009 Coreboot-compatible laptops?

I thought you had to go further back than 2009 to get pre-AMT chipsets, was I wrong on that? ron On Thu, May 29, 2014 at 4:44 PM, Silkie Carlo wrote: > Hi guys, > > I do hope you can help me! I am working on an infosec project at the > moment, trying to fight the good fight... > > I see Coreb

Re: [coreboot] booting vxworks from linux BIOS

There was a time, quite some time ago, when somebody was booting vxworks from linuxbios, i.e. it was the payload. ron On Thu, May 22, 2014 at 6:55 AM, Stojsavljevic, Zoran wrote: > Hello Peter, > > I'll try to find answers to these questions. I might even myself build one of > these images to t

Re: [coreboot] Booting an EFI OS

I certainly like seeing the words 'mortem' and 'EFI' in the same email ;-) -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Booting an EFI OS

what's an "EFI OS"? ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] PIC instead of APIC mode for KolibriOS - mouse fix

On Tue, May 13, 2014 at 5:29 AM, Peter Stuge wrote: > That's an important question, but I believe the answer is no. That's all I wanted to know, to start. So why don't we just get that CL in and see where we go from there. Thanks all. And sorry if I was too hard on kolibrios. It's totally wond

Re: [coreboot] PIC instead of APIC mode for KolibriOS - mouse fix

Like I say, if it's not going to do harm, and you all want it, submit the CL. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] PIC instead of APIC mode for KolibriOS - mouse fix

On Mon, May 12, 2014 at 12:13 PM, Peter Stuge wrote: > Why shouldn't coreboot do legacy initialization? What is the reason > to be *less* compatible than possible? The main question I had was whether enabling this set of interrupts could negatively impact other payloads. The goal of linuxbios an

Re: [coreboot] coreboot at the LinuxTag 2014 in Berlin: Visit our booth at the community day this Saturday!

Sorry to miss it! Take many pictures! ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] FSP, SNB, and a new board

Oh no, I don't want to try FSP, I just want to do the thing that's the least work for me, and it sounds like Google mrc.bin is what I want, since I know where to find it :-) Thanks ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] FSP, SNB, and a new board

How good is the FSP code with a new board? I have an SNB board and I'm curious as to how much blood will be on the walls if I try to use an FSB-based coreboot image with it. SNB = my weird way of saying sandybridge ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mai

Re: [coreboot] The Novena Open Laptop + Coreboot?

IT will probably run u-boot, so free is solved. But, wow, I think the price to what-you-get ratio on that thing is not attractive. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] PIC instead of APIC mode for KolibriOS - mouse fix

Thanks, that's a great explanation. Generally, we've tried to avoid too much hardware setup in coreboot; that's the job of the kernel. I'm not really happy that we're doing all this PIC setup for one OS, written in assembly. It's been quite some time since I've had to use PIC mode at all. Why can'

Re: [coreboot] PIC instead of APIC mode for KolibriOS - mouse fix

So, how would these changes affect other payloads? ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] New addendums to INTEL FSP family (ron minnich)

Jiming, why doesn't intel just put that more open stuff up on github and be done with it? ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Life hack #37: how to make a great touchpad

well, you may not like the missing trackpoint, but a couple million chromebook and macbook users are doing just fine. It's all about the numbers. ron On Sat, May 3, 2014 at 2:52 AM, Stefan Tauner wrote: > Alex, you have missed something very important here: > 0: Look at any Chromebook, notice t

[coreboot] USB tick in SMM?

Anybody out there know typical numbers for the timer tick if USB is active as part of SMM? I just heard one number for one product line, 8 HZ. We're seeing a mysterious 18 HZ tick on one system. Any other numbers people know? thanks ron -- coreboot mailing list: coreboot@coreboot.org http://ww

Re: [coreboot] Life hack #37: how to make a great touchpad

coreboot on chromebooks are very on topic. Track pad drivers for Linux, or the trackpad firmware, or the trackpad vendor, or the algorithms used, or the fact that you made this comment in such a way that nobody from the trackpad group will see it, or that it's pretty rude on top of that, not so muc

Re: [coreboot] Life hack #37: how to make a great touchpad

well, as long as we're off topic, the El Patron restaurant in Albuquerque was quite good. And it looks like the new Fit is a great car, although I still think the 2007 model year had more of a road feel. Oh, wait, what mailing list is this again? I thought it was the ~coreboot list. ron -- cor

Re: [coreboot] Bug in your code

a better solution. > > > On Fri, Apr 18, 2014 at 4:52 PM, Aaron Durbin wrote: >> >> On Fri, Apr 18, 2014 at 9:49 AM, ron minnich wrote: >> > Can somebody give me a sanity check? I can't see the error with the >> > macro. >> > I w

Re: [coreboot] Bug in your code

Fooey. Now they all look wrong. I think the macro maybe should be defined as makemagic(b0,b1,b2,b3) the thing I can't figure out is why this ever worked. OK, off to the dentist, ... ron On Fri, Apr 18, 2014 at 8:34 AM, ron minnich wrote: > Which of course means my code IS wrong,

Re: [coreboot] Bug in your code

Which of course means my code IS wrong, but the suggested fix is wrong too I think. ron On Fri, Apr 18, 2014 at 8:34 AM, ron minnich wrote: > Still not seeing it. > > I think the order should be > ' ', 'S', 'S', 'B' > > not '

Re: [coreboot] Bug in your code

Still not seeing it. I think the order should be ' ', 'S', 'S', 'B' not ' ', 'B'','S','S' or 'B','S','S',' ' i.e. space is the high order byte. ron On Fri, Apr 1

Re: [coreboot] Bug in your code

Can somebody give me a sanity check? I can't see the error with the macro. I won't say too much here -- just take a look. I'm not convinced the code is wrong. thanks ron On Fri, Apr 18, 2014 at 7:39 AM, WANG FEI wrote: > Ronald, > > I just noticed a bug in your code, I've added the comment to c

Re: [coreboot] Blog post by Scott D.: Small Integers: Big Penalty

Paul, very nice, thanks. It's not real surprising, actually, at least in my old scientific computing world. Since that is AMD code, maybe we can get the guys who wrote it to read that nice book written by AMD :-) ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailma

Re: [coreboot] So, you want to try coreboot? Here are a few hints

And a little warning here. This is the PC business, and the version control on hardware is just terrible. So, you may have a board called the blackrock m23551-rev 3/Z, and somebody else may have the blackrock m23551-rev 3/Z, and they may be utterly different, because you bought yours on a saturday

Re: [coreboot] Wyse S10 Geode GX2

I'm a huge fan of tinycore. So, could we ever have tinycore in flash? Man that would be nice. Talk about instant on! ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] AMD doesn't get it either in some ways (the bastards!!!)

And here's where we thank Intel, btw. They've done a truly wonderful job of getting code into the Linux kernel that I was able to use to open up chipset init for sandybridge, ivybridge, and haswell, A tip of the hat to Intel and Jesse Barnes especially for all they've done in that area. So let's k

Re: [coreboot] AMD doesn't get it either in some ways (the bastards!!!)

On Fri, Apr 4, 2014 at 5:28 PM, mrnuke wrote: > That's just a reference to South Park. Which would be fine if everyone on this list was a native English speaker and knew what South Park was. Else, they could naturally take offense, so please keep that in mind. While I think I share your acid se

Re: [coreboot] AMD doesn't get it either in some ways (the bastards!!!)

Now, there's no need to be that mean, ok? AMD are not bad guys in my view. But they have made some seriously boneheaded decisions, and locking up the VGA bios is one of them. We can't get anywhere calling people names like this. ron -- coreboot mailing list: coreboot@coreboot.org http://www.cor

[coreboot] AMD doesn't get it either in some ways

I have this nice board, with a nice AMD cpu, and I get no graphics. Why? Because AMD won't release the VGA blob. So the board is headless. Another addition to the blob matrix. sigh. It's really not that just one vendor is bad and one is good. AMD has its issues too. It's a wonder I have any teet

Re: [coreboot] New addendums to INTEL FSP family

On Wed, Apr 2, 2014 at 10:17 AM, David Hubbard wrote: > Could the two interested parties negotiate a compromise? In my mind that's > Google calling Intel, and they talk it over. That probably just demonstrates > how little I understand about who and what is involved. Goodness, you think that has

Re: [coreboot] New addendums to INTEL FSP family

On Wed, Apr 2, 2014 at 10:15 AM, mrnuke wrote: > $ git grep -i intel |grep -i copyright |grep -v microcode Point being? ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] New addendums to INTEL FSP family

On Wed, Apr 2, 2014 at 9:38 AM, mrnuke wrote: > That is a clear attempt to circumvent the > wishes of the rightsholders to this project. > That part I believe you are missing here is that this is a balancing act. The vendors are rightsholders too. They have knowledge we need. Unfortunately, mos

Re: [coreboot] New addendums to INTEL FSP family

This license still looks problematical to me. Couple that with the fact that the Haswell MRC is still not generally available from Intel and I'm a bit concerned. If I build a coreboot image with FSP, am I allowed to put it on dropbox for others to try out? Not clear at all! And, "one backup copy"

Re: [coreboot] ThinkPad T60p coreboot config file

On Wed, Mar 26, 2014 at 5:00 PM, Thom Lauret wrote: > That disassembly is > required to identify the flash chip is going to slow coreboot adoption. um, what? ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [announce] coreboot for the 21st century

On Sat, Mar 29, 2014 at 12:30 AM, Vladimir 'φ-coder/phcoder' Serbinenko wrote: > Do I get it correctly that your main problem is the heavy use of > #include romcc requires? no ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Classification of blobs and respecting your freedom

Ah, that's what I meant by persistent. Let's take your name and get rid of mine, and we're still at 2 axes? ron On Wed, Mar 26, 2014 at 12:40 PM, David Hendricks wrote: > On Wed, Mar 26, 2014 at 12:29 PM, ron minnich wrote: >> >> I agree with david. >> >

Re: [coreboot] Classification of blobs and respecting your freedom

I agree with david. Simple classifications are better. I think I found two axes. persistent replacable persistent and not replaceable --> this system may not be usable non-persistent and not replaceable --> requires a close look replaceable --> we're ok with enough effort are there more? ron

Re: [coreboot] Classification of blobs and respecting your freedom

I think it's good and well written. I'd replace your 'panic levels' with 4 simple classifications and leave it at that. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] A new, modern coreboot long-term support laptop

what kind of EC? and other questions ... ron On Wed, Mar 26, 2014 at 2:01 AM, Niels Ole Salscheider < niels_...@salscheider-online.de> wrote: > > Anyone has any experience with the AMD ProBooks? Are they built to last, > or > > are they crap? > > I have a HP ProBook (6465b, I think) with a Llan

Re: [coreboot] A new, modern coreboot long-term support laptop

On Tue, Mar 25, 2014 at 1:26 PM, David Hendricks wrote: > On Tue, Mar 25, 2014 at 12:17 PM, mrnuke wrote: > >> On Tuesday, March 25, 2014 12:03:28 PM David Hendricks wrote: >> > On Tue, Mar 25, 2014 at 10:57 AM, mrnuke wrote: >> >> I'm assuming BLO is not persistent. >> > > It's been a while sin

Re: [coreboot] A new, modern coreboot long-term support laptop

On Tue, Mar 25, 2014 at 12:09 PM, mrnuke wrote: > > There's already been more action in the last few days than in the last few > years. We've rounded up a first batch of candidates, got interested people > pledging coding effort, and even a pledge for financial support. We got > some > of the lib

Re: [coreboot] A new, modern coreboot long-term support laptop

Just one thing. Don't underestimate just how miserable the EC can make your life. I place a high premium on systems with an open EC. Just be careful there. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Expectations, project direction and interest of contributors

On Mon, Mar 24, 2014 at 10:58 PM, Kyösti Mälkki wrote: > > > coreboot- Mon Apr 29 15:07:52 PDT 2013 starting... > > > That is, it appears the revision information seems to be intentionally > wiped from the string logged in CBMEM console there. That's a heck of an assumption. You did not see it

Re: [coreboot] Changes to the coreboot Project Structure

On Mon, Mar 24, 2014 at 10:37 PM, Vladimir 'φ-coder/phcoder' Serbinenko < phco...@gmail.com> wrote: > > That's why I added *supposed to*. I'm aware that some boards are > probably broken and not much we can do about it. > > Except remove them, right? ron -- coreboot mailing list: coreboot@coreb

Re: [coreboot] Changes to the coreboot Project Structure

On Mon, Mar 24, 2014 at 10:20 PM, Vladimir 'φ-coder/phcoder' Serbinenko < phco...@gmail.com> wrote: > > I don't see how this prevents any of my propositions for the bulk of the > boards. The problem you describe isn't going away with your proposition. > We still want to have a top which is suppose

Re: [coreboot] A new, modern coreboot long-term support laptop (was: Expectations, project direction and interest of contributors)

On Mon, Mar 24, 2014 at 9:10 PM, mrnuke wrote: > > > > [slightly OT, feel free to skip] My stance on blobs is a little weird. I > try > to make sure I have full control of my system. If the blob cannot do any > harm > to my freedom, or in other words, respects it, then that blob is > acceptable.

Re: [coreboot] Expectations, project direction and interest of contributors (was: Changes to the coreboot Project Structure)

I keep wanting to drop out of this discussion but there are some things I just can't let go by, On Mon, Mar 24, 2014 at 4:20 PM, Paul Menzel < paulepan...@users.sourceforge.net> wrote: > > > First I find "wildest expectations" a little exaggerated seeing the > blobs (especially ME) shipped in al

Re: [coreboot] Changes to the coreboot Project Structure

On Sat, Mar 22, 2014 at 11:34 PM, Vladimir 'φ-coder/phcoder' Serbinenko wrote: > On 23.03.2014 04:10, Peter Stuge wrote: >> That isn't too different from creating a fork? > Fork is better. With fork we don't have to deal with the same people who > pushed the community out in the first place. Vlad

Re: [coreboot] [announce] coreboot for the 21st century

If you're going to make big changes to what happens at coreboot.org, you have to get buyin from the folks who do all the work. I'm not the right person to propose this to :-) Put simply, it's above my pay grade. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman

Re: [coreboot] [announce] coreboot for the 21st century

On Fri, Mar 21, 2014 at 4:50 PM, David Hubbard wrote: > I've been thinking about it all day and it seems Vladimir is pretty much > spot on, "The proposition of gatekeepers would essentially kill community > effort." There's just something I'm clearly not understanding here. For the first year o

Re: [coreboot] [announce] coreboot for the 21st century

On Fri, Mar 21, 2014 at 6:52 PM, Alex G. wrote: > The bad-ness or good-ness of motives is relative. Note that I'm not > using "bad" in the sense of "evil". Let's look at the six gatekeeper idea: > * Easier for commercial entities to upstream code, therefore faster > progress for coreboot (good m

[coreboot] ioapic dump tool

anybody know of a tool to dump all apics/ioapics from user mode? I'm having a Very Stupid Problem with a research OS in that we can't get the apic's and or iopiac's working. I suck at these things. We can't tell what we've got wrong.I'm hoping a register dump would help us. ron -- coreboot mail

Re: [coreboot] [announce] coreboot for the 21st century

On Fri, Mar 21, 2014 at 1:33 PM, mrnuke wrote: > On Saturday, March 22, 2014 03:56:46 AM Andrew Wu wrote: >> Yes, that is right. DMP/Vortex86EX has no MTRR. So it maybe a problem >> if without romcc. :( > > Is there any way whatsoever to temporarily use the cache as SRAM? when we did the first re

Re: [coreboot] [announce] coreboot for the 21st century

On Fri, Mar 21, 2014 at 7:55 AM, Vladimir 'φ-coder/phcoder' Serbinenko < phco...@gmail.com> wrote: > > I suppose that most of boards were contributed by non-commercial > community. It's much more complicated than that. The initial support for coreboot came from DOE. SiS gve a lot of support with

Re: [coreboot] Changes to the coreboot Project Structure

ah, blush, somebody wants me to be dictator. However, I can't do it. First off, if you're not going to let me invade some country, it's no fun. Secondly, it's hard to find Dictator clothes that look good on me. Just won't work. Thirdly, Stefan has been doing this very well for at least 7 years, a

Re: [coreboot] [announce] coreboot for the 21st century

No, I think this is a good first step, and we'll learn a lot in the act of removing them. I think if we ever CONFIG_ANNOYING_CHIPSET anything, we remove the chipset :-) ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [announce] coreboot for the 21st century

I like this, I just wish we could remove more boards :-) ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] GSoC-2014 Coreboot project

On Thu, Mar 20, 2014 at 9:41 AM, mrnuke wrote: > Not sure I care much about Intel nowadays. They are already part of the > "fellatio_admin" group in my books. No offense intended, but your cares in this case are of no real importance compared to the cares of the companies that are shipping O(1M)

Re: [coreboot] GSoC-2014 Coreboot project

On Thu, Mar 20, 2014 at 9:33 AM, mrnuke wrote: > On Thursday, March 20, 2014 09:08:18 AM ron minnich wrote: >> On Thu, Mar 20, 2014 at 8:36 AM, mrnuke wrote: >> > BTW, has any manufacturer been hostile in the past in any way relating to >> > coreboot supporting hard

Re: [coreboot] GSoC-2014 Coreboot project

On Thu, Mar 20, 2014 at 8:36 AM, mrnuke wrote: > BTW, has any manufacturer been hostile in the past in any way relating to > coreboot supporting hardware they would rather have kept closed/secret? ha ha ha ha ha ha ha ha ha ha ha haha ha ha ha ha haha ha ha ha ha haha ha ha ha ha haha ha ha ha h

Re: [coreboot] GSoC-2014 Coreboot project

put in the proposal. We'll deal with other issues later. The guy that gave us the first real CAR implementation was an intel employee who had NDAs out the ... and it was not an issue. Let's not start putting in roadblocks. We're not lawyers. ron -- coreboot mailing list: coreboot@coreboot.o

Re: [coreboot] GSoC-2014 Coreboot project

well, vladimir, I would not be so discouraging. In fact if it is an existing mainboard, and you have not done coreboot before, I suggest doing a port, and then doing something new with the port. I'd like somebody to look at doing LinuxBIOS again, i.e. getting us back to the point where we can emb

Re: [coreboot] Python versioning

I'm so tired of python. I hit this all the time and not just on coreboot. Easy fix sudo mount --bind /usr/bin/python2 /usr/bin/python Done ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [RFT] Please test patch set intel/i945: Only write CID, PN and TCID once

First, Mono, thank *you* for your interest and involvement in coreboot. On Sun, Mar 16, 2014 at 2:00 PM, Mono wrote: > Moreover, I was not aware that the code might do something else than what > one can know by reading the code and the public documentation. To be > honest, if that was true, I w

Re: [coreboot] [RFT] Please test patch set intel/i945: Only write CID, PN and TCID once

So do I understand it correctly, that this patch is for hardware that has been working, in some cases for 5 years; that it has been written after reading a public doc; and that it was not developed in response to a known bug or issue? Code that does not conform to a public doc is NOT a bug. A wor

Re: [coreboot] I've turned on paging as a test

On Sat, Mar 15, 2014 at 11:31 AM, Kevin O'Connor wrote: > > > I suspect the pain of mapping files in CBFS to different virtual > addresses is greater then the pain of having files in CBFS at static > addresses. > I'm happy to verify it either way :-) You won't have to feel my pain :-) ron --

Re: [coreboot] Following the instructions on the NXM page causes problems

ot;This signature fought the Time Wars, time and again." > > > On Sat, Mar 15, 2014 at 2:10 PM, ron minnich wrote: > > NxM is done. We took it down last year. > > It's no longer available via coreboot.org > > > > If you're still interested in giving

Re: [coreboot] Following the instructions on the NXM page causes problems

NxM is done. We took it down last year. It's no longer available via coreboot.org If you're still interested in giving it a try, https://github.com/rminnich/NxM On Sat, Mar 15, 2014 at 10:49 AM, Gregg Levine wrote: > Hello! > I just tried to retrieve the latest NXM code via git. Instead of

Re: [coreboot] I've turned on paging as a test

On Sat, Mar 15, 2014 at 10:22 AM, Kevin O'Connor wrote: > > > Agreed. I don't see any problems with a 1:1 page mapping where it's > useful. > > me neither. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] GSoC-2014 Project for Coreboot

On Sat, Mar 15, 2014 at 10:02 AM, Kevin O'Connor wrote: > > > The coreboot code's interaction with the "filesystem" after memory > init (should) largely boil down to load_file(char *name, void > *address, int maxsize). Why not just end the abstraction there (ie, > on these arm devices, implement

Re: [coreboot] CBFS bullfart (forked from GSoC-2014 Project for Coreboot)

You're going where we were in 2000. Many of us have been here before. We'd have killed to have the 40K of space you have on the ARM. We were doing this with either just the register set or a 16-register scratchpad. And we solved it with a streaming abstraction. So the argument that we're somehow x

Re: [coreboot] CBFS bullfart (forked from GSoC-2014 Project for Coreboot)

Just to step back here. The flash is 8M. The system has 4G. What do I care if I leak memory? What's the issue you are solving? ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] GSoC-2014 Project for Coreboot

On Fri, Mar 14, 2014 at 9:23 AM, Naman Govil wrote: > > > I agree with the long term goal, but from the point of view of a project > in GSoC, is'nt it better for me to implement the block device API first, > and then in the course of time think about the generic device interface? > > > you shoul

Re: [coreboot] GSoC-2014 Project for Coreboot

On Fri, Mar 14, 2014 at 8:14 AM, Patrick Georgi wrote: > Am Freitag, den 14.03.2014, 08:07 -0700 schrieb ron minnich: > > There's not much point in fighting the tide here. The idea of > linux-as-bios > > was nice, but we have come to the point where linux-as-bios requir

Re: [coreboot] GSoC-2014 Project for Coreboot

We've been kind of holding off on this, but, fact is, coreboot has followed the well trod path of firmware everywhere and become a small kernel. It started as little more than memcpy with a frisson of I2C packet IO thown in, but thanks to the generous ideas of hardware designers everywhere, with ev

Re: [coreboot] Friendly reminder: Please just send plain text messages to the list

Works for me, but then what would we talk about :-) ron On Wed, Mar 12, 2014 at 11:38 AM, Peter Stuge wrote: > mrnuke wrote: > > Why don't we just configure the mail server to reject messages containing > > HTML? > > I'd welcome that policy, and it is common on many lists. > > > //Peter > > --

Re: [coreboot] Friendly reminder: Please just send plain text messages to the list

And i was joking. ron On Wed, Mar 12, 2014 at 10:50 AM, Xavi Drudis Ferran wrote: > I hesitate to make this thread longer... > > Just my 2c. > > HTML - please no. > > It's bloated for this purpose and I've seen it (outside this list) > introduce costly errors because of that. It brings new feat

Re: [coreboot] I've turned on paging as a test

Good point. On Wed, Mar 12, 2014 at 10:12 AM, David Woodhouse wrote: > On Mon, 2014-03-10 at 16:41 -0500, Jonathan A. Kollasch wrote: > > On Mon, Mar 10, 2014 at 02:33:41PM -0700, ron minnich wrote: > > > And locked out page zero. And we trap. > > > > >

Re: [coreboot] I've turned on paging as a test

On Wed, Mar 12, 2014 at 9:07 AM, Peter Stuge wrote: [on arm] > Why is it helpful or neccessary there? It only matters if you like to have a dcache. Do you want a dcache? You must turn on paging. On PPC, you have no choice, you can't turn off the soft TLBs on the new ones. So, you want PowerPC

Re: [coreboot] Friendly reminder: Please just send plain text messages to the list

Dear coreboot folks, lately even long time contributors started to send messages to the list, which were not just plain text but included UTF-8. Besides that UTF-8 for text only adds advantage in rare cases, it also increases message size, since it can grow the size of a single printable charact

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