Issue #508 has been updated by Yu-Ping Wu.
Arthur Heymans wrote in #note-3:
> I don't understand the hardware however I tried to look at the soc code.
> In soc/mediatek/common/pcie.c I see the following:
>
> write32p(table, mmio_res->cpu_addr |
>
Issue #508 has been updated by Arthur Heymans.
Yu-Ping Wu wrote:
> Similar to #499, after https://review.coreboot.org/c/coreboot/+/75012, Dojo
> fails to boot.
> Disabling CONFIG_RESOURCE_ALLOCATION_TOP_DOWN fixes the problem.
> However I'm not sure how to fix it from MediaTek's PCIe functions
Issue #508 has been updated by Yu-Ping Wu.
```
dojo-rev1 ~ # lspci
:00:00.0 PCI bridge: MEDIATEK Corp. Device 8195 (rev 01)
:01:00.0 Non-Volatile memory controller: Samsung Electronics Co Ltd NVMe
SSD Controller 980
0001:00:00.0 PCI bridge: MEDIATEK Corp. Device 8195 (rev 01)
Issue #508 has been updated by Yu-Ping Wu.
Related to Bug #499: coreboot will not boot edk2 on Lenovo T440p with
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled, cannot disable this setting during
build added
Bug #508: Dojo fails to boot from NVMe with
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