Carl-Daniel Hailfinger wrote:
They don't know (or need to know) what ht links are connecting the cpu
and what ones go to pci bus.
They need a way to specify settings for any given PCI device. Since most
modern machines have multiple PCI devices with the same vendor/device
ID, we have to be
On Fri, Oct 24, 2008 at 8:24 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
Would you mind posting lspci -tvnn for that 5-processor board as well?
It would help me a lot to understand this issue better.
Here they are, if you are still interested. There is a 5-node, and
8-node, and a 2-node
On 28.10.2008 00:49, Tom Sylla wrote:
On Fri, Oct 24, 2008 at 8:24 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
Would you mind posting lspci -tvnn for that 5-processor board as well?
It would help me a lot to understand this issue better.
Here they are, if you are still
On Fri, Oct 24, 2008 at 5:05 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
With Marc's mail, this is getting more complicated. It may be the best
thing to stick with the logical PCI structure of the system, however
that is not clear at all and seems to depend a great deal on the used
On Fri, Oct 24, 2008 at 8:24 PM, Carl-Daniel Hailfinger
[EMAIL PROTECTED] wrote:
AGESA has a default discovery method (I think
breadth first, lowest link number first) but it has options to
over-ride the discovery mechanism to change the order of nodes in a
system. All that matters is that the
On Sat, Oct 25, 2008 at 9:25 AM, Tom Sylla [EMAIL PROTECTED] wrote:
Hopefully it is clear now how things can move like that. The Opterons
won't move. It is possible with HT that other devices may exist on
higher bus numbers without a bridge (real or fake) from bus 0. It is
weird, and
+--18.0(Link n where n in [0,1,2])--+--19.0--(CPU)-(2nd HT link)
| |\|
\--(3rd HT link)
| | | +--19.1
| | | +--19.2
| | | +--19.3
| | |
| |
The HT topology is not really directly reflected in PCI config space.
They are obviously linked, but there is not really a way to map a HT
topology of Opteron nodes to a graphical view of config space, it just
doesn't exist. The Opterons just are where they are.
All of the processor PCI devices
Carl-Daniel Hailfinger wrote:
Hi,
I'm trying to understand how HT is modeled into PCI space so that I can
propose the right way to handle it in the dts.
Depending on whether I run lspci -t under coreboot or factory BIOS,
different topologies will be displayed. That means looking at lspci is
not
On Fri, Oct 24, 2008 at 6:10 AM, ron minnich [EMAIL PROTECTED] wrote:
+--18.0(Link n where n in [0,1,2])--+--19.0--(CPU)-(2nd HT link)
| |\|
\--(3rd HT link)
| | | +--19.1
| | | +--19.2
| | |
On 24.10.2008 15:10, ron minnich wrote:
+--18.0(Link n [0,1,2])--+--19.0--(CPU)-(2nd HT link)
| |\ |\--(3rd HT link)
| | |+--19.1
| | |+--19.2
| | |+--19.3
| | |
| |
On 24.10.2008 20:51, yhlu wrote:
On Fri, Oct 24, 2008 at 6:10 AM, ron minnich [EMAIL PROTECTED] wrote:
+--18.0(Link n where n in [0,1,2])--+--19.0--(CPU)-(2nd HT link)
| |\|
\--(3rd HT link)
| | | +--19.1
| | |
On 24.10.2008 19:50, Tom Sylla wrote:
The HT topology is not really directly reflected in PCI config space.
They are obviously linked, but there is not really a way to map a HT
topology of Opteron nodes to a graphical view of config space, it just
doesn't exist. The Opterons just are where
Carl-Daniel Hailfinger wrote:
On 24.10.2008 20:14, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
Hi,
I'm trying to understand how HT is modeled into PCI space so that I can
propose the right way to handle it in the dts.
Depending on whether I run lspci -t under coreboot or factory BIOS,
On 25.10.2008 02:33, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
On 24.10.2008 20:14, Marc Jones wrote:
Carl-Daniel Hailfinger wrote:
Hi,
I'm trying to understand how HT is modeled into PCI space so that I
can
propose the right way to handle it in the dts.
Depending on whether I run
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