[coreboot] [Minnowboard]: DDR initialization of Minnowboard dual ethernet

Hi, I have been following the typical approach of compiling Coreboot integrated with Inte FSP; SeaBIOS as payload, for my Minnowboard MAX dual ethernet board. On flashing, I couldn't reach at SeaBIOS shell. I noticed that SPD EEPROM(U33) is not mounted in order to configure the DDR. I could

Re: [coreboot] Minnowboard

/me starts searching for working FSP. With the current (BayTrailFspGold004_3) FSP from github and the microcode from the 3rdparty dir (3rdparty/soc/intel/baytrail/microcode_blob.h) I get it finally booting a Linux system. Thanks for all the tips. Daniel -- coreboot mailing list:

Re: [coreboot] Minnowboard

Hi Piotr, This will give you layout file similar to: :0fff fd 0040:007f bios 1000:003f me :0fff gbe I got this as well. Zoran just told me offline that fd and gbe seems to overlap. He also told me that the layout should be fd, gbe, me and finally bios.

Re: [coreboot] Minnowboard

Hi Michael and Zoran, On 03/22/2018 08:45 PM, Zoran Stojsavljevic wrote: IIRC, there are two types of BYT-i used for IOTG, in INTEL. The CPUIDs are 0x30673 (for Revision B) and 0x30679 (for Revision D). You can retrieve CPUID using simplistic CLI: dmesg | grep microcode after bringing Linux up:

Re: [coreboot] Minnowboard

t will hang > before giving any output. > > Best regards > Michael > > > > > > Ursprüngliche Nachricht > Von: Zoran Stojsavljevic <zoran.stojsavlje...@gmail.com> > Datum: 21.03.18 13:23 (GMT+01:00) > An: Daniel Wagner <w...

Re: [coreboot] Minnowboard

> It shows under position of ME. ME for Bay Trail is called TXE. I need to intervene here. TXE is a security engine, doing in HW MD5, sha256, sha1024 signatures, and more. It is used for locking and factory programming the device, also. This has nothing to do with ME. ME is completely different

Re: [coreboot] Minnowboard

.03.18 13:23 (GMT+01:00) An: Daniel Wagner <w...@monom.org> Cc: coreboot <coreboot@coreboot.org> Betreff: Re: [coreboot] Minnowboard Hello Daniel, You need to properly build Coreboot, integrating BYT-I (as I recall minnow board) FSP, and the info about BYT-I FSP you can find here:

Re: [coreboot] Minnowboard

-BEGIN PGP SIGNED MESSAGE- Hash: SHA512 On 03/22/2018 10:27 AM, Daniel Wagner wrote: > Hi Piotr, Hi Daniel, (...) > > Is the TXE code also part of the rom? I wonder why it is not > showing up in the ifdtool output. It shows under position of ME. ME for Bay Trail is called TXE.

Re: [coreboot] Minnowboard

Hi Piotr, On 03/21/2018 09:49 PM, Piotr Król wrote: > thank you for reading 3mdeb blog :) Thanks for taking time to write your findings up. Very useful. > MinnowBoard is already integrated. What board are you using ? Is this > MinnowBoard Turbot B ? It is the Turbot but I don't remember if it

Re: [coreboot] Minnowboard

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 On 03/21/2018 12:47 PM, Daniel Wagner wrote: > Hi, Hello Daniel, thank you for reading 3mdeb blog :) > > I would like to test my -rt kernels releases on the minnowboard. > Though cyclictest always reports 2 to 4 ms spikes. It looks like > that

Re: [coreboot] Minnowboard

Hello Daniel, You need to properly build Coreboot, integrating BYT-I (as I recall minnow board) FSP, and the info about BYT-I FSP you can find here: https://github.com/IntelFsp/FSP Zoran ___ On Wed, Mar 21, 2018 at 12:47 PM, Daniel Wagner wrote: > Hi, > > I would like to

[coreboot] Minnowboard

Hi, I would like to test my -rt kernels releases on the minnowboard. Though cyclictest always reports 2 to 4 ms spikes. It looks like that the original firmware is stealing those cycles. So my plan was to try out coreboot and see if my theory is correct or not. Now, I am struggling with getting

Re: [coreboot] Using High Speed UART1 as Serial port on CoreBoot (MinnowBoard)

Asunto: Re: [coreboot] Using High Speed UART1 as Serial port on CoreBoot (MinnowBoard) Hi Adrian, You are better off hooking up to the "Serial Console" port and using that. http://wiki.minnowboard.org/MinnowBoard_MAX If you really want to use one of the HS UARTs, then you have a b

Re: [coreboot] Using High Speed UART1 as Serial port on CoreBoot (MinnowBoard)

Hi Adrian, You are better off hooking up to the "Serial Console" port and using that. http://wiki.minnowboard.org/MinnowBoard_MAX If you really want to use one of the HS UARTs, then you have a bit of work to do. See src/drivers/uart/uart8250mem.c and note the use of

[coreboot] Using High Speed UART1 as Serial port on CoreBoot (MinnowBoard)

Hello everybody, I am newby with minnow board and CoreBoot. I am trying to use HIGH Speed UART1 as Serial port on CoreBoot (SIO_UART 1 pins) with no success. I have tried to configure CoreBoot with the following options: - Console > Index for UART port to use for console -> '0' o