On 09/11/2018 08:16 AM, Rudolf Marek wrote:
> Hi,
>
> Sifive did great job [1] [2] and everything is now opensource including mask
> rom loader.
Nice!
Truly a win for freedom hardware
Lets hope they next add an IOMMU.
>
> "Today we’re finally able to rectify this issue by releasing the
It looks like someone already pulled it off :[
https://github.com/sifive/freedom-u540-c000-bootloader/pull/6
0xDF372A17.asc
Description: application/pgp-keys
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Hi,
Sifive did great job [1] [2] and everything is now opensource including mask
rom loader.
"Today we’re finally able to rectify this issue by releasing the FU540-C000’s
ZSBL and FSBL as an open source project, which can be found on GitHub like all
of SiFive’s other open source projects."
That document is very useful. Nice to see SiFive came through :-)
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Hi all
See [1]
> terpstraWesley W. TerpstraVerified SiFive Account
> 2d
>
> I saw a few posts on the internet, which misrepresented what I was
> expressing. I never suggested reverse engineering our partner’s IP!
>
> SiFive is committed to supporting the open-source community. We are pleased
On Mon, Jun 25, 2018 at 11:39 PM, ron minnich wrote:
>
>
> On Mon, Jun 25, 2018 at 12:55 AM Shawn wrote:
>>
>> Hi Ron,
>>
>>
>> IIRC, Machine mode in RISC-V is just looking similar to SMM in x86.
>> But it can do more than what SMM does.
>
>
> that's in my view not good, since in many cases, M
On Tue, Jun 26, 2018 at 12:01 AM, Nico Huber wrote:
> On 25.06.2018 09:55, Shawn wrote:> Hi Ron,
>> On Sun, Jun 24, 2018 at 12:55 AM, ron minnich wrote:
>>> On Wed, Jun 20, 2018 at 11:03 PM taii...@gmx.com wrote:
Whats the deal with SMM? What a shame they thought to add it.
>>>
>>> It's a
Hi,
Dne 25.6.2018 v 09:01 Jonathan Neuschäfer napsal(a):
> If this is the Denali DDR controller, do you think it would be possible
> to simply read the initial configuration out of the registers of a
> booted system? (In any case, that's probably worth trying.)
Perhaps it could work with the
On Mon, Jun 25, 2018 at 8:46 AM Peter Stuge wrote:
> ron minnich wrote:
> > I realize there was a lot of hope in the early days that RISC-V
> > implied "openness" but as we can see that is not so.
>
> I hope that noone had that impression.
>
Lots of people have had that impression, hence my
On 25.06.2018 09:55, Shawn wrote:> Hi Ron,
> On Sun, Jun 24, 2018 at 12:55 AM, ron minnich wrote:
>> On Wed, Jun 20, 2018 at 11:03 PM taii...@gmx.com wrote:
>>> Whats the deal with SMM? What a shame they thought to add it.
>>
>> It's a huge disappointment. I made some effort a few years ago to
On 06/25/2018 10:45 AM, Peter Stuge wrote:
> ron minnich wrote:
>> I realize there was a lot of hope in the early days that RISC-V
>> implied "openness" but as we can see that is not so.
>
> I hope that noone had that impression.
>
> The key point (which I have to repeat every now and then) is
ron minnich wrote:
> I realize there was a lot of hope in the early days that RISC-V
> implied "openness" but as we can see that is not so.
I hope that noone had that impression.
The key point (which I have to repeat every now and then) is that
RISC-V *supports* openness, in ways not possible
On Mon, Jun 25, 2018 at 12:55 AM Shawn wrote:
> Hi Ron,
>
>
> IIRC, Machine mode in RISC-V is just looking similar to SMM in x86.
> But it can do more than what SMM does.
>
that's in my view not good, since in many cases, M mode code is part of
firmware, not the kernel image. Kernels don't get
Hi Ron,
On Sun, Jun 24, 2018 at 12:55 AM, ron minnich wrote:
>
>
> On Wed, Jun 20, 2018 at 11:03 PM taii...@gmx.com wrote:
>>
>>
>>
>> Whats the deal with SMM? What a shame they thought to add it.
>>
>>
>
>
> It's a huge disappointment. I made some effort a few years ago to try to
> convince
On 06/25/2018 02:30 AM, Timothy Pearson wrote:
> On 06/24/2018 08:06 PM, Nico Huber wrote:
>> On 25.06.2018 01:55, Timothy Pearson wrote:
>>> On 06/24/2018 06:41 PM, Timothy Pearson wrote:
On 06/24/2018 06:35 PM, Nico Huber wrote:
> On 24.06.2018 23:52, Timothy Pearson wrote:
>> On
On Mon, Jun 25, 2018 at 2:46 AM, Jonathan Neuschäfer
wrote:
> On Fri, Jun 22, 2018 at 01:01:04PM +0200, Jonathan Neuschäfer wrote:
> [...]
>> Section 20.3 describes the initialization sequence for the DRAM
>> controller, but leaves out the values for the register for "memory
>> timing settings,
On 06/24/2018 08:06 PM, Nico Huber wrote:
> On 25.06.2018 01:55, Timothy Pearson wrote:
>> On 06/24/2018 06:41 PM, Timothy Pearson wrote:
>>> On 06/24/2018 06:35 PM, Nico Huber wrote:
On 24.06.2018 23:52, Timothy Pearson wrote:
> On 06/24/2018 03:43 PM, Nico Huber wrote:
>> On
On Sun, Jun 24, 2018 at 11:28:11PM +0200, Rudolf Marek wrote:
> Hi,
>
> Lets do some speculation that some off the shelf DDR memory controller is
> used.
Probably.
> Maybe it could be same as the RockChip aka Denali High-Speed DDR PHY IP from
> Cadence?
> It has also some "interrupt status"
On 25.06.2018 01:55, Timothy Pearson wrote:
> On 06/24/2018 06:41 PM, Timothy Pearson wrote:
>> On 06/24/2018 06:35 PM, Nico Huber wrote:
>>> On 24.06.2018 23:52, Timothy Pearson wrote:
On 06/24/2018 03:43 PM, Nico Huber wrote:
> On 24.06.2018 21:37, taii...@gmx.com wrote:
>> On
On 06/24/2018 06:41 PM, Timothy Pearson wrote:
> On 06/24/2018 06:35 PM, Nico Huber wrote:
>> On 24.06.2018 23:52, Timothy Pearson wrote:
>>> On 06/24/2018 03:43 PM, Nico Huber wrote:
On 24.06.2018 21:37, taii...@gmx.com wrote:
> On 06/24/2018 02:59 PM, ron minnich wrote:
>> On Sun,
On 06/24/2018 06:35 PM, Nico Huber wrote:
> On 24.06.2018 23:52, Timothy Pearson wrote:
>> On 06/24/2018 03:43 PM, Nico Huber wrote:
>>> On 24.06.2018 21:37, taii...@gmx.com wrote:
On 06/24/2018 02:59 PM, ron minnich wrote:
> On Sun, Jun 24, 2018 at 11:47 AM Jonathan Neuschäfer
>
On 24.06.2018 23:52, Timothy Pearson wrote:
> On 06/24/2018 03:43 PM, Nico Huber wrote:
>> On 24.06.2018 21:37, taii...@gmx.com wrote:
>>> On 06/24/2018 02:59 PM, ron minnich wrote:
On Sun, Jun 24, 2018 at 11:47 AM Jonathan Neuschäfer
wrote:
>
>
> "While we’d love
On 06/24/2018 03:43 PM, Nico Huber wrote:
> On 24.06.2018 21:37, taii...@gmx.com wrote:
>> On 06/24/2018 02:59 PM, ron minnich wrote:
>>> On Sun, Jun 24, 2018 at 11:47 AM Jonathan Neuschäfer
>>> wrote:
>>>
"While we’d love to provide you with this information, we believe we
Hi,
Lets do some speculation that some off the shelf DDR memory controller is used.
Maybe it could be same as the RockChip aka Denali High-Speed DDR PHY IP from
Cadence?
It has also some "interrupt status" bits and such and "bstlen" which sounds
same as the few
regs named as the
I'm still interested in risc-v, just not hifive.
In saying I've lost interest, I'm definitely not saying anyone is a bad
person. The sifive people are wonderful, personally and professionally, and
I wish them the best success.
But sifive had to make some decisions to get to what they thought
On 24.06.2018 21:37, taii...@gmx.com wrote:
> On 06/24/2018 02:59 PM, ron minnich wrote:
>> On Sun, Jun 24, 2018 at 11:47 AM Jonathan Neuschäfer
>> wrote:
>>
>>>
>>>
>>> "While we’d love to provide you with this information, we believe we
>>> cannot. However, we can’t prevent anyone from
Hi Ron,
Dne 24.6.2018 v 20:59 ron minnich napsal(a):
> and ... there ends my interest in the hifive. A shame.
Well perhaps because the DDR controller is third party IP, see [1] FAQ or here:
> The Freedom U540 SoC is based on the Freedom Unleashed Platform, which has
> been open sourced. The
On 06/24/2018 02:59 PM, ron minnich wrote:
> On Sun, Jun 24, 2018 at 11:47 AM Jonathan Neuschäfer
> wrote:
>
>>
>>
>> "While we’d love to provide you with this information, we believe we
>> cannot. However, we can’t prevent anyone from disassembling the fsbl and
>> copying the values sent to the
On Sun, Jun 24, 2018 at 11:47 AM Jonathan Neuschäfer
wrote:
>
>
> "While we’d love to provide you with this information, we believe we
> cannot. However, we can’t prevent anyone from disassembling the fsbl and
> copying the values sent to the blackbox DDR register map."
>
>
and ... there ends
On Fri, Jun 22, 2018 at 01:01:04PM +0200, Jonathan Neuschäfer wrote:
[...]
> Section 20.3 describes the initialization sequence for the DRAM
> controller, but leaves out the values for the register for "memory
> timing settings, PAD mode configuration, initialization, and training."
> It says:
On Wed, Jun 20, 2018 at 11:03 PM taii...@gmx.com wrote:
>
>
> Whats the deal with SMM? What a shame they thought to add it.
>
>
>
It's a huge disappointment. I made some effort a few years ago to try to
convince folks this was a bad idea and failed.
I'm no longer as optimistic as I was about
All this said, note that the HiFive is no more open, today, than your
average ARM SOC; and it is much less open than, e.g., Power. I realize
there was a lot of hope in the early days that RISC-V implied "openness"
but as we can see that is not so. There's blobs in HiFive.
Open instruction sets do
On Fri, Jun 22, 2018 at 7:01 PM, Jonathan Neuschäfer
wrote:
> On Fri, Jun 22, 2018 at 03:04:06PM +0800, Shawn wrote:
>> Hi Jonathan,
>>
>> On Thu, Jun 21, 2018 at 7:48 PM, Jonathan Neuschäfer
> [...]
>> > With the unfinished coreboot port, I want it to look like this (although
>> > *a lot* of
On Fri, Jun 22, 2018 at 03:04:06PM +0800, Shawn wrote:
> Hi Jonathan,
>
> On Thu, Jun 21, 2018 at 7:48 PM, Jonathan Neuschäfer
[...]
> > With the unfinished coreboot port, I want it to look like this (although
> > *a lot* of work has to be done on coreboot first, and I'm currently not
> >
Hi Jonathan,
On Thu, Jun 21, 2018 at 7:48 PM, Jonathan Neuschäfer
wrote:
> Hello Taiidan and Timothy,
>
> On Thu, Jun 21, 2018 at 01:14:05AM -0500, Timothy Pearson wrote:
>> -BEGIN PGP SIGNED MESSAGE-
>> Hash: SHA256
>>
>> On 06/20/2018 09:13 PM, taii...@gmx.com wrote:
>> >
Hello Taiidan and Timothy,
On Thu, Jun 21, 2018 at 01:14:05AM -0500, Timothy Pearson wrote:
> -BEGIN PGP SIGNED MESSAGE-
> Hash: SHA256
>
> On 06/20/2018 09:13 PM, taii...@gmx.com wrote:
> >
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
On 06/21/2018 01:14 AM, Timothy Pearson wrote:
> On 06/20/2018 09:13 PM, taii...@gmx.com wrote:
>>
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
On 06/20/2018 09:13 PM, taii...@gmx.com wrote:
> https://www.phoronix.com/forums/forum/hardware/motherboards-chipsets/1021175-risc-v-sifive-freedom-unleahsed-540-soc-hifive-unleashed-board-added-to-coreboot
>
> The board costs almost as much as a
https://www.phoronix.com/forums/forum/hardware/motherboards-chipsets/1021175-risc-v-sifive-freedom-unleahsed-540-soc-hifive-unleashed-board-added-to-coreboot
The board costs almost as much as a significantly faster and with much
more features (IOMMU!) TALOS 2 Lite so I think it is not really
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