On Wed, Feb 27, 2019 at 8:27 AM wrote:
> I noticed in your patch you are calling this host CPU based clearing after
> the return from FSP memory initialization. If you are calling this in a
> system with ECC memory, this step is redundant. Part of the initialization
> of ECC enabled memory
On Wed, 2019-02-27 at 09:19 -0700, stevemoo...@sysproconsulting.com
wrote:
> Hi Patrick,
>
> I noticed in your patch you are calling this host CPU based clearing
> after the return from FSP memory initialization. If you are calling
> this in a system with ECC memory, this step is redundant.
Hi Patrick,
I noticed in your patch you are calling this host CPU based clearing after the
return from FSP memory initialization. If you are calling this in a system
with ECC memory, this step is redundant. Part of the initialization of ECC
enabled memory is to write a pattern to all of
On Tue, 2019-02-26 at 11:16 -0800, ron minnich wrote:
> On Tue, Feb 26, 2019 at 6:41 AM Patrick Rudolph
> wrote:
> >
> > Hi coreboot folks,
> > in order to support TEE like Intel TXT it is necessary to be able
> > to
> > clear all DRAM at boot on request.
> >
> > As all of the x86 coreboot code
I looked for my CL from years back in which I showed a way to 64-bit
amd64 ramstage, but I don't see it any more.
But it was easy.
On Tue, Feb 26, 2019 at 2:11 PM Rudolf Marek wrote:
>
> Hi,
>
> Dne 26. 02. 19 v 22:58 Nico Huber napsal(a):
> > On 26.02.19 20:16, ron minnich wrote:
> >> On Tue,
Hi,
Dne 26. 02. 19 v 22:58 Nico Huber napsal(a):
> On 26.02.19 20:16, ron minnich wrote:
>> On Tue, Feb 26, 2019 at 6:41 AM Patrick Rudolph
>> wrote:
>>>
>>> Hi coreboot folks,
>>> in order to support TEE like Intel TXT it is necessary to be able to
>>> clear all DRAM at boot on request.
>>>
>>>
On 26.02.19 20:16, ron minnich wrote:
> On Tue, Feb 26, 2019 at 6:41 AM Patrick Rudolph
> wrote:
>>
>> Hi coreboot folks,
>> in order to support TEE like Intel TXT it is necessary to be able to
>> clear all DRAM at boot on request.
>>
>> As all of the x86 coreboot code is x86_32, it is necessary
On Tue, Feb 26, 2019 at 6:41 AM Patrick Rudolph
wrote:
>
> Hi coreboot folks,
> in order to support TEE like Intel TXT it is necessary to be able to
> clear all DRAM at boot on request.
>
> As all of the x86 coreboot code is x86_32, it is necessary to make use
> of PAE to clear memory.
I would
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