Re: [coreboot] VGA and Graphics

his should allow getting rid of the option ROM if real mode support is >not required. Would great to have indeed, who knows if other OS drivers will mandate VBT one day. Kind regards. -- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Overheating on f2a85-m

on vendor UEFI, so this issue is > specific to Coreboot. Any idea what I can do? > If you notice a difference in CPU fan speed, that would be my guess since it looks fan control (super I/O) is rather minimally configured in coreboot. Kind regards. -- Arthur Heymans -- coreboot maili

Re: [coreboot] Lenovo Thinkpad X201: cannot boot encrypted Debian w/Coreboot & GRUB2

ode written in ada/spark, which might set up display correctly... > Is there anyone on the list who has Coreboot working on an X201 who > would be willing to share their .config file, so that I might see how > they succeeded where I am failing? > > Thanks! Kind regards -- Arthur Heyma

Re: [coreboot] Rowhammer DRAM Refresh

printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us"); } -- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] kfsn4-dre: Tested RAM configurations?

disable a dimm if they are unmatched. -- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Where to get ME image/flash descriptors for the x220?

the EC firmware if > that could potentially cause problems, I of course do not know if it > has DMA. > Only existing tool to flash EC is using vendor tool. EC are only accessed trough port mapped IO (or on newer ones also via memory mapped IO). EC itself does not have DMA afaik. -- A

Re: [coreboot] How to improve the boot time of the Asus KGPE-D16?

restore those on next boots (and resume from suspend) if no change in dimm configuration was detected. Maybe something like this could also be applied here (or maybe it's already the case since it includes code to access spi flash)? > > Thanks, > > Paul Kind regards -- Arthur Heyma

Re: [coreboot] No external PCIe GPU possible/working on Gigabyte g41m-es2l

w.coreboot.org/#/c/18511/ (not sure if needed) and https://review.coreboot.org/#/c/18513/ (works but might be improved) fix this issue. -- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] No external PCIe GPU possible/working on Gigabyte g41m-es2l

Arthur Heymans <art...@aheymans.xyz> writes: > <i1w5d7gf38...@tutanota.com> writes: > >> Hardware: Gigabyte g41m-es2l, latest coreboot git, latest seabios git, two >> nvidia gpu cards tested >> >> I tried to use some external GPU on a g41m-es2l to

Re: [coreboot] No external PCIe GPU possible/working on Gigabyte g41m-es2l

led/disabled. Linux is sometimes unhappy if no form of initialisation (option rom or native) has been performed. > > With OEM-bios the intel card gets disabled and a PCIe GPU works fine. OEM bios does the right thing :) -- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Freeze after few bootups

e a hardware issue? > I had this problem also on an other g41m-es2l mainboard with latest libreboot > image installed. So it does not seem to be hardware related and not fixed in > latest > coreboot. > > Anything i could do to help fixing this bug? I have never seen

Re: [coreboot] Freeze after few bootups

e a hardware issue? > I had this problem also on an other g41m-es2l mainboard with latest libreboot > image installed. So it does not seem to be hardware related and not fixed in > latest > coreboot. > > Anything i could do to help fixing this bug? I have never seen anything

Re: [coreboot] T520 2630QM 16GB DIMM

Thomas Richter <coreb...@tricnet.de> writes: > Hi, > > Zitat von Arthur Heymans <art...@aheymans.xyz>: > >>> TL;DR - Has anybody either successfully used 16GB DDR3 modules on >>> SandyBridge, can rule it out, or has ideas about how to dig deeper? >>

Re: [coreboot] T520 2630QM 16GB DIMM

hen it starts testing. > According to Sandy bridge datasheets only up to 4GB DDR3 technology is supported, which makes it possibly to use dimms with 2 ranks, with each rank having a capacity of 4GB, hence max 8GB per DIMM. This is a hardware limitation. <#secure method=pgpmime mode=sign>

[coreboot] Warning: Changed changed cmos.layout on many systems

t: Make multibyte options byte aligned" https://review.coreboot.org/#/c/18321/ Kind regards --- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Back to original BIOS

) bios which does not write protect its bootblock. With this it is possible to flash the vendor bios without having to rely on an external programmer to re-flash coreboot. Backup are essential! -- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mail

[coreboot] Warning: changed location of EC nvram settings on thinkpad X60 and T60

e, nvramtool -w bluetooth=Enable, etc" Kind regards ------ Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Removing ME on G45 desktop chipset - same as GM45 mobile?

d ICH10R southbridge. ICH10 supports descriptorless mode just like ICH9, so like ICH9 you can probably modify the firmware descriptor to boot without updating ME firmware, or simply remove the firmware descriptor. No idea if the 'procedure?' to do this would be the same. Kind regards -- Arthur H

[coreboot] Petitboot based bootloader

://github.com/open-power/op-build Kind Regards -- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] ISOLINUX gfx problems under qemu/coreboot/SeaBIOS

ck to a > text-based menu. A quick test shows me that selecting CONFIG_SEABIOS_VGA_COREBOOT is the culprit. This change https://review.coreboot.org/#/c/16965/ selects this by default when native graphic init is used but apparently needs an exception for QEMU. Kind regards -- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Attempt to porting coreboot to Gigabyte ga-945gcm-s2l

nly) and 533fsb (Intel d945gclf atom board). I guess I'll have to run vendor through serialICE and see how MCHBARS are configured with inteltool with 800fsb and 1067fsb cpus. Kind regards -- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Attempt to porting coreboot to Gigabyte ga-945gcm-s2l

e (like thinkpad x60). Having read all the i945 raminit code (this is not MRC but native coreboot code AFAIK) it does seem to be written with 667MHz fsb (945gm laptops like thinkpad x60)and 533MHz fsb (945gc inteld945gclf) in mind. So I will soon try to confirm this theory with 533MHz fsb cpu. > >

[coreboot] Attempt to porting coreboot to Gigabyte ga-945gcm-s2l

http://x86.renejeschke.de/html/file_module_x86_id_325.html. What does this mean? Did the raminit not work? -- Kind regards Arthur Heymans coreboot.log13 Description: coreboot.log -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Getting an WXGA+ LED MVA panel to work on T400: "G141C1-L01"

isplay-solution.com/pdf/tft-displays/Chi%20Mei%20Innolux/G141C1-L01_V2.0_20100802.pdf > From what I can understand from datasheets this is a dual channel LVDS (as expected)... > > > > -- > Merlin Büge <t...@bluenox07.de> Kind regards -- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] ps2 keyboard init in seabios

Hi In a few boards (at least x60, x200, google peppy and likely more) ps2 keyboard does not work consistently in seabios unless a timeout value is set (3sec default for x60), which adds a file etc/ps2-keyboard-spinup containing the max timeout value. A way to fix this to add this delay in the

[coreboot] RFC: implementing a way to force external EDID use.

be implemented: NB code, read_edid in drivers, decode_edid in lib, somewhere else? How do you think this feature should be turned on: nvram option or build option? Thank you for your comments -- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Documentation on msr bits on intel cpuid 6ex and later

the "Intel® 64 and IA-32 Architectures Software Developer’s Manual" those bits are marked as reserved... I would like to know more about this, so if someone can help me on this... -- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] gfx_uma_size on GM45

t;ggc |= 0x0800; } Kind regards -- Arthur Heymans -- coreboot mailing list: coreboot@coreboot.org https://www.coreboot.org/mailman/listinfo/coreboot

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