Re: [coreboot] SeaBIOS with native graphics initialization?

[Piotr Kubaj]

Thanks,

unfortunately, it didn't work :( I guess something is not wrong,
although it's not completely broken - while when I should see SeaBIOS I
can see only a turned off screen, after a few seconds my OS loads, so I
still can use software flash. Can you look at my configs and write what
is wrong?

Thanks,
Piotr Kubaj
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#

#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
# CONFIG_MULTIPLE_CBFS_INSTANCES is not set
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_SCONFIG_GENPARSER is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
# CONFIG_UNCOMPRESSED_RAMSTAGE is not set
CONFIG_COMPRESS_RAMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_EARLY_CBMEM_INIT=y
# CONFIG_COLLECT_TIMESTAMPS is not set
# CONFIG_USE_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_RELOCATABLE_MODULES is not set
# CONFIG_RELOCATABLE_RAMSTAGE is not set
CONFIG_FLASHMAP_OFFSET=0
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_BOOTBLOCK_CUSTOM=y
CONFIG_BOOTBLOCK_SOURCE="bootblock_simple.c"
# CONFIG_C_ENVIRONMENT_BOOTBLOCK is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_GENERIC_GPIO_LIB is not set
# CONFIG_BOARD_ID_AUTO is not set
# CONFIG_BOARD_ID_MANUAL is not set
# CONFIG_RAM_CODE_SUPPORT is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_ACPI_SATA_GENERATOR is not set

#
# Mainboard
#
# CONFIG_VENDOR_A_TREND is not set
# CONFIG_VENDOR_AAEON is not set
# CONFIG_VENDOR_ABIT is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_ADVANSUS is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARTECGROUP is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_AVALUE is not set
# CONFIG_VENDOR_AZZA is not set
# CONFIG_VENDOR_BACHMANN is not set
# CONFIG_VENDOR_BAP is not set
# CONFIG_VENDOR_BCOM is not set
# CONFIG_VENDOR_BIFFEROS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BROADCOM is not set
# CONFIG_VENDOR_COMPAQ is not set
# CONFIG_VENDOR_CUBIETECH is not set
# CONFIG_VENDOR_DIGITALLOGIC is not set
# CONFIG_VENDOR_DMP is not set
# CONFIG_VENDOR_ECS is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ESD is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GIZMOSPHERE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IEI is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_IWAVE is not set
# CONFIG_VENDOR_IWILL is not set
# CONFIG_VENDOR_JETWAY is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LANNER is not set
CONFIG_VENDOR_LENOVO=y
# CONFIG_VENDOR_LINUTOP is not set
# CONFIG_VENDOR_LIPPERT is not set
# CONFIG_VENDOR_MITAC is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NEC is not set
# CONFIG_VENDOR_NOKIA is not set
# CONFIG_VENDOR_NVIDIA is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RCA is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SOYO is not set
# CONFIG_VENDOR_SUNW is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_TECHNEXION is not set
# CONFIG_VENDOR_THOMSON is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TRAVERSE is not set
# CONFIG_VENDOR_TYAN is not set
# CONFIG_VENDOR_VIA is not set
# CONFIG_VENDOR_WINENT is not set
# CONFIG_VENDOR_WYSE is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_DIR="lenovo/x200"
CONFIG_MAINBOARD_PART_NUMBER="ThinkPad X200"
CONFIG_MAINBOARD_VENDOR="LENOVO"
CONFIG_MAX_CPUS=2
CONFIG_VGA_BIOS_ID="8086,2a42"
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_VGA_BIOS=y
CONFIG_DCACHE_RAM_BASE=0xffaf8000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_VGA_BIOS_FILE="/root/coreboot-4.4/payloads/external/SeaBIOS/seabios/out/vgabios.bin"
CONFIG_MMCONF_BASE_ADDRESS=0xf000
CONFIG_POST_IO=y
CONFIG_MAX_REBOOT_CNT=3
# CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT is not set
CONFIG_ID_SECTION_OFFSET=0x80
CONFIG_RAMTOP=0x20
CONFIG_CACHE_ROM_SIZE_OVERRIDE=0
CONFIG_CBFS_SIZE=0x7FD000
CONFIG_POST_DEVICE=y
CONFIG_USBDEBUG_HCD_INDEX=2
# CONFIG_CONSOLE_POST is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PAYLOAD_CONFIGFILE="/root/coreboot-4.4/.seabiosconfig"
# CONFIG_BOARD_LENOVO_G505S is not set
# CONFIG_BOARD_LENOVO_R400 is not set
# CONFIG_BOARD_LENOVO_T400 is not set
# CONFIG_BOARD_LENOVO_T420 is not set
# CONFIG_BOARD_LENOVO_T420S is not set
# CONFIG_BOARD_LENOVO_T430S is not set
# CONFIG_BOARD_LENOVO_T500 is not set
# CONFIG_BOARD_LENOVO_T520 is not set
# CONFIG_BO

Re: [coreboot] SeaBIOS with native graphics initialization?

[Piotr Kubaj]

I should also mention that although I have
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT now, when I had it on previously,
the result was about the same, except that before booting OS the screen
was on (but it didn't display anything).

On 06/02/2016 20:09, Piotr Kubaj wrote:
> Thanks,
> 
> unfortunately, it didn't work :( I guess something is not wrong,
> although it's not completely broken - while when I should see SeaBIOS I
> can see only a turned off screen, after a few seconds my OS loads, so I
> still can use software flash. Can you look at my configs and write what
> is wrong?
> 
> Thanks,
> Piotr Kubaj
> 



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[coreboot] SeaBIOS with native graphics initialization?

[Piotr Kubaj]

Hi all,

I'm currently running Libreboot 20150518 on ThinkPad X200, but I'd like 
to switch to Coreboot (the newest stable version, 4.4). The reason is 
that Libreboot seems to provide only one configuration and its build 
system seems difficult to understand in comparison to Coreboot.


I'd like to use SeaBIOS (as opposed to Libreboot's GRUB) as payload - I 
also would like to have coreinfo, memtest and nvramcui so that it all 
provides kind of BIOS-like menu.


Is that possible using native graphics initialization without vgabios? 
There are some recent references that it's possible.


I'm asking because, although I have flashing equipment (I've flashed my 
X200 myself), the flashing took a lot of time, because of too long 
wires, interferences from PSU etc. I don't want to be forced to flash it 
again, so I want to be absolutely sure before I switch.
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Re: [coreboot] SeaBIOS with native graphics initialization?

[Piotr Kubaj]

Thanks,

does CONFIG_VGA_BIOS also need to be set in Coreboot config file?

On 05/31/16 09:08, Gerd Hoffmann wrote:
>   Hi,
> 
>> Is that possible using native graphics initialization without vgabios?
>> There are some recent references that it's possible.
> 
> CONFIG_VGA_COREBOOT=y in seabios.
> 
> That'll give you a vgabios which does vga text mode emulation on top of
> a coreboot framebuffer.
> 
> cheers,
>   Gerd
> 

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[coreboot] Coreboot / Libreboot on KGPE-D16 restarting / turning off randomly

[Piotr Kubaj]

I'm trying to flash the latest Libreboot images on KGPE-D16. I'm using 2 
6262HE CPU's and 56GB RAM (3*16GB + 4*2GB).


The 2GB RAM's are from Micron and they cause the system to go in the 
reboot loop even before graphics are initialized (there's nothing on the 
screen, I only get serial output).


But I don't care that much about those Microns, I only have 8GB from 
them. What matters to me more is the rest (3*16GB RAM). Those are 2 
KVR16R11D4/16 and 1 KVR16R11D4/16HB. KVR16R11D4/16 are specifically 
recommended by https://www.coreboot.org/Board:asus/kgpe-d16. Even then, 
with those 2 KVR16R11D4/16 put in the RAM slots that work with vendor 
BIOS just fine (the latest 3309 version), the system using Coreboot / 
Libreboot reboots randomly, usually during booting the OS (I use FreeBSD 
11.0-RELEASE). There's nothing on the serial console and seems to just 
reboot randomly.


The system uses pure Libreboot config with added nvramcui and memtest 
payloads and SeaBIOS as a primary payload. Since I use 16MB chip, I 
compiled my own image for it.


Any ideas about this? I spent yesterday about 8hrs trying to make it 
work and am currently out of ideas.



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[coreboot] Updated AMD microcode for Spectre V2

[Piotr Kubaj]

It looks like they go the same way that Intel did (vendors first):
https://www.amd.com/en/corporate/security-updates

It's still nice that at last we get new microcode, but it's a shame AMD didn't 
notify coreboot project :/

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Piotr Kubaj
Administrator Systemowy
e-mail: pku...@iq.pl


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[coreboot] Overheating on f2a85-m

[Piotr Kubaj via coreboot]

I've installed Coreboot on ASUS F2A85-M. Everything works fine, but the CPU 
overheats when doing something intensive (like video playing) and the OS 
crashes. Browsing the internet and watching movies doesn't make it sweat. I use 
FreeBSD 11.0-RELEASE and Gentoo Linux.

My CPU is X4 750k. I lowered the RAM voltage to 1.35V but it doesn't really 
help. Enabling power saving features also doesn't make a difference. Everything 
works fine on vendor UEFI, so this issue is specific to Coreboot. Any idea what 
I can do?

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Re: [coreboot] Overheating on f2a85-m

[Piotr Kubaj via coreboot]

Thanks!

I'm only starting to get some knowledge about Coreboot and I didn't realize 
that I need to configure fans in the OS :) Now everything seems fine, except 
that FreeBSD doesn't seem to have a way to configure fan speed...

On 17-03-26 21:35:33, Rudolf Marek wrote:
> Hi again,
> 
> Sorry, I pasted wrong dump. Before I installed right /etc/sensors3.conf
> 
> radeon-pci-0008
> Adapter: PCI adapter
> temp1:+35.0°C  (crit = +120.0°C, hyst = +90.0°C)
> 
> it8603-isa-0290
> Adapter: ISA adapter
> Vcore:+1.27 V  (min =  +1.12 V, max =  +2.96 V)  ALARM
> in1:  +1.66 V  (min =  +2.69 V, max =  +0.08 V)  ALARM
> +12V:+12.38 V  (min = +14.98 V, max =  +0.00 V)  ALARM
> +5V:  +5.07 V  (min =  +3.96 V, max =  +0.12 V)  ALARM
> in4:  +1.20 V  (min =  +1.92 V, max =  +0.12 V)  ALARM
> 3VSB: +3.31 V  (min =  +0.79 V, max =  +2.88 V)  ALARM
> Vbat: +3.14 V
> +3.3V:+3.36 V
> CPU Fan: 2824 RPM  (min =  200 RPM)
> CHA Fan:0 RPM  (min =  600 RPM)  ALARM
> CPU Temp: +64.0°C  (low  = +50.0°C, high = -126.0°C)  ALARM  sensor = 
> thermistor
> M/B Temp: +38.0°C  (low  = +100.0°C, high = +122.0°C)  sensor = thermistor
> temp3:   -128.0°C  (low  = -24.0°C, high =  +0.0°C)  sensor = thermistor
> intrusion0:  OK
> 
> k10temp-pci-00c3
> Adapter: PCI adapter
> temp1:+48.9°C  (high = +70.0°C)
>(crit = +70.0°C, hyst = +69.0°C)
> 
> Thanks
> Rudolf
> 
> -- 
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> 

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Re: [coreboot] Coreboot + Seabios Asus F2A85-M LE card

[Piotr Kubaj via coreboot]

Do you use the internal GPU or external? If you use internal, you probably need 
firmware from AMD (SeaVGABIOS won't work). If you have external GPU, you don't 
need VGA option ROM at all.

Anyway, you don't need SeaVGABIOS.

You also put CONFIG_QEMU_HARDWARE=y, which is unnecessary.


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Re: [coreboot] Coreboot + Seabios Asus F2A85-M LE card

[Piotr Kubaj via coreboot]

https://www.coreboot.org/VGA_support

On 17-06-08 11:01:55, Gabriel Bosque wrote:
> Internal. Where do I find firmware for it?
> 
> Tanks in advance
> 
> 2017-06-08 10:45 GMT-03:00 Piotr Kubaj <pku...@anongoth.pl>:
> 
> > Do you use the internal GPU or external? If you use internal, you probably
> > need firmware from AMD (SeaVGABIOS won't work). If you have external GPU,
> > you don't need VGA option ROM at all.
> >
> > Anyway, you don't need SeaVGABIOS.
> >
> > You also put CONFIG_QEMU_HARDWARE=y, which is unnecessary.
> >
> 
> -- 
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> dangerous content by MailScanner, and is
> believed to be clean.
> 

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Re: [coreboot] Coreboot + Seabios Asus F2A85-M LE card

[Piotr Kubaj via coreboot]

My F2A85-M has UEFI by default, you probably also have UEFI. That means 
bios_extract won't work. You can keep trying to extract with UEFITool, or try 
this path https://www.coreboot.org/VGA_support#Retrieval_via_Linux_kernel

On 17-06-09 10:41:31, Gabriel Bosque wrote:
> Okay. I tried a path, which I thought was the most practical, but I have a
> problem:
> _I downloaded the .cap file from the card in Asus site
> _Using the UEFITool draw for asus.rom
> _By using ./bios_extract asus.rom, it gives msg:
>   Error: Unable to detect BIOS Image type.
> Any tips?
> 
> 2017-06-08 12:19 GMT-03:00 Piotr Kubaj <pku...@anongoth.pl>:
> 
> > https://www.coreboot.org/VGA_support
> >
> > On 17-06-08 11:01:55, Gabriel Bosque wrote:
> > > Internal. Where do I find firmware for it?
> > >
> > > Tanks in advance
> > >
> > > 2017-06-08 10:45 GMT-03:00 Piotr Kubaj <pku...@anongoth.pl>:
> > >
> > > > Do you use the internal GPU or external? If you use internal, you
> > probably
> > > > need firmware from AMD (SeaVGABIOS won't work). If you have external
> > GPU,
> > > > you don't need VGA option ROM at all.
> > > >
> > > > Anyway, you don't need SeaVGABIOS.
> > > >
> > > > You also put CONFIG_QEMU_HARDWARE=y, which is unnecessary.
> > > >
> > >
> > > --
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> > > dangerous content by MailScanner, and is
> > > believed to be clean.
> > >
> >
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> >
> 
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> 

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Re: [coreboot] Ability to remotely debug the grub menu in case of boot failure

[Piotr Kubaj via coreboot]

You might want to check what PCengines guys did, their APU doesn't have video 
(only serial), and the keyboard works in SeaBIOS.

On 17-10-05 12:00:01, coreboot-requ...@coreboot.org wrote:

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Today's Topics:

  1. Re: Broadwell-DE NS FSP not support (Hilbert Tu (???_Pegatron))
  2. Re: Ability to remotely debug the grub menu in case of boot
 failure (Anshuman Aggarwal)


--

Message: 1
Date: Thu, 5 Oct 2017 01:40:04 +
From: Hilbert Tu(???_Pegatron)  
To: Zoran Stojsavljevic 
Cc: "coreboot@coreboot.org" 
Subject: Re: [coreboot] Broadwell-DE NS FSP not support
Message-ID:
<9efdf862436d5041ad8d822c06211f1501491...@ptw-ex-36.pega.corp.PEGATRON>

Content-Type: text/plain; charset="utf-8"

Hi Zoran/Piotr,

Yes, the current available FSP does not support BDX-DE NS. I got same 
information from local Intel FAE.  So I don?t know the next step to evaluate my 
CRB.

@Taiidan,
Thanks for your information, ?6 months for skilled person? ? Maybe I should try 
BIOS/UEFI first.

-Hilbert

From: Zoran Stojsavljevic [mailto:zoran.stojsavlje...@gmail.com]
Sent: Wednesday, October 04, 2017 7:57 PM
To: Hilbert Tu(???_Pegatron)
Cc: coreboot@coreboot.org
Subject: Re: [coreboot] Broadwell-DE NS FSP not support

Hello Hilbert,

There is none FSP for BDW-DE? Are you sure?? And how did you conclude that???

Here is the answer: https://github.com/IntelFsp/FSP

Intel? Xeon? Processor D Product Family (formerly Broadwell-DE, Compliant with 
FSP v1.0 Specification) Broadwell-DE: git clone -b Broadwell-DE 
https://github.com/IntelFsp/FSP.git


git clone -b Broadwell-DE  
https://github.com/IntelFsp/FSP.git


Zoran
___

On Tue, Oct 3, 2017 at 4:39 AM, Hilbert Tu(???_Pegatron) 
> wrote:
Hi,
I have an Intel Broadwell-DE NS CRB and I want to evaluate it with coreboot. 
But from Intel FSP git, there is no corresponding FSP for Broadwell-DE NS. Does 
that mean I can?t use coreboot as boot loader if Intel FSP not available for my 
platform? If not, does anyone know how to do that? Please help. Thanks.
-Hilbert
This e-mail and its attachment may contain information that is confidential or 
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Message: 2
Date: Thu, 5 Oct 2017 15:24:50 +0530
From: Anshuman Aggarwal 
To: ron minnich 
Cc: "taii...@gmx.com" , coreboot@coreboot.org
Subject: Re: [coreboot] Ability to remotely debug the grub menu in
case of boot failure
Message-ID:

[coreboot] Serial input / output with SeaBIOS 1.11.0

[Piotr Kubaj via coreboot]

Hi,

I've upgraded my coreboot to tag 4.7. As a payload I use SeaBIOS. I want to use 
the new feature of serial communication from SeaBIOS. The issue I have is that 
there's only serial output (meaning I can see the SeaBIOS menu on serial), but 
pressing any key on keyboard via serial doesn't do anything - I can only 
control SeaBIOS via keyboard plugged directly to the board, not via serial.

Does anyone have the same issue? I use AsRock E350M1 board. I didn't create a 
custum SeaBIOS config, I just use the default one.


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Re: [coreboot] Server systems shipped with coreboot

[Piotr Kubaj via coreboot]

There's no "pure coreboot" systems. You need some payload.

Also, while Talos is truly awesome, the OP asked about coreboot specifically 
and Talos doesn't run coreboot :)

At the moment, the best coreboot-supported server motherboard is ASUS KGPE-D16. 
You can also get libre BMC with OpenBMC port for it.

If you just want a libre motherboard, Talos is the best you can get.

On 18-01-17 12:00:01, coreboot-requ...@coreboot.org wrote:

Message: 2
Date: Tue, 16 Jan 2018 19:29:18 +0100
From: Carl-Daniel Hailfinger 
To: Coreboot 
Subject: [coreboot] Server systems shipped with coreboot
Message-ID: 
Content-Type: text/plain; charset=UTF-8

Hi,

does anyone have a list of server systems which are shipped with
coreboot? I'm interested in coreboot+UEFI systems, coreboot+Linux
systems, coreboot+SeaBIOS systems, pure coreboot systems.

At 34C3 I was told by someone that a major vendor has been shipping
servers with coreboot without announcing this, and I unfortunately
neither remember the server model nor who told me about this. If said
person could remind contact me, I'd be thankful.

Regards,
Carl-Daniel



--

Message: 3
Date: Wed, 17 Jan 2018 00:28:23 +0300
From: Mike Banon 
To: Carl-Daniel Hailfinger ,
coreboot@coreboot.org
Subject: Re: [coreboot] Server systems shipped with coreboot
Message-ID:

Content-Type: text/plain; charset="UTF-8"

Hi friend ! I just googled "coreboot servers" and found this:

https://store.vikings.net/the-server-1u , and
https://www.siliconmechanics.com/i7045/opteron-server.php
(Installation of coreboot is available with certain configurations;
contact Sales for details.)

And, of course, Talos II POWER9 servers which are already available
for pre-orders.
They are the future of libre server computing :
https://www.raptorcs.com/TALOSII/prerelease.php

So basically there are two options:
1) use one of a few coreboot-supported boards with AMD Opterons (which
are also a bit outdated)
you can even build such a server by yourself, just get the supported
hardware and flash coreboot to it
2) preorder Talos II and wait for shiny new server to come ;)

Mike


On Tue, Jan 16, 2018 at 9:29 PM, Carl-Daniel Hailfinger
 wrote:

Hi,

does anyone have a list of server systems which are shipped with
coreboot? I'm interested in coreboot+UEFI systems, coreboot+Linux
systems, coreboot+SeaBIOS systems, pure coreboot systems.

At 34C3 I was told by someone that a major vendor has been shipping
servers with coreboot without announcing this, and I unfortunately
neither remember the server model nor who told me about this. If said
person could remind contact me, I'd be thankful.

Regards,
Carl-Daniel

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Re: [coreboot] When does AMD release the fam15 spectre microcode updates?

[Piotr Kubaj via coreboot]

AFAIK it's not only fam15 that is vulnerable. If you're going to ask, could you 
ask about updates for other CPU's than Ryzen in general? I also have fam14 and 
fam16 boards.

On 18-02-19 12:00:01, coreboot-requ...@coreboot.org wrote:

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Today's Topics:

  1. Re: When does AMD release the fam15 spectre microcode
 updates? (Mike Banon)
  2. Re: When does AMD release the fam15 spectre microcode
 updates? (Rudolf Marek)


--

Message: 1
Date: Sun, 18 Feb 2018 14:48:05 +0300
From: Mike Banon 
To: "taii...@gmx.com" , coreboot@coreboot.org
Subject: Re: [coreboot] When does AMD release the fam15 spectre
microcode updates?
Message-ID:

Content-Type: text/plain; charset="UTF-8"

Maybe its' a good idea to write to AMD support regarding this question
- please share a reply if you would get an answer. I'm curious about
other fam15 CPUs as well, e.g. A10-5750M microcode update would be
nice, maybe a request could be more general, e.g. : what is the
estimated release date for the microcode updates for fam15 AMD CPUs
(so a request is  not about "opterons only")

On Sun, Feb 18, 2018 at 2:47 PM, Mike Banon  wrote:

Maybe its' a good idea to write to AMD support regarding this question
- please share a reply if you would get an answer. I'm curious about
other fam15 CPUs as well, e.g. A10-5750M microcode update would be
nice, maybe a request could be more general, e.g. : what is the
estimated release date for the microcode updates for fam15 AMD CPUs
(so a request is  not about "opterons only")

On Sun, Feb 18, 2018 at 4:30 AM, taii...@gmx.com  wrote:

They said they would be releasing opteron microcode updates in a few weeks
but it has been over a month and I am wondering when this is going to happen
or if it already has and I should re-compile coreboot?

https://www.amd.com/en/corporate/speculative-execution
"We expect to make updates available for our previous generation products
over the coming weeks."

Thanks!


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Message: 2
Date: Sun, 18 Feb 2018 13:03:07 +0100
From: Rudolf Marek 
To: Mike Banon , "taii...@gmx.com"
, coreboot@coreboot.org
Subject: Re: [coreboot] When does AMD release the fam15 spectre
microcode updates?
Message-ID: 
Content-Type: text/plain; charset=iso-8859-2

Hi,

What do you want to protect? If you want to protect the kernel, retpolines are 
OK on AMD.
And you don't need any microcode update. Your CPU needs to have SMEP, otherwise
you would need to clear RSB on CPL change (the paper on mentined page says that 
you need to do that
always, but at least on Ryzen, the attack using RSB is not working (we tried 
that out, maybe it works
only on some circumstances).

If you want to protect userspace, the RSB will be clear by IBPB (which you 
would need if you don't have userspace compiled
with retpolines). I don't know if intel clears RSB on IBPB... probably not

To sum it up on AMD:

kernel:
retpolines, RSB clear on CPL change on CPU without SMEP (see above)

userspace:
retpolines, RSB clear on context switch necessary or IBPB (needs microcode 
update).

Plus make sure you enable "LFENCE is dispatch serializing" - perhaps coreboot 
can do that :) it is simple
MSR write on fam 10h 12h+ the fam 11h and 0fh dont have this MSR but LFENCE is 
dispatch serilizing.

Besides that, you don't need any microcode update.

Plus of course there is a spectre variant 1, which is more difficult to 
mitigate, basically you need to check all the software
and look for any pattern like array_x[array_z[untrusted_index] * any 
transformation].

The first access would leak just address (ASLR defated), second will leak data.
The variant 1 works on user/user attack and as well as user/kernel.

As far I know there are no automated tools to check for this.


Thanks
Rudolf









Dne 18.2.2018 v 12:48 Mike Banon napsal(a):

Maybe its' a good idea to write to AMD support regarding this question
- please share a reply if you would get an answer. I'm curious about
other fam15 CPUs as well, e.g. A10-5750M microcode update would be
nice, maybe a request could be more general, 

Re: [coreboot] OpenBMC & KGPE-D16

[Piotr Kubaj via coreboot]

Strange, I didn't apply any patches. I run D16 with stock coreboot 4.7 and 
OpenBMC.

Could it be because I have different memory modules (4xKVR16R11D4/16)?

On 18-02-24 12:00:01, coreboot-requ...@coreboot.org wrote:

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Today's Topics:

  1. Re: OpenBMC & KGPE-D16 (Elisenda Cuadros)
  2. Re: OpenBMC & KGPE-D16 (Timothy Pearson)
  3. Re: OpenBMC & KGPE-D16 (Elisenda Cuadros)
  4. Re: OpenBMC & KGPE-D16 (Timothy Pearson)
  5. Re: OpenBMC & KGPE-D16 (Elisenda Cuadros)
  6. make gitconfig not working for me with git 1.9.1
 (mtur...@codeaurora.org)
  7. Re: OpenBMC & KGPE-D16 (Elisenda Cuadros)


--

Message: 1
Date: Fri, 23 Feb 2018 23:38:42 +0100
From: Elisenda Cuadros 
To: Timothy Pearson , Coreboot

Subject: Re: [coreboot] OpenBMC & KGPE-D16
Message-ID: <024a1ee2-7edc-be52-f87d-3bfbf95aa...@e4l.es>
Content-Type: text/plain; charset="utf-8"; Format="flowed"

Hello,

Thank you for your reply.

I reflashed (same build) the BMC module with a hotplug. Now it works 
like a charm, it got an ip, I can log through ssh, reboot, etc..


But now I have a new problem. If I try to boot from a halted system, 
with BMC module attached, the system fires up but Coreboot hangs:


Unable to detect valid memory on any nodes.? Halting!
mct_d: fatalexit

If I remove the BMC module the system boots fine.

I have 4 Micron MT18JSF25672PDZ-1G4F1DD modules, located in CPU1 orange 
slots.


I attach both console logs.

Regards,

- Eli



On 22/02/18 22:36, Timothy Pearson wrote:

Actually, for OpenBMC work, hotplugging is often the only way to go.
Just be very careful to align the pins correctly the first time; you
don't have a second chance if you misalign the pins and fry the module...

On 02/22/2018 03:22 PM, taii...@gmx.com wrote:

On 02/17/2018 09:46 AM, Elisenda Cuadros wrote:


Hi,

Now I trying to use your OpenBMC port.

I followed the instructions and everything was fine (compiling,
reading and flashing). I waited several minutes after flashing, but
the module didn 't blinked like in the vendor rom, nor did it receive
an ip.

I halted the system because I thought maybe it needs a cold start.

After this, the system doesn't boot with the module plugged in. The
fans begin to spin for approximately 1/4 second, but nothing else.

My two fans (1 cpu & 1 chassis) have 3 pins and are low speed (~1000rpm)

In the case I have to reflash the module, is it possible to hotplug it?

Hotplugging is dangerous and not supported, don't do it.

Thank you very much for your support.

You can use a test clip to externally flash it via a flashing device
(not sure which can do 16 pins though, I would inquire on the flashrom
mailinglist)

Are you using the latest coreboot? AFAIK coreboot was patched to support
OpenBMC, so you need a new version with the patches.

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--

Message: 2
Date: Fri, 23 Feb 2018 17:01:13 -0600
From: Timothy Pearson 
To: Elisenda Cuadros 
Cc: Coreboot 
Subject: Re: [coreboot] OpenBMC & KGPE-D16
Message-ID: <5a909d39.40...@raptorengineering.com>
Content-Type: text/plain; charset=UTF-8

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When replying, please edit your Subject line so it is more specific
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Today's Topics:

  1. Re: OpenBMC & KGPE-D16 (Elisenda Cuadros)
  2. Re: OpenBMC & KGPE-D16 (Timothy Pearson)
  3. Re: OpenBMC & KGPE-D16 (Elisenda Cuadros)
  4. Re: OpenBMC & KGPE-D16 (Timothy Pearson)
  5. Re: OpenBMC & KGPE-D16 (Elisenda Cuadros)
  6. make gitconfig not working for me 

Re: [coreboot] OpenBMC & KGPE-D16

[Piotr Kubaj via coreboot]

It's iKVM4.

On 18-02-25 04:23:45, Timothy Pearson wrote:

Actually that's quite odd -- it should not work that way.  There is a
hardware mux that is switched in when the module is installed; only the
BMC can access the DRAM SPD lines without a BMC GPIO being set.

Which module are you using, the iKVM4 or the iKVM5?

On 02/24/2018 11:10 AM, Piotr Kubaj via coreboot wrote:

Strange, I didn't apply any patches. I run D16 with stock coreboot 4.7
and OpenBMC.

Could it be because I have different memory modules (4xKVR16R11D4/16)?

On 18-02-24 12:00:01, coreboot-requ...@coreboot.org wrote:

Send coreboot mailing list submissions to
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You can reach the person managing the list at
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When replying, please edit your Subject line so it is more specific
than "Re: Contents of coreboot digest..."


Today's Topics:

  1. Re: OpenBMC & KGPE-D16 (Elisenda Cuadros)
  2. Re: OpenBMC & KGPE-D16 (Timothy Pearson)
  3. Re: OpenBMC & KGPE-D16 (Elisenda Cuadros)
  4. Re: OpenBMC & KGPE-D16 (Timothy Pearson)
  5. Re: OpenBMC & KGPE-D16 (Elisenda Cuadros)
  6. make gitconfig not working for me with git 1.9.1
 (mtur...@codeaurora.org)
  7. Re: OpenBMC & KGPE-D16 (Elisenda Cuadros)


--

Message: 1
Date: Fri, 23 Feb 2018 23:38:42 +0100
From: Elisenda Cuadros <li...@e4l.es>
To: Timothy Pearson <tpear...@raptorengineering.com>, Coreboot
<coreboot@coreboot.org>
Subject: Re: [coreboot] OpenBMC & KGPE-D16
Message-ID: <024a1ee2-7edc-be52-f87d-3bfbf95aa...@e4l.es>
Content-Type: text/plain; charset="utf-8"; Format="flowed"

Hello,

Thank you for your reply.

I reflashed (same build) the BMC module with a hotplug. Now it works
like a charm, it got an ip, I can log through ssh, reboot, etc..

But now I have a new problem. If I try to boot from a halted system,
with BMC module attached, the system fires up but Coreboot hangs:

Unable to detect valid memory on any nodes.? Halting!
mct_d: fatalexit

If I remove the BMC module the system boots fine.

I have 4 Micron MT18JSF25672PDZ-1G4F1DD modules, located in CPU1
orange slots.

I attach both console logs.

Regards,

- Eli



On 22/02/18 22:36, Timothy Pearson wrote:

Actually, for OpenBMC work, hotplugging is often the only way to go.
Just be very careful to align the pins correctly the first time; you
don't have a second chance if you misalign the pins and fry the
module...

On 02/22/2018 03:22 PM, taii...@gmx.com wrote:

On 02/17/2018 09:46 AM, Elisenda Cuadros wrote:


Hi,

Now I trying to use your OpenBMC port.

I followed the instructions and everything was fine (compiling,
reading and flashing). I waited several minutes after flashing, but
the module didn 't blinked like in the vendor rom, nor did it receive
an ip.

I halted the system because I thought maybe it needs a cold start.

After this, the system doesn't boot with the module plugged in. The
fans begin to spin for approximately 1/4 second, but nothing else.

My two fans (1 cpu & 1 chassis) have 3 pins and are low speed
(~1000rpm)

In the case I have to reflash the module, is it possible to hotplug
it?

Hotplugging is dangerous and not supported, don't do it.

Thank you very much for your support.

You can use a test clip to externally flash it via a flashing device
(not sure which can do 16 pins though, I would inquire on the flashrom
mailinglist)

Are you using the latest coreboot? AFAIK coreboot was patched to
support
OpenBMC, so you need a new version with the patches.

-- next part --
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Name: Console_Without_BMC.log.gz
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Size: 24422 bytes
Desc: not available
URL:
<http://mail.coreboot.org/pipermail/coreboot/attachments/20180223/80d225ea/attachment-0002.bin>

-- next part --
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Size: 2158 bytes
Desc: not available
URL:
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--

Message: 2
Date: Fri, 23 Feb 2018 17:01:13 -0600
From: Timothy Pearson <tpear...@raptorengineering.com>
To: Elisenda Cuadros <li...@e4l.es>
Cc: Coreboot <coreboot@coreboot.org>
Subject: Re: [coreboot] OpenBMC & KGPE-D16
Message-ID: <5a909d39.40...@raptorengineering.com>
Content-Type: text/plain; charset=UTF-8

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You can reach the pe

Re: [coreboot] Serial input / output with SeaBIOS 1.11.0

[Piotr Kubaj via coreboot]

I didn't get it working with SeaBIOS' SERCON, but I just moved on to SgaBIOS. 
It turns out it's actually better for me than SERCON, because it provides 
serial redirection to the point where kernel takes over, while SERCON only 
provides till bootloader starts.

That feature of SgaBIOS makes it possible to use full disk encryption on 
FreeBSD (without unencrypted /boot), because the password prompt just before 
bootloader is about to start and currently it's impossible to redirect it to 
serial (bootloader can be redirected to serial, password prompt can not). With 
SgaBIOS, I can get a password prompt via serial, with SERCON it's not possible 
(at least I didn't find a way to do so).

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[coreboot] HV121WX4-120 screen for X200

[Piotr Kubaj via coreboot]

Hi,

I just wanted to share my experience of using alternative screens for ThinkPad 
X200 (HV121WX4-120) with coreboot.

After fitting the screen, it became apparent that something is wrong.
Having turned on the X200, it ran happily for about 1 minute, then the screen 
just powered off. It didn't matter whether I stayed in SeaBIOS, or just booted 
my OS. And when the screen powered off, I could awake it after several minutes, 
but only for another minute. Apart from that, the laptop worked.

nico_h from IRC helped me (thank you!) by providing alternative values for 
devicetree, which could make the screen work orderly. Well, it did work better, 
but still wasn't stable (it worked for 10-20 minutes, once I even got it to 2 
hours).

Still, that was a huge difference. I tried to experiment a little with it and 
set some crazy values:
   register "gpu_panel_power_up_delay" = "600" # T1+T2: 25ms
   register "gpu_panel_power_down_delay" = "3000"  # T3:25ms
   register "gpu_panel_power_backlight_on_delay" = "500"   # T5:   250ms
   register "gpu_panel_power_backlight_off_delay" = "2500" # Tx:   250ms
   register "gpu_panel_power_cycle_delay" = "255"  # T4:   200ms

After that, things seem to work fine.

I hope someone finds it useful if they replace their X200's screen with 
alternative one.

Again thanks to Nico for help!

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[coreboot] Asus ASMB-iKVM modules

[Piotr Kubaj via coreboot]

I'm looking to buy some ASMB-iKVM module for my KGPE-D16. I've looked in all 
the Internet shops I could find, but there are none available.

Do any of you have some for sale?

I figured it may be the best place to ask about it.

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Re: [coreboot] Supported Motherboards

[Piotr Kubaj via coreboot]

@Nico
By removing open-source AGESA and all boards that use them, you would remove 
many boards that can boot blobless (like KGPE-D16 and KCMA-D8, there's also 
cheap low-end like E350M1, although I'm not sure this uses AGESA).

This would mean that if we want blobless, we can either use much less powerful 
than ASUS boards Intel-based boards from 10 years ago or use Chromebooks. This 
would severely lower the number of coreboot users.

You said we could maintain AGESA code on our own and even rewrite. I'm with 
Mike about this. I'm not a firmware engineer,  I can understand so-so what the 
code is doing but writing it is completely beyond me. I'm also engaged in other 
open-source project (I contribute to FreeBSD ports) and this doesn't leave time 
to work on coreboot.

Also, running tokei in AGESA dir currently shows:
pkubaj@KGPE-D16:$~/coreboot/src/vendorcode/amd/agesa/f15tn$ tokei
---
 Language   

 FilesLines Code Comments   Blanks
---
 Assembly   

 1  209  1840   25
 C  

   457   143870775585473711575
 C Header   

   251   1305549103829652 9864
---
 Total  

   709   274633   1687808438921464
---

The size of AGESA is currently about 10% of coreboot. Nico, do you think a 
single person working in spare time can reimplement 10% of coreboot?


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