[coreboot] [coreboot - Bug #499] coreboot will not boot edk2 on Lenovo T440p with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled, cannot disable this setting during build

[Christian Walter]

Issue #499 has been updated by Christian Walter.


Oberon 4071 wrote:
> coreboot revision in git: feb27dcbf3fc685b070c950a16e8adec958bc1ce
> coreboot revision (git describe --tags): 4.20-520-gfeb27dcbf3
> Tested payloads: edk2 from MrChromebox revision uefipayload_202304 and 
> uefipayload_202306
> 
> coreboot will not boot my Lenovo ThinkPad T440p with 
> CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled, when using the edk2 payload 
> (MrChromebox version, either uefipayload_202304 or uefipayload_202306). The 
> display sometimes turns on, indicating that some of the hardware 
> initialization was successful, but the payload will not start.
> 
> I tried to disable CONFIG_RESOURCE_ALLOCATION_TOP_DOWN in .config, but the 
> build process insists on leaving this config enabled. This seems to be caused 
> by the RESOURCE_ALLOCATION_TOP_DOWN setting changed to "def_bool y" in 
> src/device/Kconfig in commit 5226301765ded70e0ef640e5252bbaca8cd14451 
> (allocator_v4: Treat above 4G resources more natively). The make target for 
> building coreboot seems to automatically rerun olddefconfig, causing this 
> setting to always remain enabled no matter what was previously saved in the 
> .config file.
> 
> Modifying src/device/Kconfig to change RESOURCE_ALLOCATION_TOP_DOWN to 
> "def_bool n" appears to fix the problem on my machine.
> 
> I have attached my .config file (with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN 
> enabled to reproduce the problem).

We fixed the issue in our edk2 here: 
https://github.com/9elements/edk2/commit/d965778103bfe2badd815c6fe35d2786581980b3


Bug #499: coreboot will not boot edk2 on Lenovo T440p with 
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled, cannot disable this setting during 
build
https://ticket.coreboot.org/issues/499#change-1807

* Author: Oberon 4071
* Status: New
* Priority: Normal
* Assignee: Nico Huber
* Start date: 2023-06-29
* Affected versions: 4.21
* Needs backport to: none
* Related links: https://review.coreboot.org/c/coreboot/+/76198
https://review.coreboot.org/c/coreboot/+/76199
* Affected hardware: lenovo/t440p

coreboot revision in git: feb27dcbf3fc685b070c950a16e8adec958bc1ce
coreboot revision (git describe --tags): 4.20-520-gfeb27dcbf3
Tested payloads: edk2 from MrChromebox revision uefipayload_202304 and 
uefipayload_202306

coreboot will not boot my Lenovo ThinkPad T440p with 
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN enabled, when using the edk2 payload 
(MrChromebox version, either uefipayload_202304 or uefipayload_202306). The 
display sometimes turns on, indicating that some of the hardware initialization 
was successful, but the payload will not start.

I tried to disable CONFIG_RESOURCE_ALLOCATION_TOP_DOWN in .config, but the 
build process insists on leaving this config enabled. This seems to be caused 
by the RESOURCE_ALLOCATION_TOP_DOWN setting changed to "def_bool y" in 
src/device/Kconfig in commit 5226301765ded70e0ef640e5252bbaca8cd14451 
(allocator_v4: Treat above 4G resources more natively). The make target for 
building coreboot seems to automatically rerun olddefconfig, causing this 
setting to always remain enabled no matter what was previously saved in the 
.config file.

Modifying src/device/Kconfig to change RESOURCE_ALLOCATION_TOP_DOWN to 
"def_bool n" appears to fix the problem on my machine.

I have attached my .config file (with CONFIG_RESOURCE_ALLOCATION_TOP_DOWN 
enabled to reproduce the problem).



---Files
.config (20.7 KB)
console.log (128 KB)
cbmem.txt (151 KB)
cbmem_seabios_with_resource_allocation_top_down.txt (41.1 KB)
dmesg_change_76199.txt (56.7 KB)
cbmem_change_76199.txt (120 KB)
cbmem.txt (116 KB)
cbmem_top_down_n.txt (163 KB)
dmesg_top_down_n.txt (58.2 KB)
dmesg.txt (58.3 KB)
cbmem.txt (166 KB)


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[coreboot] [coreboot - Bug #401] edk2 hangs indefiniately

[Christian Walter]

Issue #401 has been updated by Christian Walter.


Is this a problem within coreboot - or do we rather need to fix up EDKII ?


Bug #401: edk2 hangs indefiniately 
https://ticket.coreboot.org/issues/401#change-1043

* Author: Sean Rhodes
* Status: New
* Priority: Normal
* Assignee: Arthur Heymans
* Category: board support
* Target version: none
* Start date: 2022-07-08
* Affected versions: master
* Affected hardware: Everything
* Affected OS: Doesn't matter

Since CB:63555, edk2 will no longer boot and hangs indefiniately

Various forks disable MTRR programming in edk2 (such as 
https://github.com/MrChromebox/edk2/commit/d641ea6920737fd9b9a94210e9a2e7636bfb3cdc)
 but this shouldn't be done as it breaks spec.

Workarounds are to revert CB:64804, CB:63550, CB:64803 and CB:63555.

---Files
with_avph_patch.txt (65.8 KB)
with_avph_patch_reverted.txt (64.6 KB)
master.txt (91.9 KB)
master_w_revert.txt (197 KB)


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[coreboot] Re: Servers?

[Christian Walter]

Hi Jeremy,Both Wiwynn and Prodrive produce servers with coreboot-based firmware that can be bought off the shelf with coreboot on it.Prodrive sells Coffee Lake based servers where as Wiwynn sells Cooper Lake Scalable (Xeon-SP) based Open Compute Project Servers, so 21-inch servers. If one of these work for you, or both, I can give you an introduction to the sales rep. of both companies.Best,ChrisVon meinem iPhone gesendetAm 13.07.2022 um 07:23 schrieb Jeremy Hansen via coreboot :  I’m really looking for something I can purchase assembled. We already have one of Purism’s hosts. We’re looking for something with a higher core density and overall availability. I know supply issues is a problem for everyone. Any more info on the hosts you manufactured?Thanks!  On Tuesday, Jul 12, 2022 at 10:17 PM, Shawn C  wrote: We manufactured small amount of servers based on x11sch-f which the coreboot support done by 9elements. It's currently support the features that most ppl need including TPMv2. CBnT had some issues still though. It's not that hard if any organization try to assemble their own Common Building Blocks x86 server. We used a assembly factory in Shenzhen. Sure you can find similar vendors in other region (Vietnam/Mexico?).  regards Shawn   On Tuesday, July 12th, 2022 at 11:01 PM, Jeremy Hansen via coreboot  wrote:   I’ve looked at the list of hardware vendors. I see System76 listed but when I asked System76, they claim it’s not supported.  “Support” I understand, but does it work? Maybe using their System76 firmware?  Any other server vendors I should consider? I know Purism offers servers as well.  Anyone else?  Thank you -jeremy   ___coreboot mailing list -- coreboot@coreboot.orgTo unsubscribe send an email to coreboot-le...@coreboot.org

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[coreboot] Open-Source Firmware Conference 2022 in Sweden, Gothenburg, September 19-21

[Christian Walter]

Hi,

finally! We can meet in person again. After the hackathon next week in 
Darmstadt, and the Linux Plumber in September, the Open-Source Firmware 
Conference will take place in Sweden, Gothenburg from September 19th - 21th.


The Call for Participation already started and the deadline is set to 
the 25th of June. As you know, the OSFC is the biggest open-source 
firmware conference world-wide, and we would love to welcome you again 
in person in Gothenburg. We are looking forward to two days of 
conference and one day of pure hackathon - all around open-source firmware.


So feel free to participate in the CfP - or just get yourself an 
early-bird ticket. There are also reduced community tickets (non business).


Looking forward to meet you in person again!

Best Regards,

Chris

PS: Obviously, check out https://www.osfc.io

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[coreboot] Re: Support to Openpower platforms

[Christian Walter]

Can we push this documentation upstream?

Von meinem iPhone gesendet

> Am 31.03.2022 um 22:38 schrieb David Hendricks :
> 
> 
> 3mdeb has been working on this. Here is some documentation with resources to 
> get started: https://github.com/3mdeb/openpower-coreboot-docs. They've also 
> given several recent talks about this, and many of their patches have been 
> merged into upstream coreboot.
> 
> If you've got a Talos II or other POWER9 platform I'm sure they'd love some 
> help testing it :-)
> 
>> On Thu, Mar 31, 2022 at 12:46 PM ratatouille gamer 
>>  wrote:
>> the openpower have created this new firmware for boot openpower platforms
>> is possible to coreboot use this base to write a new code for best support 
>> in openpower socs?
>> https://github.com/open-power/hostboot
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[coreboot] Re: "Private" changes on Gerrit are now disabled and removed

[Christian Walter]

Yeah - no.

The GPL allows you do keep your modifications private as long as you do not 
release them in any way. So if these private changes are not released somewhere 
they do not need to be public.

Chris

> 
> Am 12.11.2021 um 11:06 schrieb Keith Emery :
> 
> Your well within your rights not to. I don't believe anyone should be 
> compelled to expend effort for which they are not compensated.
> 
> But would anyone else like to explain why this isn't a GPL violation? Because 
> it really seems like it is.
> 
> 
>> On 12/11/21 8:44 pm, Patrick Georgi wrote:
>> 12. November 2021 10:31, "Keith Emery"  
>> schrieb:
>>> I'm fairly sure it say's 'you must publish the source code AND any 
>>> changes'. Did that change at some point?
>> I'm fairly sure that you don't understand the conditions under which the GPL 
>> takes effect. Since I'm not your lawyer, I won't discuss this with you any 
>> further.
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[coreboot] Re: Status of Tianocore EDK2 on Coreboot

[Christian Walter]

Hi Julian,

There are a couple of Repo's you can check out:

https://github.com/tianocore/edk2

https://github.com/MrChromebox/edk2

https://github.com/9elements/edk2

https://github.com/system76/edk2


We are using our own Fork (9elements) on a CFL Board in production. Also 
System76 does use their Fork in production - so setting this up in a 
virtualized environment shouldnt be a problem at all. To be honest, I 
would not start with the tianocore one, use one of the forks ;)


Best,

On 4/16/21 1:44 PM, Julian Stecklina wrote:

On Thu, 2021-04-15 at 16:49 +, Andy Pont wrote:

Julian wrote…


Is anyone actually actively using TianoCore EDK2 on top of coreboot or is
support experimental in general?

We have platforms that are using Matt’s UEFIPayload package to boot
either Linux or Windows.  The mainboards and configs aren’t in the
upstream coreboot repo at present - I am just working with the company
concerned to get them into a form where they will (hopefully) be
accepted.

This is great news! We are mostly interested in running Coreboot+EDK2 in a
virtualized environment and knowing that it works in the real world gives a
confidence boost here.

We are not afraid of fixing the occasional issue and bitrot, but fully
maintaining everything is out of scope for us.

Julian

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[coreboot] Re: Running QEMU targets in Jenkins

[Christian Walter]

Hi Julius,

you can also check this out: https://lava.9esec.io/scheduler/alljobs

It currently runs on:
* Various QEmu Targets
* HP Z220
* HP8200
* Lenovo T500

we are about to add another target (Prodrive Hermes / CFL).

If you have more ideas what could be added with little effort - feel 
free to ping us. :)


Best,

Chris

On 3/4/21 11:14 AM, Patrick Georgi via coreboot wrote:

Hi Julius,

https://qa.coreboot.org/job/coreboot-boot-test/ 
<https://qa.coreboot.org/job/coreboot-boot-test/> sends off ToT builds 
to 9esec's Lava system where they are run on some virtual and real 
devices. See for example the comments to 
https://review.coreboot.org/c/coreboot/+/51189 
<https://review.coreboot.org/c/coreboot/+/51189> where Lava reports 
passing on 5 qemu configs and 3 real devices.



Regards,
Patrick

Am Do., 4. März 2021 um 02:42 Uhr schrieb Julius Werner 
mailto:jwer...@chromium.org>>:


I'm just curious... have we ever considered booting some of our QEMU
targets as part of the Jenkins CI? I know they don't do a lot but they
do cover some stuff (e.g. CBFS). I randomly happened to boot one of my
in-flight patch trains on qemu-i440fx recently and discovered that I
accidentally broke rmodule loading. Would be nice if Jenkins could
just do that for you automatically.

Just wanted to know whether this had been discussed before and people
have come up with good reasons not to do it, or if it's just a matter
of nobody had time to implement it yet. (And if someone wanted to
implement it, what would be the best hook point? Put it into abuild?)



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[coreboot] Re: Intel CBnT tooling and dealing with NDA

[Christian Walter]

Hi,

thanks for the feedback. I am totally on your site that this is not an 
ideal solution - however the coreboot community has to think about how 
to work around these issues. Stating that this just does not get merged 
into the tree is not a good solution, as we are not moving forward on 
these topics and can not compete with proprietary solutions if we are 
holding on to the statement that also tooling needs to be open-source.


Don't get me wrong - I love open-source and don't understand why these 
things, especially when they are security critical, are closed-source. 
That is against what I learned from as a security researcher - and this 
is what security does for years now - open-sourcing the concepts, 
algorithms and so on.


So - I am always a fan on moving forward, and also moving fast forward. 
However: we cleared out the NDA issues and released the tool into the 
public [1]. That being said - NDA issues are off the table now.


---

Golang did quite some work on the dependency system and I know it tends 
to be confusing. But things get better - plus python is not any better 
on that. But don't get me started on that ;)



Best,

Chris


[1]: https://github.com/9elements/converged-security-suite/

On 2/23/21 12:26 PM, Enrico Weigelt, metux IT consult wrote:

On 09.02.21 13:14, Christian Walter wrote:

Hi,

As Arthur pointed out, we would hope to integrate this as a binary as 
a temporary solution, until Intel clears out the NDA issues. 


I really don't like this idea. As it's a special case for the time
being, this can live in some extra branch, possibly extra repo, just
for those few folks who really need it right now.

Adding binary cruft to the mainline removed the pressure for folks
like Intel (which is an exceptionally ugly player in this regard)
to clear up everyhing. They should feel the presure of being ignored
(at best), until they provide a really clean solution. They should learn
once for all that those things never should have been under NDA in the
first place.

Note: this has nothing to do with (dis)repsect regarding your work.

And also in the sense of moving forward, I would like to choose 
Golang over C in this case.


hmm, golang in general is a bit problematic in distro context.
(anyone, who tried clean packaging and build process of golang
and go applications for distros like Debian, knows what I'm talking
about :p) ... it's a nice language, but getting their own ecosystem
isle (damn, they even built their own wannabe package manager) play
along nicely with distros is a pretty huge and non-trival job.

Personally, for that kind of job, I'd prefer something like Python :p


--mtx


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[coreboot] Re: Regarding GSoC 2020

[Christian Walter]

Hi,

you could also join the OSF-Slack Channel. You'll get an invite here: 
https://slack.osfw.dev/


There is also a #coreboot-dev channel

Best,

Chris

On 2/22/21 12:31 PM, Vedant Paranjape wrote:
Thanks for the update. I joined coreboot IRC, it doesn't seem active. 
Any other communication channel to lookout for?


On Mon, 22 Feb, 2021, 16:56 Patrick Georgi, <mailto:pgeo...@google.com>> wrote:


Hi Vedant,

coreboot has applied to this year's GSoC but GSoC still has to
decide on the projects they want to host: That will be announced
on March 9.


Patrick

Am Sa., 20. Feb. 2021 um 07:40 Uhr schrieb
mailto:vedantparanjape160...@gmail.com>>:

Hi, I am interested to apply to gsoc2020, is coreboot going to
apply in gsoc 2021?

Regards,
Vedant Paranjape
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[coreboot] Re: Intel CBnT tooling and dealing with NDA

[Christian Walter]

Hi Michal,

this _could_ have been a good starting point - however we decided to 
integrate this into the Converged Security Suite 
(github.com/9elements/converged-security-suite 
<http://github.com/9elements/converged-security-suite>) which already is 
part of coreboot as a 3rdparty module. However even if we _would_ extend 
your tooling - NDA issues still are not resolved. As Arthur pointed out, 
we would hope to integrate this as a binary as a temporary solution, 
until Intel clears out the NDA issues. And also in the sense of moving 
forward, I would like to choose Golang over C in this case.


Best,
Chris

Am Di., 9. Feb. 2021 um 12:14 Uhr schrieb Michal Zygowski 
mailto:michal.zygow...@3mdeb.com>>:


   Hi Christian,

   On 09.02.2021 11:58, Christian Walter wrote:

> Hi Michal,
>
> mind pointing me to the tooling you make for *creating* these
   manifests?
>
   There is a whole intel_bootguard topic:
   https://review.coreboot.org/q/topic:intel_bootguard
   <https://review.coreboot.org/q/topic:intel_bootguard>
   In particular have a look at these patches:
   - Tool: https://review.coreboot.org/c/coreboot/+/43403
   <https://review.coreboot.org/c/coreboot/+/43403>
   - Hook manifest creation into build system:
   https://review.coreboot.org/c/coreboot/+/43404
   <https://review.coreboot.org/c/coreboot/+/43404>

   The manifests layout is implemented in the tool. Although it creates the
   v1.0 manifests and AFAIK CBnT required v2.1 format, but this tool can be
   a good base, isn't it?


   Best regards,

   -- 
   Michał Żygowski

   Firmware Engineer
   https://3mdeb.com <https://3mdeb.com> | @3mdeb_com

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[coreboot] Re: Intel CBnT tooling and dealing with NDA

[Christian Walter]

Hi Michal,

mind pointing me to the tooling you make for *creating* these manifests?

Am Di., 9. Feb. 2021 um 11:46 Uhr schrieb Michal Zygowski <
michal.zygow...@3mdeb.com>:

> Hi,
>
> On 09.02.2021 11:02, Arthur Heymans wrote:
> > Hi
> >
> > To make Intel CBnT (Converged Bootguard and TXT) useful in coreboot some
> > tooling is required to generate both a Key Manifest (A signed binary,
> > that is checked
> > against a key fused into the ME, holding keys that OEM can use to sign
> the BPM)
> > and a Boot Policy Manifest (signed binary, has a digest of IBBs,
> > Initial Boot Blocks).
> > At the moment these are included as binaries by the build system.
> >
> > Obviously this only works if the IBB hasn't changed. If it changed, you'd
> > need to regenerate the BPM. 9elements has written some open source
> tooling
> > (BSD-3 clause) to generate both KM and BPM. The code for this tool is
> not yet
> > public as it was written using NDA documentation. Intel is currently
> reviewing
> > this to allow us to make it public, but this takes time. It will be
> > part of the 3rdparty/intel-sec-tools
> > submodule.
>
> What is the diff between BtG and CBnT manifests format? Is the work that
> we (3mdeb) did, not usable?
>
> Best regards,
>
> --
> Michał Żygowski
> Firmware Engineer
> https://3mdeb.com | @3mdeb_com
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[coreboot] Re: AMD AGESA: Missing PCI bridge 00:15.2 on Asus F2A85-M PRO

[Christian Walter]

Hi,

if we are sure it is behind 15.2 - one can also try to make it hidden.
This way the device will be enabled no matter what. If that solves the
problem - you need to investigate why coreboot does not enable the device.

Best,

Chris

On 10/16/20 3:05 PM, Peter Stuge wrote:
> Paul Menzel wrote:
>> With the vendor firmware 6601, it is
>>
>>  04:00.0 Ethernet controller [0200]: Realtek Semiconductor Co., Ltd. 
>> RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller [10ec:8168] 
>> (rev 09)
>>
>> behind PCI bridge 00:15.2.
> ..
>> In the current state [1], coreboot says device 00:15.2 is disabled
>>
>>> Show all devs... After init.
> ..
>>> PCI: 00:15.0: enabled 1
>>> PCI: 00:15.1: enabled 1
>>> PCI: 00:15.2: enabled 0
>> But it is enabled in the devicetree 
>> `src/mainboard/asus/f2a85-m/devicetree_f2a85-m_pro.cb`.
>>
>>  device pci 15.2 on end # PCI bridge
>> spew log
> ..
>> Enabling cache
>> Setting up local APIC...
>>  apic_id: 0x11 done.
>> siblings = 01, CPU #1 initialized
>> All AP CPUs stopped (1060 loops)
>> CPU0: stack: 0x5fef4000 - 0x5fef5000, lowest used address 0x5fef455c, stack 
>> used: 2724 bytes
>> CPU1: stack: 0x5fef3000 - 0x5fef4000, lowest used address 0x5fef3dbc, stack 
>> used: 580 bytes
>> CPU_CLUSTER: 0 init finished in 64 msecs
>> PCI: 00:00.0 init
>> PCI: 00:00.0 init finished in 0 msecs
> ..
>> PCI: 00:15.0 init
>> PCI: 00:15.0 init finished in 0 msecs
>> PCI: 00:15.1 init
>> PCI: 00:15.1 init finished in 0 msecs
>> PCI: 00:18.1 init
>> PCI: 00:18.1 init finished in 0 msecs
> Note that there is no init for 15.2 above. I don't know why, if it's
> enabled in the mainboard devicetree file.
>
>
> Another thought - have you compared PCI bus numbers and addresses
> between vendor BIOS and coreboot? They can change around, certainly
> bus numbers but wasn't there a thread a while back with addresses
> being confused too?
>
>
> Sorry I can't suggest anything more concrete
>
> //Peter
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*Christian Walter*
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[coreboot] Re: Bios Corrupted

[Christian Walter]

Hi Miraz,
What laptop/mainboard are you running?

Best,
Chris 

Von meinem iPhone gesendet

> Am 04.10.2020 um 22:19 schrieb Miraz Shuvra :
> 
> 
> Hello sir , 
> 
> 
> I need a little bit help 
> 
> I accidentally corrupted bios of my laptop during bios update 
> ...before it blackout... i saw the txt .." searching for bios firmware ... 
> bios firmware not found "
> 
> I baught a ch341A usb bios programming device ...
> I think a .bin file may bring my laptop back to life.
> 
> My laptop ran with ami bios 
> The bios chip is 25Q80DVS IG 1646
> 
> Can you pls help me anyway.
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[coreboot] Re: Should coreboot.org provide a vendor-agnostic hub for open hardware projects?

[Christian Walter]

Hi Patrick,

what does "coreboot compatible open hardware" means here? Do we have
some kind of specification for this or does that "just" means no blobs
at all?

I would think that we can definitely host such a projects, give it a
gerrit, docs and stuff - but I would be aware of leveraging resources
for this. I don't think that we should promote this in any way or brand
it as coreboot compatible open hardware.

Best,

Chris

On 9/23/20 7:54 PM, Patrick Georgi via coreboot wrote:
> Hi everybody,
>
> I heard about a project interested int creating coreboot compatible
> open hardware. While that effort isn't ready to make any announcement,
> questions came up about where to host such a project.
>
> There's lots of open hardware out there already, but it's often
> based on not-quite open base boards so there seems to be a hole in
> the ecosystem approximately the shape of open hardware designs that
> could serve as base for hardware of all sizes (SBC alikes to put
> "shields" on, laptop/desktop designs that can be customized, maybe
> even servers, ...)
>
> That's where coreboot.org might come in: When I brought up the question in
> today's leadership meeting, people were generally interested in having
> coreboot.org host projects like that.
>
> The idea isn't to create "coreboot branded" hardware, because that
> makes as much sense as "UEFI branded" hardware (that is, none), but to
> provide a place where people can cooperate on and publish open hardware
> designs that are complex enough to require coreboot-style firmware.
>
>
> Thoughts?
> Patrick
>
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[coreboot] Re: Intel Firmware Descriptor

[Christian Walter]

Hi Andy,
If you already have a stock bios you can extract it with the ifdtool (ifdtool 
-x Image.bin). If you are doing a port for a hardware which happened to have no 
stock bios you need to generate the ifd and me with intels fitc tooling.
Best,
Chris

Von meinem iPhone gesendet

> Am 18.09.2020 um 16:09 schrieb Andy Pont :
> 
> Hello,
> 
> I’m working on porting Coreboot to a laptop that uses Intel Comet Lake.  When 
> the build completes it spits out the following warning:
> 
>** WARNING **
> coreboot has been built without an Intel Firmware Descriptor.
> Never write a complete coreboot.rom without an IFD to your
> board's flash chip! You can use flashrom's IFD or layout
> parameters to flash only to the BIOS region.
> 
> What is an IFD and how do I create one?
> 
> -Andy.
> 
> 
> 
> 
> 
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[coreboot] Re: Building coreboot for custom design

[Christian Walter]

HI Derryl,

I don't think that there is such a document. The best guidance is still
the old wiki: https://www.coreboot.org/Motherboard_Porting_Guide .
Otherwise you might need to check back with one of the consulting
partners (https://coreboot.org/consulting.html) - or join the slack
channel for more guidance on this. Building coreboot for custom design
does require more knowledge as "just" porting coreboot, as there is no
reference i.e. the stock bios.

Best,

Chris

On 8/18/20 12:53 PM, Derryl Tauro wrote:
> Hi,
>
> I have been doing research on building coreboot to a custom design
> with Intel chipset. I couldn't find an appropriate document for the
> same. Is there a document available that I have missed?
>
> Regards,
> Derryl Tauro
>
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*Christian Walter
Head of Firmware Development / Cyber Security*



9elements GmbH, Kortumstraße 19-21, 44787 Bochum, Germany
Email:  christian.wal...@9elements.com
Phone:  _+49 234 68 94 188 _
Mobile:  _+49 17670845047 _

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[coreboot] Re: UEFI bios menu

[Christian Walter]

HI Andrey,

in addition to what Nico said - EDK2 Tianocore does already provide a
minimal BIOS Gui including things such like Boot Device Selection. You
might ne to clarify what _exactly_ you are looking for. But most
probably if you want more than that, it is a custom solution.

Best,

Chris

On 7/9/20 10:42 AM, Nico Huber wrote:
> Hello Andrey,
>
> On 08.07.20 12:05, avi...@gmail.com wrote:
>> Does it mean I can not use EDK II a full platform implementation with BIOS 
>> gui and use in coreboot ?
> if you have such a "BIOS gui", you can integrate it with the tianocore
> payload for coreboot. However, how to integrate it is more an EDK topic
> than a coreboot one. So few people on this mailing list would know some-
> thing about it.
>
> Also, I wonder what exactly is it that you call "a full platform imple-
> mentation"? If you'd really have everything in EDK II, what would you
> need coreboot for? The general idea of coreboot+payload is to have
> everything mainboard and chip specific handled by coreboot. And only
> use standard hardware interfaces in the payload to load an OS and,
> optionally, interact with the user.
>
> Nico
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Email:  christian.wal...@9elements.com
Phone:  _+49 234 68 94 188 _
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[coreboot] Re: How newbie can contribute to the project as developper

[Christian Walter]

Hi,

First of all: Welcome. The best thing to do would be to either join the
IRC channel or Slack channel that we do have. You can find the IRC
Channel on https://coreboot.org/developers.html in the community
section. To be invited into the slack channel go here:
http://slack.u-root.com/ . Not sure on what you current expertise is
with firmware - a good starting point might be checking out the
documentation on doc.coreboot.org - There is also a tutorial section
where you can easily get started.

Hope this helps a little bit.

Best,

Chris

On 7/3/20 3:06 PM, NJONGDSI KOUAM Esaïe Ledoux wrote:
> Hey everyone , ...
> i'm newbie and i want to contribute to the project as developer.
> I'm student in computer science and i like low level developing language as C 
> and Assembly .
>
> Since 12 weeks , i try to contact some person or developer to help me to 
> contribute to the project.
> Please can we give me some starting or fundamentals to contribute at the 
> project as developer ??, ...
>
> github : https://github.com/kouamdo
> ID: 1003005
> Username : kouamdo
>
> thank you ...
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[coreboot] Re: Status of Supermicro X11 series?

[Christian Walter]

HI Stephane,

currently following x11 Supermicro boards are supported:

* x11ssh-tf
* x11ssm-f

The board status list is not always update and not very convenient to
update.

Let me know if you need to know more.

Chris


On 5/25/20 1:10 PM, Stéphane Delaunay via coreboot wrote:
> Hi all,
>  
> I just wanted to ask about the current status of the Supermicro
> X11-series of boards.
>  
> I read on a German magazine that it should be supported by joint
> efforts of 9elements and Mullvad. Link (auto-translated):
> https://translate.google.com/translate?hl==de=en=https%3A%2F%2Fwww.heise.de%2Fnewsticker%2Fmeldung%2FOffene-Coreboot-Firmware-fuer-Xeon-Serverboard-4490578.html
>
>  
> Apparently there was a presentation planned at the OSFC 2019, but I
> can't find anything on it and the boards-list still shows them as
> status "Unknown", which seems odd.
>  
> Does somebody have any infos on the current development with these
> boards?
>  
> Kind regards!
>
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Email:  christian.wal...@9elements.com
<mailto:christian.wal...@9elements.com>
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[coreboot] Season of Docs - Mentors

[Christian Walter]

Hi,

I just registered coreboot at the season of docs [1]. The idea is that
technical writers can improve our documentation - therefore we are
looking for people who are willing to mentor such technical writers. The
registration for mentors can be found here [2] - be aware that the
deadline is already on May 4h, so in two days! I already created a list
of documentation ideas here [3].

The Timeline of season of docs can be found on the homepage. The
mentoring phase would start in June/July and will go throughout the year
until the end of year. Always two mentors need to work with one
technical writer on a project. So don't feel shy - you are not alone :)

Before you register yourself, please check out the mentoring guide here.
It gives you an idea on what you need to do as a mentor. [4]

Best Regards,

Chris

[1] : https://developers.google.com/season-of-docs
[2] : https://bit.ly/gsod-mentor-reg
[3] : https://doc.coreboot.org/contributing/documentation_ideas.html
[4] : https://developers.google.com/season-of-docs/docs/mentor-guide

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