Re: [coreboot] [ANN] Port of GPL vgabios to gcc

Am Mittwoch, den 06.05.2009, 23:53 -0400 schrieb Kevin O'Connor: […] > The new code can be found in the SeaBIOS git repository. To download > and build the code use: > > git clone git://git.linuxtogo.org/home/kevin/seabios.git > cd seabios/ > make out/vgabios.bin I am wondering, if a separate

[coreboot] [PATCH] flashrom: Check return codes of spi_write_enable

Until the ICH SPI driver can handle preopcodes as standalone opcodes, we should handle such special opcode failure gracefully on ICH and compatible chipsets. This fixes chip erase on almost all ICH+VIA SPI masters. Thanks to Ali Nadalizadeh for helping track down this bug! Signed-off-by: Carl-Da

Re: [coreboot] [ANN] Port of GPL vgabios to gcc

Hi Kevin, Great, I think this is what libv or I need. I have in plan to create some simple mode3 only VGA rom for K8M890. I have some questions: Have you spoken with orig authors? Maybe they want such rewrite too Is it really GPLv3? I thought it was LGPL. The resulting rom image is indepen

Re: [coreboot] [PATCH] flashrom: Check return codes of spi_write_enable

On 07.05.2009 13:44, Carl-Daniel Hailfinger wrote: > Until the ICH SPI driver can handle preopcodes as standalone opcodes, we > should handle such special opcode failure gracefully on ICH and > compatible chipsets. > > This fixes chip erase on almost all ICH+VIA SPI masters. > > Thanks to Ali Nadal

Re: [coreboot] [flashrom] Transaction Error with opcode 0x03 failed...

Hi, Thanks for the explanation. After looking at the ICH9 specification, i'm thinking of modifying the FRAP register value in order to enable write and read permission to all the region. However, i have a question: How to exactly use flashrom to bring the SPI into descriptor mode so that i can do

Re: [coreboot] [PATCH] flashrom: Check return codes of spi_write_enable

Erasing Confirmed working on my hardware : chip-set : "Intel ICH7M" chip : "SST SST25VF080B" Output image is now completely full of 0xFF (s) Regards -- Ali Nadalizadeh On Thu, May 7, 2009 at 4:48 PM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2...@gmx.net> wrote: > On 07.05.2009 13:44, Carl-

[coreboot] [PATCH] flashrom: List chipset test status

See patch. I'm also working on wiki-sytax output for of the status tables so we can easier sync "flashrom --whatever" output to the wiki. This patch is one of several preconditions to make that possible. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.or

Re: [coreboot] [PATCH] flashrom: List chipset test status

On 07.05.2009 14:39, Uwe Hermann wrote: > See patch. > > I'm also working on wiki-sytax output for of the status tables so we can > easier sync "flashrom --whatever" output to the wiki. This patch is one > of several preconditions to make that possible. > > Store and display chipset test status (no

Re: [coreboot] [ANN] Port of GPL vgabios to gcc

On Thu, May 07, 2009 at 01:33:55PM +0200, Rudolf Marek wrote: > Hi Kevin, > > Great, I think this is what libv or I need. I have in plan to create > some simple mode3 only VGA rom for K8M890. > > I have some questions: > > Have you spoken with orig authors? Maybe they want such rewrite too > Is

Re: [coreboot] [ANN] Port of GPL vgabios to gcc

On Thu, May 07, 2009 at 09:21:01AM +0200, Paul Menzel wrote: > Am Mittwoch, den 06.05.2009, 23:53 -0400 schrieb Kevin O'Connor: > > The new code can be found in the SeaBIOS git repository. To download > > and build the code use: > > > > git clone git://git.linuxtogo.org/home/kevin/seabios.git > >

Re: [coreboot] [flashrom] RE: Tyan Product Listings

On Wed, May 06, 2009 at 05:45:44PM +0200, Peter Stuge wrote: > > Can we have the S5397 motherboard added to the compatibility > > listings? > > The list which is included in the utility itself (flashrom -L) only I'll fix that, patch almost done, will send later. Uwe. -- http://www.hermann-uwe.

[coreboot] [PATCH] flashrom: Handle one-byte SPI writes

Chips like the SST SST25VF080B can only handle single byte writes outside AAI mode. Change SPI architecture to handle 1-byte chunk chip writing differently from 256-byte chunk chip writing. Convert all flashchips.c entries with SPI programing to the 256-byte version by default. Change the flashc

[coreboot] [flashrom] r472 - trunk

Author: uwe Date: 2009-05-07 15:24:49 +0200 (Thu, 07 May 2009) New Revision: 472 Modified: trunk/chipset_enable.c Log: Store and display chipset test status (not only chip status). The list of tested chipsets is synced from the wiki. Also, split the chipset vendor and name into two fields for

[coreboot] coreboot and Intel 5100 chipset compatibility question

Hello, I am trying to find out whether coreboot is compatible with Intel 5100 chipset. I know that it is not listed on the compatibility page of the coreboot website, but I was wondering if anyone has done any work with it or if there are any plans to make it compatible in the future. Any informati

Re: [coreboot] [PATCH] flashrom: Handle one-byte SPI writes

On 07.05.2009 15:14, Carl-Daniel Hailfinger wrote: > Chips like the SST SST25VF080B can only handle single byte writes > outside AAI mode. > > Change SPI architecture to handle 1-byte chunk chip writing differently > from 256-byte chunk chip writing. > > Convert all flashchips.c entries with SPI pr

Re: [coreboot] [PATCH] Disable AC97 modem early on IP1000

On Thu, 07 May 2009 02:01:18 -0400, Joseph Smith wrote: > > This patch disables the AC97 modem via the ICH4 LPC disable function > register early in the boot process. Leaving it enabled was causing > resource > allocation problems, making IO read/writes under 0x200 fail. As I found > out > by

Re: [coreboot] [PATCH] Assign PIRQs in mainboard Config.lb for IP1000 and RM4100

On Thu, 07 May 2009 02:12:00 -0400, Joseph Smith wrote: > This patch sets up PIRQs in mainboard Config.lb for IP1000 and RM4100 > instead of using the ones in i82801xx_lpc.c > > Signed-off-by: Joseph Smith > ACK here too please? -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org --

Re: [coreboot] [PATCH] flashrom: List chipset test status

On Thu, May 07, 2009 at 02:46:47PM +0200, Carl-Daniel Hailfinger wrote: > If you change vendor and name to vendor_name and device_name, this is > Acked-by: Carl-Daniel Hailfinger Thanks, r472. Uwe. -- http://www.hermann-uwe.de | http://www.holsham-traders.de http://www.crazy-hacks.org | http

Re: [coreboot] GSoC: Seabios USB Option ROM, small initial planning

Hi all, On Wed, May 6, 2009 at 10:05 PM, Leandro Dorileo wrote: > Hi Guys > > I was talking to Jason and we found we need to draw a bit better the > API and responsibilities between us. I figure out I`m going to support > hardware detection and initialization, and a framework to read and > write

Re: [coreboot] [flashrom] Transaction Error with opcode 0x03 failed...

Yu Ning, thank you very much again. BTW, an unrelated question: Generating OPCODES... done does this line mean that no opcodes at all were generated? I wonder why that could be. -- Andriy Gapon -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] cbfs XIP patch

Just catching up on this discussion so I applogize if these ideas have already been hashed out. I think that the original idea Jordan had was that the alignment is in the master header. Each component is always header and data together. The component header has the length. Given the alignment and

Re: [coreboot] GSoC: Seabios USB Option ROM, small initial planning

Hi Jason On Thu, May 7, 2009 at 11:34 AM, Jason Wang wrote: > Hi all, > > On Wed, May 6, 2009 at 10:05 PM, Leandro Dorileo wrote: >> >> Hi Guys >> >> I was talking to Jason and we found we need to draw a bit better the >> API and responsibilities between us. I figure out I`m going to support >>

[coreboot] status of coreboot on Asus A8N-E

Hi there, I have an A8N-E from Asus and according to your wiki it is supported by coreboot: http://www.coreboot.org/ASUS_A8N-E I did search the wiki, mailing list archives and even had a look at the source. But I am not sure about the statement about the PCIx16 slot: "Doesn't seem to work, yet

Re: [coreboot] GSoC: Seabios USB Option ROM, small initial planning

On Wed, May 6, 2009 at 8:05 AM, Leandro Dorileo wrote: > For now, I have two major questions, #1: I`ve seen other projects like > FILO including libpayload with svn:external, once seabios is > maintained with git, how it should be done with seabios? how would we > manage the source code integratio

Re: [coreboot] [flashrom] Transaction Error with opcode 0x03 failed...

Stan Yong wrote: > i'm thinking of modifying the FRAP register value in order to enable write > and read permission to all the region. (I don't like giving discouraging information. I have given much.) I am afraid that it could not be done if datasheet is correct. As you may have read in the dat

Re: [coreboot] [flashrom] Transaction Error with opcode 0x03 failed...

Andriy Gapon wrote: > Yu Ning, thank you very much again. You are welcome. > Generating OPCODES... done > > does this line mean that no opcodes at all were generated? > I wonder why that could be. I think it means opcodes have been successfully generated. The difference you saw may be caused by c

Re: [coreboot] [PATCH] flashrom: Check return codes of spi_write_enable

Carl-Daniel wrote: > Until the ICH SPI driver can handle preopcodes as standalone opcodes ... I don't like ICH's preop design either. However, I think we shall write software following the hardware design's policy. Trying to compensate defect of hardware design costs and probably not gains more.

[coreboot] [PATCH] flashrom: print hex in ich_spi_read_page

Print the value of offset in hex. Hex values are easier to debug. Signed-off-by: FENG Yu Ning Index: trunk/ichspi.c === --- trunk/ichspi.c (revision 472) +++ trunk/ichspi.c (working copy) @@ -628,7 +628,7 @@ uint32

[coreboot] Board enable for Epox 8K5A2.

I didn't prepend this with [PATCH] yet, as i still need to verify this change on an epia-m with its original bios... This patch adds support for the Epox 8k5a2 motherboard as owned by Kevin Sopp (CC). His lspci is attached for future reference. Kevin still needs to try this code too. His board

Re: [coreboot] Board enable for Epox 8K5A2.

On Thu, May 07, 2009 at 07:14:03PM +0200, Luc Verhaegen wrote: > I didn't prepend this with [PATCH] yet, as i still need to verify this > change on an epia-m with its original bios... > > This patch adds support for the Epox 8k5a2 motherboard as owned by Kevin > Sopp (CC). His lspci is attached

Re: [coreboot] Board enable for Epox 8K5A2.

On Thu, May 07, 2009 at 07:14:03PM +0200, Luc Verhaegen wrote: > @@ -152,6 +152,65 @@ > } > > /** > + * w83627: Enable MEMW# and set ROM size to max. > + */ > +static void w8326xx_memw_enable(uint16_t index) > +{ > + w836xx_ext_enter(index); > + if (!(wbsio_read(index, 0x24) & 0x02)) {

Re: [coreboot] [PATCH] Disable AC97 modem early on IP1000

> -Original Message- > From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] > On Behalf Of Joseph Smith > Sent: Thursday, May 07, 2009 12:09 AM > To: coreboot > Subject: Re: [coreboot] [PATCH] Disable AC97 modem early on IP1000 > > > > On Thu, 07 May 2009 02:01:18

Re: [coreboot] [PATCH] Assign PIRQs in mainboard Config.lb for IP1000and RM4100

> -Original Message- > From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] > On Behalf Of Joseph Smith > Sent: Thursday, May 07, 2009 12:12 AM > To: coreboot > Subject: [coreboot] [PATCH] Assign PIRQs in mainboard Config.lb for > IP1000and RM4100 > > This patch set

Re: [coreboot] [PATCH] flashrom: Handle one-byte SPI writes

Hello, This might work, but, if I can say, I don't like the idea of renaming the ich_spi_write to ich_spi_write_256. 1) ich_spi_write() looks to be the generic one, then, this one has the good name. 2) ich_spi_write() should already use something, stored in the relevant flashchips[] item, to pe

Re: [coreboot] [PATCH] flashrom: Handle one-byte SPI writes

Hi, On 08.05.2009 01:05, stephan.guill...@free.fr wrote: > This might work, but, if I can say, I don't like the idea of renaming the > ich_spi_write to ich_spi_write_256. > > 1) ich_spi_write() looks to be the generic one, then, this one has the good > name. > The big problem is that the stand

[coreboot] [v2] r4258 - trunk/coreboot-v2/src/mainboard/thomson/ip1000

Author: linux_junkie Date: 2009-05-08 02:19:13 +0200 (Fri, 08 May 2009) New Revision: 4258 Modified: trunk/coreboot-v2/src/mainboard/thomson/ip1000/gpio.c Log: Disable the AC97 modem via the ICH4 LPC disable function register early in the boot process. Signed-off-by: Joseph Smith Acked-by: My

Re: [coreboot] [PATCH] Disable AC97 modem early on IP1000

On Thu, 7 May 2009 15:55:11 -0600, "Myles Watson" wrote: > > >> -Original Message- >> From: coreboot-boun...@coreboot.org > [mailto:coreboot-boun...@coreboot.org] >> On Behalf Of Joseph Smith >> Sent: Thursday, May 07, 2009 12:09 AM >> To: coreboot >> Subject: Re: [coreboot] [PATCH] D

[coreboot] [v2] r4259 - in trunk/coreboot-v2/src/mainboard: rca/rm4100 thomson/ip1000

Author: linux_junkie Date: 2009-05-08 02:24:24 +0200 (Fri, 08 May 2009) New Revision: 4259 Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb Log: Set up PIRQs in mainboard Config.lb for IP1000 and RM4100 instead of using t

Re: [coreboot] [PATCH] Assign PIRQs in mainboard Config.lb for IP1000and RM4100

On Thu, 7 May 2009 15:55:37 -0600, "Myles Watson" wrote: > > >> -Original Message- >> From: coreboot-boun...@coreboot.org > [mailto:coreboot-boun...@coreboot.org] >> On Behalf Of Joseph Smith >> Sent: Thursday, May 07, 2009 12:12 AM >> To: coreboot >> Subject: [coreboot] [PATCH] Assig

[coreboot] [v2] r4260 - in trunk/coreboot-v2: src/mainboard/rca/rm4100 src/mainboard/thomson/ip1000 targets/thomson/ip1000

Author: linux_junkie Date: 2009-05-08 02:45:47 +0200 (Fri, 08 May 2009) New Revision: 4260 Modified: trunk/coreboot-v2/src/mainboard/rca/rm4100/Config.lb trunk/coreboot-v2/src/mainboard/thomson/ip1000/Config.lb trunk/coreboot-v2/targets/thomson/ip1000/Config.lb Log: Trivial fixup IRQS on

[coreboot] [PATCH] flashrom: Trim default ICH SPI delay from 1000 to 10 microseconds

Trim default ICH SPI delay from 1000 to 10 microseconds. Since many commands take around 10 microseconds to complete, it is totally pointless to wait for 1000 microseconds before checking the status again. This patch is tested and reduced write time on ICH7 with SST25VF080B from over one hour to 6

[coreboot] [PATCH] flashrom: External flasher support

To prepare flashrom for Paraflasher (or other external flasher) support, each chip read/write access is either handled as memory mapped access or external flasher cycle. External flashers can set the flasher variable to their own ID/number during startup and handle accesses in the switch statement

Re: [coreboot] GSoC: Seabios USB Option ROM, small initial planning

On Wed, May 06, 2009 at 10:05:34AM -0400, Leandro Dorileo wrote: > For now, I have two major questions, #1: I`ve seen other projects like > FILO including libpayload with svn:external, once seabios is > maintained with git, how it should be done with seabios? how would we > manage the source code i

[coreboot] [PATCH] flashrom: Explicit read functions

Flashrom assumes that the flash chip contents are available via mmap if no read function is defined. This special case is handled in lots of places all over the code. Remove the special case and use the read_memmapped function. Not only does this allow us to fix a read bug in flashrom I recently u

[coreboot] flashrom: State of development

Hi, the following flashrom patches from me are pending: - SB600 SPI hang fix. Needs a test on SPI and a test on LPC. - VIA/ICH SPI workaround for standalone WRITE_ENABLE opcodes. This fix is URGENT. The bug already messed up flash contents of one machine. - SPI one-byte write support. This fix is

Re: [coreboot] GSoC: Seabios USB Option ROM, small initial planning

On 08.05.2009 03:02, Kevin O'Connor wrote: > As I understand the GSOC project, it is to build an option rom that > provides usb services to applications that use legacy bios functions. > I don't believe the project is specific to SeaBIOS. That is, the > project is to build an option rom that uses

Re: [coreboot] [PATCH] flashrom: External flasher support

On Fri, 08 May 2009 02:57:27 +0200, Carl-Daniel Hailfinger wrote: > To prepare flashrom for Paraflasher (or other external flasher) support, > each chip read/write access is either handled as memory mapped access or > external flasher cycle. > > External flashers can set the flasher variable t

Re: [coreboot] [PATCH] flashrom: External flasher support

On 08.05.2009 03:34, Joseph Smith wrote: > On Fri, 08 May 2009 02:57:27 +0200, Carl-Daniel Hailfinger wrote: > >> To prepare flashrom for Paraflasher (or other external flasher) support, >> each chip read/write access is either handled as memory mapped access or >> external flasher cycle. >> >>

Re: [coreboot] status of coreboot on Asus A8N-E

Hello Pierre, I also have this board and a NVIDIA 7600GT PCI-E card. I tested the latest revision a few days ago. Unfortunately there was still no output on the screen after a power-off. So it is no real alternative/replacement for the legacy bios of the board yet. But console output works.