Dear coreboot folks,
In commit a554b0c5b7 (soc/intel/common/block: Add Intel XHCI driver
support) [1] the directory
`src/soc/intel/common/block/include/intelblocks` is created.
Could somebody please help me, what *intelblocks* means here, and why
*intel* is twice in the path?
Thanks,
Paul
[
Hi,
I am working on an embedded board from Interface concept.
The chipset is intel QM67 (Cougar point) with a sandybridge Gen2 processor.
I think the board doesn’t have any spd because I get the error “Not a DDR3
SPD!” so I try to do the mrc raminit with the systemagent-r6.bin but I am
stuck on
actually Lenovo G505S has more freedom in some relations, if compared
to Chromebook R13 : for example, G505S does not require blobs for WiFi
and Bluetooth if you replace its' preinstalled Broadcom half size mini
PCI-e card with Atheros AR9462 (which has 2.4 GHz + 5 GHz + Bluetooth
and is top-of-the
On Mon, Jun 5, 2017 at 2:48 AM, Paul Menzel
wrote:
> Dear coreboot folks,
>
>
> In commit a554b0c5b7 (soc/intel/common/block: Add Intel XHCI driver
> support) [1] the directory
> `src/soc/intel/common/block/include/intelblocks` is created.
>
> Could somebody please help me, what *intelblocks* mean
Hi,
VT-d requires support from BIOS. Does coreboot support VT-d?
Regards
Himanshu Chauhan
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On Mon, Jun 5, 2017 at 9:00 AM Himanshu Chauhan
wrote:
> Hi,
>
> VT-d requires support from BIOS. Does coreboot support VT-d?
>
>
>
what support does it need?
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coreboot mailing list: coreboot@coreboot.org
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> On 05-Jun-2017, at 9:41 PM, ron minnich wrote:
>
>
>
> On Mon, Jun 5, 2017 at 9:00 AM Himanshu Chauhan
> wrote:
> Hi,
>
> VT-d requires support from BIOS. Does coreboot support VT-d?
>
>
>
> what support does it need?
BIOS adds DMAR and other entries in the ACPI table. I am not qui
You are asking for VT-d support. You are talking about Intel platforms ?
But for which specific platform you are asking for ? There are so many..
Am 05.06.2017 um 10:24 schrieb Himanshu Chauhan:
>
>> On 05-Jun-2017, at 9:41 PM, ron minnich wrote:
>>
>>
>>
>> On Mon, Jun 5, 2017 at 9:00 AM Himan
> what support does it need?
Intel Virtualization Technology for Directed I/O" (VT-d). VT-d is a
virtualized IOMMU, so by using HYP type 1 there should be a VT-d driver
supporting VT-d HW extension (?), as my best understanding is
The practical implications are Graphics and Network Connectivity i
> On 05-Jun-2017, at 10:02 PM, Zaolin wrote:
>
> You are asking for VT-d support. You are talking about Intel platforms ?
Yes. I am talking about intel platforms. All CPUs that have VT-d support need
support from motherboards as well. So any setup with VT-d enabled CPU and a
motherboards that
The reason I ask about what you need is that on chromebooks the main
coreboot support came down to 'don't disable anything'.
The DMAR requirements are not met on all platforms. But even after boot you
can insert DMAR tables into kernels.
So there is a key distinction between required support and
> On 05-Jun-2017, at 10:19 PM, ron minnich wrote:
>
> The reason I ask about what you need is that on chromebooks the main coreboot
> support came down to 'don't disable anything’.
I think its can’t just be disabled. Its just that kernel is not given any
knowledge about its existence. This i
On Mon, Jun 5, 2017 at 9:58 AM Himanshu Chauhan
wrote:
>
> I think its can’t just be disabled.
>
oh, really? Why do you think that? Have you looked at the relevant MSR and
what is the basis of your claim?
ron
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Hi,
On 05.06.2017 18:58, Himanshu Chauhan wrote:
>
>> On 05-Jun-2017, at 10:19 PM, ron minnich wrote:
>>
>> The reason I ask about what you need is that on chromebooks the main
>> coreboot support came down to 'don't disable anything’.
>
> I think its can’t just be disabled. Its just that kern
> On 05-Jun-2017, at 10:50 PM, ron minnich wrote:
>
>
>
> On Mon, Jun 5, 2017 at 9:58 AM Himanshu Chauhan
> wrote:
>
> I think its can’t just be disabled.
>
> oh, really? Why do you think that? Have you looked at the relevant MSR and
> what is the basis of your claim?
I was just guessing
On Mon, Jun 5, 2017 at 10:33 AM Himanshu Chauhan
wrote:
>
> > oh, really? Why do you think that? Have you looked at the relevant MSR
> and what is the basis of your claim?
>
> I was just guessing what it could be. :)
>
>
I think it's a ton easier if you study on some simple hypervisors written
fo
>> The reason 'intelblocks' is in the include path is because the include
>> headers are namespaced. e.g. #include .
My +2 to Aaron's comment, that’s the only reason to create "intelblocks".
Thanks,
Subrata
-Original Message-
From: Aaron Durbin [mailto:adur...@google.com]
Sent: Monday
> If you are lucky, you only need to add 20~30 lines to your chipset's code.
Could you, please, show us an explicit example (of these 20 to 30 lines of
code)?!
Zoran
On Mon, Jun 5, 2017 at 7:34 PM, Nico Huber wrote:
> Hi,
>
> On 05.06.2017 18:58, Himanshu Chauhan wrote:
> >
> >> On 05-Jun-2017
On 05.06.2017 19:47, Zoran Stojsavljevic wrote:
>> If you are lucky, you only need to add 20~30 lines to your chipset's code.
>
> Could you, please, show us an explicit example (of these 20 to 30 lines of
> code)?!
`src/northbridge/intel/sandybridge/iommu.c` and acpi_fill_dmar() in
`src/northbrid
Hi,
Le dimanche 04 juin 2017 à 22:49 +, qma ster a écrit :
> Good day! While building the coreboot's toolchain by using GCC 7.1.1
> version, I am getting the following error:
[…]
> Found this solution here -
> https://patchwork.openembedded.org/patch/138884/ . Would be great if
> you could s
Hi Mike,
I use Cutecom.
Why ?
Martin
De : Mike Banon
Envoyé : lundi 5 juin 2017 17:03
À : Martin A
Objet : Re: [coreboot] Asus M2N-E
Hi Martin! Please tell: what tools are you using to receive this coreboot
booting log?
On Wed, May 24, 2017 at 12:14 AM, Ma
Hey,
Le lundi 05 juin 2017 à 18:20 +0300, Mike Banon a écrit :
> actually Lenovo G505S has more freedom in some relations, if compared
> to Chromebook R13 : for example, G505S does not require blobs for WiFi
> and Bluetooth if you replace its' preinstalled Broadcom half size mini
> PCI-e card with
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