Re: [coreboot] [RFH] Status of the Lenovo X201

Hi On Wed, Apr 18, 2018 at 12:42 PM, Nicola Corna wrote: > Hi Paul, > > I can't make my X201 boot with the most recent commit: the screen turns on > and it shows a blinking > cursor, but that's all. > Attached you can find the debug log: as you can see it has detected a stack

Re: [coreboot] AMD Family 15h and 16h: ASSERTION ERROR

Mike Banon wrote: > APIC 00: ** Enter AmdInitLate [00020004] > [1] ASSERTION ERROR: file > 'src/vendorcode/amd/agesa/f15tn/Proc/Common/CommonReturns.c', line 187 > [2] ASSERTION ERROR: file > 'src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuGeneralServices.c', line > 776 > ^^^ these two lines repeat 9

Re: [coreboot] [RFH] Status of the Lenovo X201

Hi Paul, I can't make my X201 boot with the most recent commit: the screen turns on and it shows a blinking cursor, but that's all. Attached you can find the debug log: as you can see it has detected a stack smashing and it froze in a random point. I don't have the build config right now, but

[coreboot] Problem about GPIO

I try to porting coreboot to msi's Motherboard(H110 chipset). I read GPIO config from PCR config space under linux. But the value I got was very strange. eg: //DW0 and DW1 cannot be 0x according to the data sheet PIN:GPP_C6 DW1,DW0:, FUNC:(null) PULL:NATIVE

Re: [coreboot] How is our SPI API supposed to work?

On Wed, Apr 18, 2018 at 8:46 PM, Julius Werner wrote: > I was trying to understand how to best implement the coreboot SPI API for a > new SoC, and as I was reading into it I got increasingly confused. This has > changed a bit last year (with the addition of struct

[coreboot] How is our SPI API supposed to work?

I was trying to understand how to best implement the coreboot SPI API for a new SoC, and as I was reading into it I got increasingly confused. This has changed a bit last year (with the addition of struct spi_ctrlr), and I don't think it was fully consistent before that across all implementations