Re: [coreboot] Modifying Coreboot to support a new processor

On Tue, Aug 9, 2011 at 5:40 AM, Dsouza, Malcolm < malcolm.dso...@igatepatni.com> wrote: > ** > >1. I am trying to work out an overview of the changes required for a >start; a bird’s eye view of what the changes could turn out to be. What is >the best approach for this? > > As Stefan an

Re: [coreboot] Dose coreboot support TPM(trusted platform module) ?

On Tue, Aug 30, 2011 at 7:44 PM, Cui Lei wrote: > Hi all, I know TPM was supported by FreeBIOS and the FreeBIOS was turned > into linuxBIOS , now linuxBIOS is called coreboot. But it seems that > coreboot now does not provide the TPM support, may be I lost in the source > code.So,dose corebootV4

Re: [coreboot] barbarians at the gates

Unfortunately, as a consumer there isn't a whole lot that can be done. It's sort of like trying to buy a PC with Linux instead of Windows -- Due to volume, the cheapest and most readily-available hardware is ironically likely to have the Microsoft tax built into the pricetag. Similarly, nearly all

Re: [coreboot] barbarians at the gates

On Sat, Sep 10, 2011 at 1:25 PM, Niklas Cholmkvist wrote: > On the main page http://www.coreboot.org/ which redirects to > http://www.coreboot.org/Welcome_to_coreboot there's lots of information > but I see no "get coreboot" anywhere. Maybe coreboot is still in its > infant stages to go so boldly

Re: [coreboot] ARM SoC ID

Plumbers Conference talk: http://linuxplumbersconf.org/ocw/proposals/47 2010 Embedded Linux Conference talk: http://elinux.org/images/b/b6/ARM_Device_Tree_Status_Report.pdf -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org htt

Re: [coreboot] [LinuxBIOS] [patch] MSI MS-7135 (this time with attachment)

Whoa, I don't know how I let this one slip by... Did you manage to get SATA working, by chance? That was a show stopper for me, but I haven't been able to diagnose it. 2007/12/6 <[EMAIL PROTECTED]>: > Initial support for MSI MS-7135 (K8N Neo3) mainboard. > > Signed-off-by: Jonathan A. Kollasch <[

Re: [coreboot] [LinuxBIOS] [patch] MSI MS-7135 (this time with attachment)

10:36:26AM -0600, [EMAIL PROTECTED] wrote: > > On Fri, Feb 01, 2008 at 12:06:15AM -0800, David Hendricks wrote: > > > Whoa, I don't know how I let this one slip by... Did you manage to get > SATA > > > working, by chance? That was a show stopper for me, but I haven'

Re: [coreboot] [LinuxBIOS] [patch] MSI MS-7135 (this time with attachment)

That's very possible -- My pirq table didn't look nearly as nice as yours! On Feb 2, 2008 11:45 AM, <[EMAIL PROTECTED]> wrote: > On Fri, Feb 01, 2008 at 10:29:17PM -0800, David Hendricks wrote: > > Have you benchmarked SATA performance? I'm curious if you can run a

[coreboot] Coreboot Tech Talk @ Google, October 30 2008

Hey everyone, Just thought I'd post a link to the tech talk Stefan, Peter and Ron gave at Google a couple days ago: http://www.youtube.com/watch?v=X72LgcMpM9k . The format goes: 1) Ron Minnich, project founder: What is Coreboot, motivation, and principles of operation. 2) Peter Stuge, long-time co

Re: [coreboot] LPCflasher Wiki Page

So far so good. I'm looking forward to reading up more on flashrom support, but I suspect that it will come more or less automatically once all the hardware is hooked up and the machine is booting linux. On Wed, Nov 19, 2008 at 2:56 PM, Joseph Smith <[EMAIL PROTECTED]> wrote: > > Well I almost ha

Re: [coreboot] Big picture of recent ARM patches?

ge where they belong. It would've been the same had we developed everything internally and then sent a sanitized patchset upstream ex post facto, only without the instructive (perhaps cautionary) early debugging parts. Thankfully this is the coreboot mailing list, where ugly early debugging

Re: [coreboot] Guide lines: Prepend commit summary with component (was: New patch to review for coreboot: 0b41858 Clean up the mmu setup a bit)

cular part of the codebase, then specify the directories/files you wish to look at when running git log. Actually, I think it would look kind of ugly to do "git log src/arch/x86" and see every commit cluttered with some cookie-cutter prefix. /my $0.02. -- David Hendricks (dhendrix) Sys

Re: [coreboot] gerrit: patch iterations in email [was: differences between patchset iterations]

s or if the commit message was changed? - Can we make Jenkins send less verbose messages to the IRC channel so that it sends out one (instead of two) brief messages indicating a patch's success or failure? Any other thoughts? -- David Hendricks (dhendrix) Systems Software Engineer, Google

Re: [coreboot] Guide lines: Prepend commit summary with component

On Thu, Jan 31, 2013 at 2:24 PM, Paul Menzel < paulepan...@users.sourceforge.net> wrote: > Am Mittwoch, den 30.01.2013, 21:47 +0100 schrieb Peter Stuge: > > David Hendricks wrote: > > > If you wish to focus only on a particular part of the codebase > > > > It

Re: [coreboot] Different Google copyright notices: »The Chromium OS Authors. ?«

on > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Patch set updated for coreboot: b115b35 armv7: Clean up: remove deprecated SPL.

On Wed, Feb 6, 2013 at 3:01 PM, Peter Stuge wrote: > David Hendricks wrote: > > David Hendricks (dhend...@chromium.org) just uploaded a new patch set > to gerrit, which you can find at http://review.coreboot.org/2297 > > > > -gerrit > > > > commit b115

Re: [coreboot] New patch to review for coreboot: 0ae65d8 Add support for "Butterfly" Chromebook

s and then iterating makes a great deal of sense. /my $0.02 -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Unifying AMD SB700/SB800/SB900 code base

arately from the SB800 to utilize chipset-specific debug features, and then sanitized the code prior to releasing it. You're right to point out the problems with this model, but in general I suspect it's best to simply accept the ugly parts rather than diverge from whatever AMD uses internally.

Re: [coreboot] Could some one please give me parameters for QEMU for running Coreboot with Linux payload

the display, such as VGABIOS output or the GUI for your OS. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [RFC] Abbreviations in commit messages and code

On Tue, Mar 19, 2013 at 3:41 PM, Paul Menzel < paulepan...@users.sourceforge.net> wrote: > Dear coreboot folks, > > > following up on Ron’s comment to Gerrit item(?) 2695 [1] > > We can't break out each and every vendor TLA (Three Letter > Acronym) or we'll be here for years. I und

Re: [coreboot] Coreboot support for AMD Parmer?

ms the board support is present: http://review.coreboot.org/gitweb?p=coreboot.git;a=tree;f=src/mainboard/amd/parmer;h=468c7303dd73cc6f211997024ad7849d6a7fc8fa;hb=HEAD -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot

Re: [coreboot] coreboot: make crossgcc - Failed to download acpica-unix-20121114.tar.gz.

My first intuition is to "make clean" and "rm -f .xcompile", then attempt to "make" again. You should not need to make crossgcc manually. On Wed, Apr 10, 2013 at 10:48 PM, Pradish M P, ERS, HCLTech < pradis...@hcl.com> wrote: > Dear coreboot folks > > i downloaded the latest source code form cor

Re: [coreboot] Boot flow flexibility changes

about the reboot case? -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] On loongson CPU or MIPS ARCH

mon}, and the first ARM motherboard target is in src/mainboard/google/snow. The ARM stuff is still under active development, and we are still making changes to code that was imported from another codebase (u-boot). But overall it works and we are able to load a payload and boot Linux. -- David Hen

Re: [coreboot] On loongson CPU or MIPS ARCH

o agree. The real question is whether it might be useful for future MIPS-based laptops. I suspect coreboot is overkill for current MIPS-based products. However, we may see more complex systems where the Loongson is only a small part of the system as a whole, and where you may need flexibility to customize

Re: [coreboot] On loongson CPU or MIPS ARCH

onsibility of the payload. The "payload" may be a Linux kernel if you can fit it on the ROM. As Vladimir pointed out, this is only 512KB. If you have a very small kernel then you may simply set it as the payload. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. --

Re: [coreboot] [flashrom] Looking for dediprog users...

h...@flashrom.org > http://www.flashrom.org/mailman/listinfo/flashrom -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Best Supported Laptop

On Mon, Jun 3, 2013 at 1:57 PM, Alex G. wrote: > > On 06/03/2013 03:10 PM, Oliver Schinagl wrote: > > On 06/03/13 16:03, Denis 'GNUtoo' Carikli wrote: > >> Hi, > >> > >> On Sun, 2 Jun 2013 20:54:04 -0500 > >> slhac tivist wrote: > >> > >>> >Which supported laptop is the most free? > >> The Lenovo

Re: [coreboot] Chromebooks overview

l detect and skip over the management engine region on Intel platforms and comes installed on all Chromebooks. Is there information about where the spi chips can be found? > Hmmm, I don't know off-hand :-/ If not, we can augment existing pics on the site you found or get some new on

Re: [coreboot] Overview of latest Google patch push?

of a way to order the patches regarding their > dependencies in Gerrit? > That would be nice! I usually just click on a patch and follow its "Depends On" link... -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Patch management

lt;http://ostatic.com/blog/open-source-code-review-tools>. Review Board <http://www.review-board.org/> from the folks at VMWare looks really good, and Rietveld <http://code.google.com/p/rietveld/>, which is a relatively new open-source fork of Google's Mondrian<http://www.youtub

[coreboot] MSI 7135 verbose lspci output

Attached is an lspci dump for the MSI 7135 (K8N Neo3) board. jakllsch did a v2 port for this board last year. Flashrom works, but only if you do -m msi:k8n-neo3 for erase and write operations. Uwe suggested posting the lspci contents in case someone has a few spare cycles to try and implement auto-

Re: [coreboot] Which file should I burn?

On Tue, Jun 23, 2009 at 7:06 PM, Rick Ant wrote: > I got this message : > = > boot: hda:/boot/vmlinuz root=/dev/hda initrd=/boot/initrd console=ttyS0 > hda: LBA48 524MB: QEMU HARDDISK > Mounted ext2fs > Found Linux version 2.6.16.5 (r...@e-smith) #2 PREEMPT Sat Sep 22 00:14:46 >

Re: [coreboot] Which file should I burn?

> Am I right in this point ? > > Thanks > > --- On *Tue, 6/23/09, David Hendricks * wrote: > > > From: David Hendricks > Subject: Re: [coreboot] Which file should I burn? > To: "Rick Ant" > Cc: coreboot@coreboot.org > Date: Tuesday, June 23, 2009, 7

Re: [coreboot] Is PI-AM2RS780G supported ?

On Tue, Jun 23, 2009 at 2:28 AM, Alois Schlögl wrote: > The reason for asking is the bug as described here: > http://bugzilla.kernel.org/show_bug.cgi?id=13573 > > The bug is affecting my research at the university. > It was suggested that a Bios-update could solve the problem. IIRC you can disa

Re: [coreboot] Is PI-AM2RS780G supported ?

On Wed, Jun 24, 2009 at 12:30 AM, David Hendricks wrote: > On Tue, Jun 23, 2009 at 2:28 AM, Alois Schlögl > wrote: > >> The reason for asking is the bug as described here: >> http://bugzilla.kernel.org/show_bug.cgi?id=13573 >> >> The bug is affecting my rese

Re: [coreboot] Development IDE

r > > > any other IDE. > > > > I use vim and grep. There is no IDE for coreboot development. > Interesting, but do you use any extensions for vim? ctags are infinitely useful -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. Fellow vim us

Re: [coreboot] My last note today on EFI :-)

>From http://www.intel.com/intelpress/sum_eshl.htm : "*The UEFI Shell requires no platform-level customization. It requires no drivers beyond those included in the shipping system. This means as the UEFI Shell is used it becomes less and less likely to be the culprit of bugs introduced as a part of

Re: [coreboot] flashrom command line syntax change

tered that does not have a flag assigned to it, e.g. -p or -c or whatever, is the filename to operate on. That behavior is nice when the program does not require arguments to behave in a sane manner, e.g. *mplayer foo.ogg*. This usage model doesn't make sense for Flashrom, so it makes sense to tr

Re: [coreboot] [PATCH] support for nuvoton WPCE775x/NPCE781x devices (update copyright)

Thanks for sending the patch out, Amit! Since I wrote this particular patch, I'll go ahead and do the sign-off on it: Signed-off by: David Hendricks (dhend...@google.com) On Wed, Jul 21, 2010 at 12:00 AM, wrote: > This is the same patch as before (2010/07/14) just with an updated >

Re: [coreboot] [PATCH] support for nuvoton WPCE775x/NPCE781x devices (update copyright)

Carl-Daniel pointed out some whitespace issues with the patch. I ran it thru the "indent -kr -i8" filter and fixed up the register table entries, so the attached patch should address concerns about whitespace. On Thu, Jul 22, 2010 at 1:30 PM, David Hendricks wrote: > Thanks for send

[coreboot] [PATCH][superiotool] Quit probe_idregs_* early if chip_found is set

s quit after a chip is found. Signed-off by: David Hendricks (dhend...@google.com) -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. Index: superiotool-head/ite.c === --- superiotool-head.orig/ite.c +++ superiotoo

Re: [coreboot] Top Makefile

ake and the Linux kernel build system then this is not a good place to start. I do not mean to sound rude, but the Linux and Coreboot build systems are much more complicated than a make or gcc commands you may be familiar with from small projects. -- David Hendricks (dhendrix) Systems Software Engi

Re: [coreboot] dongle.py!!

side the subdirectories are > > called? Please mention the line which does this. > > There's no recursive make. > if only ;-) http://miller.emu.id.au/pmiller/books/rmch/ <http://miller.emu.id.au/pmiller/books/rmch/> -- David Hendricks (dhendrix) Systems Software Engi

Re: [coreboot] [PATCH][superiotool] ITE IT8500 EC support

t; > > superiotool r5679 > > [..] > > Signed-off by: Donald Huang (donald.hu...@ite.com.tw) > > Signed-off by: Yung-chieh Lo (yj...@google.com) > > Signed-off by: David Hendricks (dhend...@google.com) > > > Dear Donald, > > thank you very much for you work. However

Re: [coreboot] BBC EFI story

On Sat, Oct 2, 2010 at 3:19 AM, ali hagigat wrote: > >I understand that this can be frustrating, but it's something that the > >coreboot project has no control over. > >NDA stands for Non-Disclosure Agreement, which means that > > At least you could add some lines about NDA story and incomplete d

Re: [coreboot] coreboot certified hardware

On Mon, Oct 4, 2010 at 12:23 PM, Peter Stuge wrote: > phorsyon wrote: > > a minimal and a consumer version of a certificate > > As was mentioned, the more certifications there are, the less easy it > is for the market to make use of them. > > I don't think we can afford to try to market two diffe

[coreboot] [superiotool] patch for fintek f71889fg

Signed-off-by: David Hendricks -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. Index: fintek.c === --- fintek.c (revision 5953) +++ fintek.c (working copy) @@ -122,6 +122,50 @@ {0x30,0xf0,0xf1

Re: [coreboot] [superiotool] patch for fintek f71889fg

On Tue, Nov 2, 2010 at 12:45 PM, Uwe Hermann wrote: > Hi, > > On Mon, Nov 01, 2010 at 01:02:53PM -0700, David Hendricks wrote: > > The patch (attached) was tested by a user on IRC who had the F71889FG. I > > wrote it using documentation from Fintek's websit

Re: [coreboot] BIOS RAM in AMD SB7XX southbridges ?

7, 2009 at 6:06 AM, Darmawan Salihun < darmawan.sali...@gmail.com> wrote: > Is it to buffer the BIOS contents from SPI flash chip prior to > execution of the very first instruction? > I recall that it's impossible to execute code directly in an SPI chip. > That's correct,

Re: [coreboot] BIOS RAM in AMD SB7XX southbridges ?

On Tue, Oct 27, 2009 at 2:04 PM, Gregg Levine wrote: > On Tue, Oct 27, 2009 at 4:51 PM, David Hendricks > wrote: > > On Tue, Oct 27, 2009 at 6:06 AM, Darmawan Salihun > > wrote: > >> > >> What is the BIOS RAM in AMD SB7XX used for? > > > > Looks l

Re: [coreboot] Licensing question

using BSD-licensed AGESA code that I am not seeing here? -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] superiotool sometimes skips further SuperIO chips in the system - suggested remedy included

gt; annotations of the register dump etc - but I admit that's too much > work to be worth the bother, certainly for me at the moment :-) > > Keep up the excellent work that you're doing... > > Frank Rysanek > > > -- > coreboot mailing list: coreboot@coreboot.org > http://www.coreboot.org/mailman/listinfo/coreboot > -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Invite: Silicon Valley Coreboot Hackathon

ready, visitor badges printed, and technically prepared for the topics of interest. We'll also send confirmation with detailed instructions on how to find the building / conference room to those who register. Registration form: https://spreadsheets.google.com/viewform?formkey=dGRab2s1VH

Re: [coreboot] Invite: Silicon Valley Coreboot Hackathon

[ cc'ing flashrom mailing ] On Mon, Jan 17, 2011 at 5:39 PM, David Hendricks wrote: > Stefan mentioned that he knows several people who he has worked with in the > area, and we're thinking it would be fun to get everyone together for a day > of hacking on Coreboot and relat

Re: [coreboot] Invite: Silicon Valley Coreboot Hackathon

ation is not required, but is encouraged for planning purposes. The super-easy, <1min form is available @ https://spreadsheets.google.com/viewform?formkey=dGRab2s1VHRKNzRDX19pTVVrTjhVTkE6MQ P.S. Stefan has 50 8Mbit FWH flash chips to give away! On Mon, Jan 17, 2011 at 5:46 PM, David Hendricks wrot

Re: [coreboot] SVN service down?

wait. It > would seem to be hanging. Network monitors would only indicate that my > SSH shell is the only thing running on the host. > fwiw, svn update works fine for me right now. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@

[coreboot] [superiotool] patch for smsc mec1308

just disable it for now. Signed-off-by: David Hendricks -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. Index: smsc.c === --- smsc.c (revision 6181) +++ smsc.c (working copy) @@ -358,6 +

Re: [coreboot] [superiotool] patch for smsc mec1308

On Wed, Feb 16, 2011 at 5:09 PM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2...@gmx.net> wrote: > Auf 17.02.2011 01:11, David Hendricks schrieb: > > Attached is a patch to add support for the SMSC MEC1308 embedded > controller. > > > > Unfortunately, the devic

Re: [coreboot] [superiotool] patch for smsc mec1308

> the code. > The ITE code uses a 16-bit identifier for this info... I wish the SMSC code could do the same :-/ -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] Coreboot meeting @ Google, Sunday Mar. 13

e room (1st floor, adjacent to lobby) Contact #: 408-512-3445 (last meeting's participants bcc'd since this is pretty short notice) -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] coreboot support for memory mapped UARTs

out, you can order mini-PCIe to serial converters with the Oxford chip such as the Startech MPEX2S952 for about $60USD. Here's a link: http://www.amazon.com/2-PORT-Mini-Pci-Express-Card/dp/B003OCRW1Q/ref=sr_1_fkmr3_3?ie=UTF8&qid=1303343174&sr=8-3-fkmr3 -- David Hendricks (dhendrix) Sy

Re: [coreboot] [RFC]Using gerrit for patch management (and jenkins for QA)

up to a certain point, but Coreboot and Flashrom both have enough developers contributing that it's worth moving to a more advanced SCM. Especially since a lot of changes can linger for days or weeks since hardware scarcity can often limit the ability of reviewers and testers. -- David Hendr

Re: [coreboot] [ANN] New code repository and development workflow

ture, and we will > certainly tweak the ad-hoc messages and formatting some more. > I suggest squelching the "Patch set updated" messages on the mailing list. Reviewers will get the notifications anyway, so for those who are not reviewing a patch those notifications are excessive. -

Re: [coreboot] gerrit: differences between patchset iterations (was: New patch to review: 49493f5 T60: add volume CMOS setting)

;diff all" to open each file up in a new browser tab) 2. Click the arrow next to "Patch history" in the upper left corner 3. Choose two patch sets to diff. 4. Hit the "update" button. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] gerrit: patch iterations in email [was: differences between patchset iterations]

u add yourself as a reviewer, you should get e-mails for comments and iterations. (Note: I haven't verified this with Coreboot's gerrit setup) -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Is this board supported?

this a chip called "UCC" by AsRock? > EC is sort of a SuperIO chip, but with more functions commonly used in laptops. I think you have a normal SuperIO chip. "UCC" seems to be a marketing name from AsRock that means "Unlock CPU Core". -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] gerrit: patch iterations in email [was: differences between patchset iterations]

On Thu, Jun 9, 2011 at 9:39 AM, Uwe Hermann wrote: > On Wed, Jun 08, 2011 at 07:24:39PM -0700, David Hendricks wrote: > > On Wed, Jun 8, 2011 at 5:16 PM, Peter Stuge wrote: > > > > > Paul Menzel wrote: > > > > > http://review.coreboot.org/12 > >

Re: [coreboot] gerrit: patch iterations in email [was: differences between patchset iterations]

the list were re-enabled, three updates to "i945 GMA: restore tft brightness from cmos" spawned three different threads within the span of 10 minutes. It has the same effect on my gmail inbox as it does on the mailing list archive. -- David Hendricks (dhendrix) Systems Software Engin

Re: [coreboot] ASRock e350m1 problems

good way to confirm that the SPD addresses are correct in Coreboot, and rule out the possibility that ASRock changed SPD addressing between board revisions... -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Flashing via TPM

On Sun, Jul 17, 2011 at 12:38 PM, Andrew Bolster wrote: > Tom, > Thank you for your response. I'll investigate the SPI angle. Is there any > structure for collecting information like this within the coreboot community > about specific boards for those of us who are more soft than hardware? > The

Re: [coreboot] Generic AMD E350 Support

load at http://ge.tt/ or another favorite > > image hoster. > > I'll hopefully upload them tonight (10 hours or so) > BTW -- try to peak under the southbridge heatsink if it's not too much of a hassle. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc. -- co

[coreboot] Draft patches in Gerrit

ltas: 100% (1/1) remote: Processing changes: new: 1, refs: 1, done remote: remote: New Changes: remote: http://review.coreboot.org/1671 [DRAFT] remote: To ssh://dhend...@review.coreboot.org:29418/coreboot * [new branch] HEAD -> refs/drafts/master/test -- David Hendricks (dhendrix) Syste

Re: [coreboot] Draft patches in Gerrit

On Fri, Nov 2, 2012 at 7:42 PM, Peter Stuge wrote: > David Hendricks wrote: > > 2012-11-02 16:03:59.026509 Running: git log HEAD^1..HEAD > > Found topic 'test' from parsing changes. > > Is it known how the finding is done? > >From what I can tell, one of

Re: [coreboot] how to use TianoCore as a coreboot payload

Hello Siyuan, You might find this webpage useful: http://www.phisch.org/website/efiboot/ Have you built Coreboot for your target mainboard or emulator? Coreboot can load any ELF payload (Payload -> Add a payload -> An ELF executable payload and provide the path to your payload). I have not attemp

Re: [coreboot] how to use TianoCore as a coreboot payload

On Wed, Dec 5, 2012 at 9:07 PM, WANG Siyuan wrote: > On Wed, Dec 5, 2012 at 6:12 AM, David Hendricks wrote: > >> Hello Siyuan, >> You might find this webpage useful: >> http://www.phisch.org/website/efiboot/ >> > No code are provided. > Perhaps you can conta

Re: [coreboot] Lemote Yeeloong

On Sun, Mar 15, 2009 at 11:29 AM, Jason Self wrote: > There is a fully free software laptop with free software BIOS, firmware, > driver, kernel, software, operating system. It is called Lemote > Yeeloong. You can see it here: > > http://www.lemote.com/english/yeeloong.html > > More pics here

Re: [coreboot] prettyprint for hardware registers

On Sat, Mar 21, 2009 at 8:58 PM, Carl-Daniel Hailfinger < c-d.hailfinger.devel.2...@gmx.net> wrote: > Could this be something useful for us, especially considering it looks > like a combination of msrtool, inteltool etc? > I'd like to make sure we don't reinvent the wheel here. > > Quoting from th

Re: [coreboot] J7F2: larger bios chip?

On Tue, Apr 7, 2009 at 12:04 PM, maarten van es wrote: > Hello everyone, > > I have just started to try out coreboot, and so far it works great in > qemu. My real target however is the jetway J7F2. I would like a larger > bios chip than the standard 512 kB on this board. Does anyone have > some su

Re: [coreboot] Just FYI: if you are under 18, you are out of GSOC; make sure your birthday is in there correctly!

On Sat, Apr 11, 2009 at 3:14 PM, ron minnich wrote: > We just got the notice from Google. There are a lot of applicants > under 18 --> automatic disqualification. Student applicants, please > verify your personal information. FWIW, if you happen to know some promising high-school hackers, you m

[coreboot] Corruption issue in build_lb_mem()?

I am having some difficulty booting a FILO (r95) payload using coreboot-v2 (r4291). My target is a via vb7001g, but I'm using the epia-cn target since the boards are practically identical afaict. The only hardware change I've made is using a 2MB flash chip. I was able to boot some simple payloads u

Re: [coreboot] Coreboot wiki: what license is the content under?

This would be a good topic to bring up in the next community chat. On Tue, Mar 21, 2017 at 1:21 PM, Sam Kuper wrote: > On 21/03/2017, Martin Roth wrote: >> Is there a reason we shouldn't switch to CC BY 4.0? > > Arguably, yes: doing so would permit the use of Coreboot wiki material > in propriet

Re: [coreboot] Coreboot wiki: what license is the content under?

On Fri, Mar 31, 2017 at 10:20 AM, Sam Kuper wrote: > Also, to further address Patrick's point above about marketing > material: it is important that the provenance of information about > Coreboot can be established. This is a reputational matter. That means > it is important that people should not

Re: [coreboot] Coreboot wiki: what license is the content under?

On Sun, Apr 2, 2017 at 11:05 AM, Sam Kuper wrote: > So, Creative Commons explicitly acknowledges that an adaptation of a > CC BY-licensed work can indeed be licensed under CC0 (or, at least, > that the adapter's contribution to the adaptation can be; which I note > would be the entire adaptation,

Re: [coreboot] ThinkPad X230 alternative flash chips?

It looks like the X230 already has a large flash chip (BOARD_ROMSIZE_12288?). How big were you thinking? The main issue would be that chips bigger than 16MB use 4-byte addresses and the SPI controller in Ivy Bridge probably only supports 3-byte addresses. From:

Re: [coreboot] New on blogs.coreboot.org: Announcing coreboot 4.6

On Tue, May 9, 2017 at 2:14 PM, taii...@gmx.com wrote: > To further clean things up, starting with the 4.8 release, any platform >> that >> does not have a successful boot logged in the board_status repo in the >> previous >> year (that is, within the previous two releases) will be removed from t

Re: [coreboot] Coreboot Stickers

On Wed, May 24, 2017 at 10:45 AM, Rene Shuster wrote: > ​Hi there, > Where can I get Coreboot stickers? > What are your thoughts working together w/ UnixStickers.com, so that > Coreboot would receive part of the sales as monthly donations ( > https://www.unixstickers.com/donations ). > Coreboot

Re: [coreboot] 2017 North American coreboot Conference

On Thu, May 25, 2017 at 7:43 PM, Martin Roth wrote: > We're working with the SFC on billing. We'll be sending out emails to > all registered attendees next week with billing information. I received my invoice via e-mail earlier today, others should check their e-mail and contact Martin if they

[coreboot] Bay Trail uCode headers out of date

Hello, I have a Minnowboard Turbot (dual core E3826) and was only able to get it up and running after finding microcode M0130679901 from patch 30679 ( https://www.intel.com/content/www/us/en/embedded/products/bay-trail/software-and-drivers.html ). I was wondering if someone from Intel would mind a

Re: [coreboot] Fwd: [FWD: Request for Chromebook Authentication Module Development]

Hi Victor, IMO this is really more of a feature for the Out Of Box Experience (OOBE) rather than coreboot or seabios. If your organization uses the ChromeOS Management Console then you should already be able to assign specific assets to users ( https://www.google.com/intl/en/chrome/business/devices

Re: [coreboot] Fwd: [FWD: Request for Chromebook Authentication Module Development]

On Tue, Aug 1, 2017 at 10:54 PM, David Hendricks wrote: > Hi Victor, > IMO this is really more of a feature for the Out Of Box Experience (OOBE) > rather than coreboot or seabios. > Just to clarify, OOBE refers to a specific set of routines - I believe within the login manage

Re: [coreboot] How is depreciating 95% of coreboot boards worth it for such minor improvements?

On Wed, Aug 23, 2017 at 3:10 PM, Jonathan Neuschäfer wrote: > On Wed, Aug 23, 2017 at 09:44:30PM +, ron minnich wrote: > > On Wed, Aug 23, 2017 at 2:31 PM taii...@gmx.com wrote: > > > > > Ah I see thanks for explaining. > > > > > > I had read all the AGESA boards were going to be removed, be

Re: [coreboot] How is depreciating 95% of coreboot boards worth it for such minor improvements?

On Thu, Aug 24, 2017 at 11:12 AM, Renze Nicolai wrote: > Another thing: I don't understand the workflow for putting my > boardstatus on the wiki yet. Could someone explain to me how I can > publish on the wiki that my board works with a certain version of > Coreboot? Also: how can I add a wiki pa

Re: [coreboot] Please clarify wiki on git vs releases

On Sat, Sep 9, 2017 at 4:43 PM, Ian Kelling wrote: > The release readme says to read http://www.coreboot.org/Build_HOWTO, > which says to use the latest git sources. The mainpage of the wiki is a > bit ambiguous, but also leads to that same link under getting > started. So, you've given the impre

Re: [coreboot] How is depreciating 95% of coreboot boards worth it for such minor improvements?

On Fri, Aug 25, 2017 at 4:41 PM, David Hendricks wrote: > On Thu, Aug 24, 2017 at 11:12 AM, Renze Nicolai wrote: > >> Another thing: I don't understand the workflow for putting my >> boardstatus on the wiki yet. Could someone explain to me how I can >> publish on

Re: [coreboot] How is depreciating 95% of coreboot boards worth it for such minor improvements?

On Sun, Sep 10, 2017 at 1:42 PM, Piotr Król wrote: > 2. Is cbmem required ? (Geode LX do not have support for cpufreq - > cbmem complains) > Yes, though hopefully we can patch cbmem to deal with this. I am only guessing but it seems it will fail in arch_tick_frequency()? Is there a way of differ

Re: [coreboot] ast2400 / ast2500

On Fri, Oct 20, 2017 at 7:46 AM, Tirumalesh wrote: > Hi, > > Could some one please let me know, if corebott supports either > AST2400/AST2500 (ASpeed BMC) > If yes, how to test it with QEMU? > What kind of support are you looking for? There is some support for interfacing with it in coreboot run

Re: [coreboot] BIOS log in coreboot

On Wed, Nov 22, 2017 at 10:09 AM, ingegneriafore...@alice.it < ingegneriafore...@alice.it> wrote: > Hello Guys ! > > I apologize with you if my question seems silly: > > can you tell me if Coreboot stores a log of the POST phase in its EPROM > memory ? > > If so, is it possible to retrive the log

Re: [coreboot] Depthcharge License

To be fair, it appears that many source files refer to a non-existent LICENSE file. Someone on the CrOS team should probably just add the LICENSE file for depthcharge and/or contact mal@ to see how the license info is being collected these days (e.g. for chrome://os-credits

Re: [coreboot] BDX-DE PCI init fail

Hi Hilbert, Have you had any luck? I have a board with a similar problem. Commenting out the entry for device 1f.3 in devicetree.cb seemed to help (I copied src/mainboard/intel/camelbackmountain_fsp for my project). On Wed, Dec 27, 2017 at 2:17 AM, Hilbert Tu(杜睿哲_Pegatron) < hilbert...@pegatroncor

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