Re: [coreboot] Regarding Intel (and Librem)

motherboard there was no MXIC chip, but cFeon QH32-104HIP bios chip instead. As you see, lots of things could be added to Coreboot G505s wiki. I've asked a coreboot wiki account so that I could improve g505s page: add new information, and clarify older as well On 17 April 2015 at 11:45, Vladimir quickcrackt

[coreboot] Regarding Intel (and Librem)

that - thanks to latest contributors - coreboot is now supporting the ASROCK IMB-A180 and Biostar AM1ML which are based on AMD AM1 platform (architecture family 16h, Puma/Jaguar SoCs are compatible) Maybe some of these products have a potential to be RYF'ed, will see... Best regards, Vladimir Shipovalov

Re: [coreboot] Lenovo G505S and Coreboot LTS Candidates list

within the EU with (online) shops still selling the A10 variant and having some actual stock? --emi On Mon, Apr 6, 2015 at 6:45 PM, Vladimir quickcrackt...@gmail.com wrote: Yes, in addition to A10-5750M based G505S there are also A8 and A6 ones. But there are some possible problems regarding

[coreboot] Lenovo G505S and Coreboot LTS Candidates list

graphics, slightly more powerful than 2) ) Are these modifications all supported by Coreboot? And would be there any additional difficulties regarding modifications with dual graphics? Your answers and opinions will be very welcome Best regards, Vladimir Shipovalov -- coreboot mailing list

Re: [coreboot] Lenovo G505S and Coreboot LTS Candidates list

in the wiki. --emi On Mon, Apr 6, 2015 at 1:45 PM, Vladimir quickcrackt...@gmail.com wrote: Dear coreboot developers, Francis Rowe (main Libreboot developer) has hinted an idea about adding Lenovo G505S to Coreboot LTS Candidates list of laptops, which is hosted at MrNuke's User talk

Re: [coreboot] Trouble with Coreboot on Lenovo G505s

-04-03 17:08 GMT+04:00 Vladimir quickcrackt...@gmail.com: On Mon Jan 26 13:07:42 CET 2015 zilogpnz wrote: I'm trying to run Coreboot on Lenovo G505s and have a problem: - backlight of LCD is not turn on. But on the external LCD (by CRT connector) is all good. Could you help me

Re: [coreboot] Trouble with Coreboot on Lenovo G505s

-03 17:08 GMT+04:00 Vladimir quickcrackt...@gmail.com: On Mon Jan 26 13:07:42 CET 2015 zilogpnz wrote: I'm trying to run Coreboot on Lenovo G505s and have a problem: - backlight of LCD is not turn on. But on the external LCD (by CRT connector) is all good. Could you help me

Re: [coreboot] Lenovo G505S and Coreboot LTS Candidates list

country. But, despite having a somewhat similar hardware, nobody ported a coreboot to them yet :P Best regards, Vladimir Shipovalov On 7 April 2015 at 16:17, Emilian Bold emilian.b...@gmail.com wrote: My point is not to limit your LTS list to US laptops. US has *extraordinary* availability

[coreboot] Trouble with Coreboot on Lenovo G505s

On Mon Jan 26 13:07:42 CET 2015 zilogpnz wrote: I'm trying to run Coreboot on Lenovo G505s and have a problem: - backlight of LCD is not turn on. But on the external LCD (by CRT connector) is all good. Could you help me with a solution to this problem? Sorry for such a long reply, but what

Re: [coreboot] [Bug?] 3 different bytes in VGAbios after upgrade to coreboot

Thank you very much for solving this riddle! And one more question for Rudolf: please tell, are you using atomDis utility to disassemble atombios into C code? Or there are some other special tools, which probably have more recent versions? (latest version of atomDis is already 4 years old...) On

[coreboot] [Bug?] 3 different bytes in VGAbios after upgrade to coreboot

limited to my hardware ( Lenovo G505s ) , and maybe could lead to some other problems Please tell your opinion, is it a bug or I am wrong at something? Best regards, Vladimir Shipovalov -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Proposal: Removing obsolete & EOL boards and chipsets for 4.2 release

It would be really wrong to remove the whole AGESA code: there are AMD-based products which are still very alive and actively sold (at the developing markets) Moving the support for these products to a separate coreboot branch, could create many inconveniences for those AMD product owners who

Re: [coreboot] Proposal: Removing obsolete & EOL boards and chipsets for 4.2 release

- > Hash: SHA1 > > On 10/27/2015 03:10 PM, Vladimir wrote: > > It would be really wrong to remove the whole AGESA code: there are > > AMD-based products which are still very alive and actively sold (at the > > developing markets) Moving the support for these products t

Re: [coreboot] Proposal: Removing obsolete & EOL boards and chipsets for 4.2 release

t; servers are affected) Hopefully this blobgesa will be open sourced eventually - its not that far from reality because AMD open sourced a lot of stuff during the past months... Also it will be very interesting to see how AMD Zen platforms will behave Best regards, Vladimir Shipovalov On 28 October 201

Re: [coreboot] A case for branching AGESA

GESA build without moving it to a branch and separating from the rest of the coreboot code . So this is seen as a really bad excuse Best regards, Vladimir Shipovalov On 3 November 2015 at 01:14, Peter Stuge <pe...@stuge.se> wrote: > Alex G. wrote: > > >> users of AGESA can

Re: [coreboot] Removal of AGESA - to be or NOT to be? A story of G505S

branch, which means it would be abandoned. > > >>> On 11/07/2015 10:18 AM, Alex Gagniuc wrote: > >> >> such malevolent plans are a great insult to a bright spirit of coreboot ! >> > > I'm insulted by your portrayal of me as aforementioned > Your recent

[coreboot] Removal of AGESA - to be or NOT to be? A story of G505S

sult to the bright spirit of coreboot project ! Best regards, Vladimir Shipovalov -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Removal of AGESA - to be or NOT to be? A story of G505S

l be allowed to stay in its AGESA shape until a stable "Native Init" replacement will be introduced Best regards, Vladimir Shipovalov On 6 November 2015 at 20:34, Timothy Pearson < tpear...@raptorengineeringinc.com> wrote: > -BEGIN PGP SIGNED MESSAGE----- > Hash: SHA

[coreboot] AMD Geode LX 800 and the CS5536

find any BIOS on the internet. Please, someone - help me with my problem. Wbr, Vladimir. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] AMD Geode LX 800 and the CS5536

oh-ho-hohhh this words sounds like a judgement sentence for my hardware... please, please do something =) i can't watch my motherboard she absolutly dead... i can't see that. why? why she not supported? southbridge, main chipset and super i/o chip are similar 2009/8/20 Myles

Re: [coreboot] AMD Geode LX 800 and the CS5536

-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net: Hi Vladimir, does the board work with the current BIOS? In general, it is recommended to use v3 for all GeodeLX targets. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http

Re: [coreboot] AMD Geode LX 800 and the CS5536

hansolofal...@worldnet.att.net: Hello! I just checked your facts, Vladimir, regarding General Software at http://www.gensw.com and indeed that spot is holding a landing page. (That means that the domain is there but no content is available.) For me this is sad news as I was a great fan

Re: [coreboot] AMD Geode LX 800 and the CS5536

for my mistakes. 2009/8/28 Stefan Reinauer ste...@coresystems.de: On 8/28/09 11:41 AM, Vladimir Alexeev wrote: I'm check their mail server via DNS records for gensw.com and the result is negative. No mail server registred for this domain. This is realy bad. Seems to be thier company are closed

[coreboot] Winbond W83627 HG revision request

Greets! Can anyone make support for Winbond W83627-based microcontroller for HG revision this chip under AMD Geode LX generic motherboard. Or if can anyone make a patch for early blind initialization UART A port for debug output? wbr, Vladimir -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] x230 - vgabios

Le Sat, May 23, 2015 à 4:46 AM, Michael Gerlach n...@terminal21.de a écrit : -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Patrick! Uhm - I do not explicitly compressed it. I just added it to config.. Extracted it via echo 1 /sys/devices/pci\:00/\:00\:02.0/rom cp

[coreboot] Coreboot T-shirts

A contact of mine proposes to print coreboot T-shirts for the community. Black printing on white T-shirt. Expected price is 30€-35€ + shipping from CH or DE, double-sided printing, one-sided is 5-8€ less. It will be printed in Russia. I need to know who wants one and sizes by June 5th. For payment

Re: [coreboot] Coreboot T-shirts

Le 21 mai 2015 13:01, Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net a écrit : On 21.05.2015 12:51, Vladimir 'phcoder' Serbinenko wrote: A contact of mine proposes to print coreboot T-shirts for the community. Black printing on white T-shirt. Expected price is 30€-35€ + shipping

[coreboot] Fwd: Coreboot T-shirts

Apparently original mail didn't make it to the list. Resent -- Forwarded message -- From: Vladimir 'phcoder' Serbinenko phco...@gmail.com Date: Thu, May 21, 2015 at 2:29 PM Subject: Re: [coreboot] Coreboot T-shirts To: Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net Cc

Re: [coreboot] Dell Dimension 8300 reboots when grub2 cbfs module is loaded

Le 3 nov. 2015 6:46 PM, "Aaron Durbin" <adur...@google.com> a écrit : > > On Tue, Nov 3, 2015 at 10:28 AM, Vladimir 'phcoder' Serbinenko > <phco...@gmail.com> wrote: > > The code itself looks good but I'd like more details. Reading 0x > > sh

Re: [coreboot] Dell Dimension 8300 reboots when grub2 cbfs module is loaded

The code itself looks good but I'd like more details. Reading 0x shouldn't cause reboot. Why does it? Le 1 nov. 2015 3:53 PM, "Andrei Borzenkov" a écrit : > I was debugging problem reported by user on Dell Dimension 8300 - it > rebooted when doing "ls -l". It turned

Re: [coreboot] Goodies for Bonn meeting

Is size L ok for you? Le Wed, Oct 7, 2015 à 8:20 AM, Marc Jones <marcj...@gmail.com> a écrit : > Hi Vladimir, > > I'd love a shirt. See you in a few days. > > Marc > > On Tue, Oct 6, 2015, 11:53 PM Vladimir 'phcoder' Serbinenko < > phco...@gmail.com> wrote: &g

Re: [coreboot] Goodies for Bonn meeting

Reminder, please write me if you want any of this. Right now only Ron Minnich and echelon have ordered. I've added pictures at http://coreboot.org/Coreboot_conference_Bonn_2015 Le Wed, Sep 9, 2015 à 9:29 AM, Vladimir 'φ-coder/phcoder' Serbinenko < phco...@gmail.com> a écrit : > Hello

Re: [coreboot] Goodies for Bonn meeting

Currently remaining are: 8 x L T-shirts 1 x XL T-shirts 1 x yellow cup 3 x plates 3 x baseball cap 8 x magnets 5 x coasters Every item under 20€ Images: http://coreboot.org/Coreboot_conference_Bonn_2015 -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] Goodies for Bonn meeting

> > > I would like to order 3 plates, 1 white, 1 black, 1 pink cup and 1 magnet. > All reserved for you. > If you have extra white cups I'll buy those too. > > Sorry, only 1 was left before this e-mail. > If I don't make it in person I'll ask if someone might courier cash > and goodies on my

Re: [coreboot] Goodies for Bonn meeting

Le Tue, Oct 6, 2015 à 10:55 PM, Peter Stuge <pe...@stuge.se> a écrit : > Vladimir 'phcoder' Serbinenko wrote: > > Reminder, please write me if you want any of this. Right now only > > Ron Minnich and echelon have ordered. I've added pictures at &g

Re: [coreboot] Lenovo Carbon X1

Please send me the full log archive so I can reproduce. Also note: X1 carbon has soldered RAM which will need adjustements Le Sun, Dec 13, 2015 à 10:59 PM, Gerhard Gappmeier a écrit : > Hi all, > > > > unfortunately autoport didn't work well. > > > > This is the output on the

Re: [coreboot] Lenovo Carbon X1

I was unable to download as I'm not willing to give dropbox access to my contacts and I'm too lazy to make a new account now. Anyway the culprit is unsupported LPC. Here you go: https://review.coreboot.org/12820 Le Sat, Jan 2, 2016 à 1:39 AM, Vladimir 'phcoder' Serbinenko < phco...@gmail.

Re: [coreboot] Lenovo Carbon X1

f06b08a60fe49784c197929b46e22fdb0e1dbbf3 is how to handle. spd.bin is generated by inteltool Le Sat, Jan 2, 2016 à 1:49 AM, Vladimir 'phcoder' Serbinenko < phco...@gmail.com> a écrit : > I was unable to download as I'm not willing to give dropbox access to my > contacts and I'm too

Re: [coreboot] RFC: Changing CBMEM console to run as a persistent ring-buffer

On Tue, Apr 25, 2017, 20:15 Julius Werner wrote: > I'm very concerned with compatibility. You can't guarantee that coreboot >> and payload match. And in case of mismatch you get a memory corruption that >> is very hard to trace. Can we please change signature of cbmem

Re: [coreboot] RFC: Changing CBMEM console to run as a persistent ring-buffer

I'm very concerned with compatibility. You can't guarantee that coreboot and payload match. And in case of mismatch you get a memory corruption that is very hard to trace. Can we please change signature of cbmem entry? You mentioned having trouble building GRUB. Can you detail those? What do you

Re: [coreboot] grub payload fails on coreboot

-de...@gnu.org http://lists.gnu.org/mailman/listinfo/grub-devel -- Regards Vladimir 'φ-coder/phcoder' Serbinenko signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [PATCH] Fix coreboot qemu RAM size detection

Stefan Reinauer wrote: On 5/2/10 5:00 PM, Vladimir 'φ-coder/phcoder' Serbinenko wrote: Hello, when testing on QEMU I noticed that it always assumed 64 MiB RAM. Fix attached. Tested from 16 MiB to 2047 MiB Hi Vladimir, please sign off your patch so we can commit it: http

Re: [coreboot] spkmodem

On 18.01.2013 12:01, Vladimir 'φ-coder/phcoder' Serbinenko wrote: Hello, all. I send a patch to make coreboot output console using system beeper and a corresponding code to interpret those beeps. I publish it under GPLv2+ but other licensing arrangements are possible. This was very useful

Re: [coreboot] spkmodem

On 18.01.2013 17:18, Paul Menzel wrote: Am Freitag, den 18.01.2013, 17:12 +0100 schrieb Peter Stuge: Vladimir 'φ-coder/phcoder' Serbinenko wrote: Hello, all. I send a patch to make coreboot output console using system beeper and a corresponding code to interpret those beeps. I publish

[coreboot] Fwd: spkmodem

Original Message Subject: spkmodem Date: Fri, 18 Jan 2013 12:01:15 +0100 From: Vladimir 'φ-coder/phcoder' Serbinenko phco...@gmail.com To: coreboot@coreboot.org Hello, all. I send a patch to make coreboot output console using system beeper and a corresponding code to interpret

Re: [coreboot] spkmodem

On 18.01.2013 17:12, Peter Stuge wrote: Vladimir 'φ-coder/phcoder' Serbinenko wrote: Hello, all. I send a patch to make coreboot output console using system beeper and a corresponding code to interpret those beeps. I publish it under GPLv2+ but other licensing arrangements are possible

[coreboot] spkmodem

. -- Regards Vladimir 'φ-coder/phcoder' Serbinenko diff --git a/src/console/Kconfig b/src/console/Kconfig index b1f41de..76864ae 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -114,6 +114,12 @@ config TTYS0_LCS default 3 depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM +config

[coreboot] [PATCH v2] spkmodem

A new version of spkmodem. This one doesn't lose the bit sync even if I disconnect the cable for the short time (but, of course data sent when no cable is attached is lost) -- Regards Vladimir 'φ-coder/phcoder' Serbinenko diff --git a/src/console/Kconfig b/src/console/Kconfig index b1f41de

Re: [coreboot] [PATCH v2] spkmodem

On 21.01.2013 15:10, Vladimir 'φ-coder/phcoder' Serbinenko wrote: A new version of spkmodem. This one doesn't lose the bit sync even if I disconnect the cable for the short time (but, of course data sent when no cable is attached is lost) Did you receive this mail? The attachments

Re: [coreboot] [PATCH v2] spkmodem

On 22.01.2013 20:08, Stefan Reinauer wrote: * Vladimir 'φ-coder/phcoder' Serbinenko phco...@gmail.com [130121 15:10]: A new version of spkmodem. This one doesn't lose the bit sync even if I disconnect the cable for the short time (but, of course data sent when no cable is attached is lost

Re: [coreboot] Gerrit problem: Not able to sign in

? Thanks, Paul I have the same problem -- Regards Vladimir 'φ-coder/phcoder' Serbinenko signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

[coreboot] X201 status

Current status. Raminit: works with delays/printfs currently in place, 1-ranked memory populating one slot. Didn't test in any other config yet (either removing debug and delays or trying other type of memory). Looks like resulting settings are slower than original BIOS due to me skipping some of

Re: [coreboot] X201 status

On 28.02.2013 22:59, Vladimir 'φ-coder/phcoder' Serbinenko wrote: Current status. Raminit: works with delays/printfs currently in place, 1-ranked memory populating one slot. Didn't test in any other config yet (either removing debug and delays or trying other type of memory). Looks like

[coreboot] X201 port is in gerrit

Hello, all. I've pushed my X201 work to gerrit. It also contains spkmodem and serialice improvements (target-side, like EHCI debug support). Host-side I attach a small patch to redirect clflush to target. Code quality is bad but it already works. Current known issues: speedstep doesn't work S3

Re: [coreboot] X201 port is in gerrit

On 12.03.2013 16:09, Vladimir 'φ-coder/phcoder' Serbinenko wrote: Hello, all. I've pushed my X201 work to gerrit. It also contains spkmodem and serialice improvements (target-side, like EHCI debug support). Host-side I attach a small patch to redirect clflush to target. Code quality is bad

[coreboot] X201 bootblock unlocking

Hello all. On X201 top 192K are locked. Fortunately the original BIOS has a way to update this region. If you extract a X201 image you'll find a lzint compressed file which makes 192K decompressed. It's the update. In it you can simply replace 74f8d1fe (PR0) with 74f8d0ff (harmless address with

Re: [coreboot] On loongson CPU or MIPS ARCH

do we have plan to add loongson CPU or MIPS ARCH support? Loongson platforms are very different from any x86 boards. I believe that coreboot in this case would get more in the way than help. I ported GRUB to be firmware on Yeloong 2F and Fuloong 2F. Everything coreboot does on x86 including

Re: [coreboot] On loongson CPU or MIPS ARCH

On 26.04.2013 23:07, ron minnich wrote: I'll look at that code. As a side note: fwstart.S inits video on yeeloong, this was done so because I was under impression that watchdog was conditioned on video init while in fact I applied wrong GPIO map. It stayed this way but doesn't have to be so.

Re: [coreboot] On loongson CPU or MIPS ARCH

On 29.04.2013 03:18, li guang wrote: 在 2013-04-26五的 22:08 +0200，Vladimir 'φ-coder/phcoder' Serbinenko写 道： do we have plan to add loongson CPU or MIPS ARCH support? Loongson platforms are very different from any x86 boards. I believe that coreboot in this case would get more in the way

Re: [coreboot] On loongson CPU or MIPS ARCH

On 29.04.2013 04:09, ron minnich wrote: not everyone wants or needs grub. So that's part of the point. Could we have a sane discussion about why it's not suitable for this or that scenario and what would need to be fixed? Not just quasi-fanatical I don't want it. signature.asc Description:

Re: [coreboot] On loongson CPU or MIPS ARCH

Yes, I'm querying coreboot for the similar consideration. Is payload indispensable? can we directly load kernel image? Not in the tiny ROM available on this machine (512KiB). And 512K is absolute maximum you can put on it (parallel flash) signature.asc Description: OpenPGP digital

Re: [coreboot] On loongson CPU or MIPS ARCH

On 29.04.2013 04:48, Peter Stuge wrote: Vladimir 'φ-coder/phcoder' Serbinenko wrote: not everyone wants or needs grub. So that's part of the point. Could we have a sane discussion about why it's not suitable IMO it's a clusterfuck as far as usability is concerned for one. But this isn't

Re: [coreboot] On loongson CPU or MIPS ARCH

Loongson platform be designed mostly like a PC, it also control PCI devices. It has just one PCI bus with all devices fixed. That hardly requires the whole complexity of coreboot. because of the payload concept, where coreboot only initializes only the minimum of the hardware and a

[coreboot] Coreboot hackathon hardware

Hello, all. I'll be at LinuxTAG and hackathon. This mail is to ask if someone needs some of hw I can take with me (list at the end), I won't take it unless I have requests. Does anybody want to share rooms to save on hotel costs? HW List: PL2303 USB-RS232 converter bus pirate 2 SOIC 8-pin clips

[coreboot] Management engine firmware

Hello, all. In order to build X201 rom, you need management engine firmware. For chromebook the appropriate blobs are in 3rdparty repo, I suppose supplied by Intel. The only place where I could get ME firmware for X201 is by dumping chip with external programmer. It's probably not appropriate for

Re: [coreboot] Management engine firmware

On 13.06.2013 03:41, George Chriss wrote: On Wed, Jun 12, 2013 at 7:16 PM, Vladimir 'φ-coder/phcoder' Serbinenko phco...@gmail.com mailto:phco...@gmail.com wrote: Hello, all. In order to build X201 rom, you need management engine firmware. For chromebook the appropriate blobs are in 3rdparty

Re: [coreboot] google/butterfly: Erratic touchpad behavior in cold weather

On 30.11.2013 16:25, mrnuke wrote: Have any of you noticed this with the Pavilion 14 Chromebook? You take it outside from the warm house, open the lid to resume, and the mouse pointer moves heratically. It becomes impossible to co control, and the only way to bring it back to sanity is to

Re: [coreboot] Lenovo X201i

On 30.11.2013 17:51, Chris Mailer wrote: Hello Coreboot, I would like to play around with Coreboot on a Lenovo X201i convertible laptop. According to http://www.coreboot.org/Supported_Motherboards#Laptops and some wiki-entries Coreboot does do well on the X201. Does this imply Coreboot

[coreboot] CBFS hardlinks

Hello, all. Currently coreboot does the mapping from PCIID to the name of option ROM in platform-dependent part (one PCIID is chosen as representative of whole family). Unfortunately SeaBIOS doesn't have this mapping and so doesn't find the right file. Could we perhaps have hardlinks in CBFS and

Re: [coreboot] Removing microcode updates from blobs

On 14.12.2013 07:46, mrnuke wrote: On 12/14/2013 12:36 AM, ron minnich wrote: And I think it even worse to put the microcode blobs in a location in the tree that implies, by its existence, that you can build without them and get a more free, working firmware image. You can't have a working

Re: [coreboot] Removing microcode updates from blobs

On 14.12.2013 07:59, ron minnich wrote: On Fri, Dec 13, 2013 at 10:46 PM, mrnuke mr.nuke...@gmail.com wrote: What's the point? Why not just enlighten them? I just can not understand this. Some distros have a policy of putting free and non-free components in separate repositories (E.g Debian

Re: [coreboot] New laptop: Lenovo ThinkPad X230 tablet, with dumps to go with it

On 15.09.2012 05:47, Keith Hui wrote: Hi all, I'm back. With a new laptop. I'm now rocking a Lenovo x230 tablet, http://review.coreboot.org/#/c/4614/ signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] does coreboot support kvm WPCE775x other questions

On 05.01.2014 07:15, Gregg Levine wrote: Part of the problem with laptops is that there is a thing on them called an Embedded Controller, EC for short. Those devices do all of the housekeeping chores that the main system has delegated to them. For example certain functions are on it. To

[coreboot] Remove GENERATE_ACPI_TABLES

By now most boards and OS don't run correctly if ACPI tables are not supplied. Ability by user to enable/disable their generation is just increasing configuration matrix for no benefit. So I propose to hardwire it to HAVE_ACPI_TABLES. I feel like in current config there are too many options of

Re: [coreboot] Remove GENERATE_ACPI_TABLES

On 07.01.2014 00:12, mrnuke wrote: On Monday, January 06, 2014 07:52:20 PM Vladimir 'φ-coder/phcoder' Serbinenko wrote: By now most boards and OS don't run correctly if ACPI tables are not supplied. Ability by user to enable/disable their generation is just increasing configuration matrix

[coreboot] Seeking for reviewers: X201 (enable S3 al) and X230

Hello, all. I've just uploaded 2 patchsets: X201 which fixes all known issues including S3 resume but except Gnome battery reporting. Top for x201 is at http://review.coreboot.org/#/c/4632/ and few separate patches with theme x201 (X201-specific) and thinkpad (having benefits for X60/T60 as well).

[coreboot] cmos.layout upgradability

Hello, all. Due to my failue to foresee this problem if one upgrades X60 coreboot, you need to manually reset CMOS config or your trackpad may not work as option trackpad_enable will get a garbage value. While I admit my part of fault, I feel like we should have a way to update options safely. I

[coreboot] Fwd: Re: coreboot port for macbook2,1

Original Message Subject: Re: [coreboot] coreboot port for macbook2,1 Date: Sat, 25 Jan 2014 01:23:12 +0100 From: Vladimir 'φ-coder/phcoder' Serbinenko phco...@gmail.com To: Mono m...@posteo.de On 24.01.2014 23:20, Mono wrote: Hallo, Would you help me on a coreboot port? I

Re: [coreboot] Fwd: Re: coreboot port for macbook2,1

On 25.01.2014 01:23, Vladimir 'φ-coder/phcoder' Serbinenko wrote: Original Message Subject: Re: [coreboot] coreboot port for macbook2,1 Date: Sat, 25 Jan 2014 01:23:12 +0100 From: Vladimir 'φ-coder/phcoder' Serbinenko phco...@gmail.com To: Mono m...@posteo.de

Re: [coreboot] cmos.layout upgradability

On 25.01.2014 01:28, mrnuke wrote: On Saturday, January 25, 2014 12:51:25 AM Vladimir 'φ-coder/phcoder' Serbinenko wrote: Hello, all. Due to my failue to foresee this problem if one upgrades X60 coreboot, you need to manually reset CMOS config or your trackpad may not work as option

Re: [coreboot] cmos.layout upgradability

http://www.coreboot.org/Infrastructure_Projects#Provide_update_paths_and_avoid_conflicts_in_addressing (which mentions another solution to the problem) Flashrom solution is interesting but it doesn't handle external flashing. It would be a nice addition to checksums for internal flashing

Re: [coreboot] cmos.layout upgradability

On 26.01.2014 05:55, Vladimir 'φ-coder/phcoder' Serbinenko wrote: http://www.coreboot.org/Infrastructure_Projects#Provide_update_paths_and_avoid_conflicts_in_addressing (which mentions another solution to the problem) Flashrom solution is interesting but it doesn't handle external flashing

Re: [coreboot] Lenovo Thinkpad T61

On 31.01.2014 17:08, Roberto A. Foglietta wrote: 2014-01-31 Peter Stuge pe...@stuge.se mailto:pe...@stuge.se: Roberto A. Foglietta wrote: I check the list of supported motherboards and laptops but I did not found in them the Lenovo Thinkpad T61 That means that

Re: [coreboot] Lenovo Thinkpad T61

On 31.01.2014 17:21, ron minnich wrote: If your only way to flash the flash is via a program, or something embedded in the lenovo bios, stop now, or stockpile 20 or 30 of these laptops, because you're going to create some bricks along the way. Let me elaborate on this: RTFM

Re: [coreboot] Lenovo Thinkpad T61

On 31.01.2014 20:30, ron minnich wrote: If you want a laptop to tear into and learn from, the old samsung x86 chromebook is hard to beat. ram and disk are standard and upgradable, you can put a clip on the flash part, ... Lenovo X201 and X230 both have those characteristics as well. Unlike

Re: [coreboot] Please use Git commit hooks

On 02.02.2014 12:05, Paul Menzel wrote: Dear coreboot folks, if you push patches please either check them manually or simply let the Git commit hooks do it for you by running `make gitconfig`. I know they take a lot of time especially when you run them the first time in a session. This

Re: [coreboot] coreboot port for macbook2,1

On 03.02.2014 21:43, Mono wrote: Hallo Vladimir, Peter and Stefan thank you for your emails! You already helped me alot. I don't expect to successfully close this project in a fast run and I'm willing to learn a number of tools. At the moment I am still collecting hardware informations

Re: [coreboot] Motherboard Not on Support MB List - Specs

On 03.02.2014 17:37, lee.changhan wrote: Hi, I have some info about my motherboard here according to the FAQ page to see if anyone can tell me about the compatibility between my BIOS and coreboot. Your motherboard is not compatible with coreboot. 1. Gigabyte GA-Z77-HD3 Motherboard

Re: [coreboot] coreboot port for macbook2,1

CY8C24794-24LFXI My guess: it's part of keyboard + touchpad Do you already know which port is USBdebug one? Did you already test USB debug with dbgp? Um, there are much more 00's than for the Thinkpad X60. Not sure what this means Different firmware. Most likely less functions are on it

[coreboot] [RFT] Lenovo convertible tablets X60t, X201t, X230t

Hello, all. I've uploaded digitizer support for X*t variants. Not tested in current form yet (was developped on Jens Erat's X201T during FOSDEM). Please test: - X60t owners: http://review.coreboot.org/#/c/5113/ - X201t owners: http://review.coreboot.org/#/c/5096 - X230t owners: should work without

Re: [coreboot] Support for Dell desktop motherboard

On 06.02.2014 23:46, Ramkumar Ramachandra wrote: Hi, I have a Dell T5500 desktop, and I'd like to know if Coreboot supports this. No. http://www.coreboot.org/Supported_Motherboards According to dmidecode, the motherboard is a Dell 0D883F. Thanks. Ram signature.asc Description:

Re: [coreboot] HP Chromebook 14 (Falco)

On 07.02.2014 17:57, Rubén Torrero Marijnissen wrote: Hi, I grew tired today of the default firmware that comes with my Google Chromebook 14; just when I had my Arch Linux install perfectly working somehow, by letting it attempt to boot Chrome OS, it messed up my partitions. If I have

Re: [coreboot] coreboot port for macbook2,1

On 08.02.2014 15:27, Mono wrote: Hallo, On Mon, Feb 03, 2014 at 10:16:30PM +0100, Vladimir 'φ-coder/phcoder' Serbinenko wrote: CY8C24794-24LFXI My guess: it's part of keyboard + touchpad Do you already know which port is USBdebug one? Yes, I found out with a USB stick, dmesg and lsusb -t

Re: [coreboot] LinuxTag in Berlin from May 8–10, 2014

On 08.02.2014 23:13, Paul Menzel wrote: Dear coreboot folks, just a short announcement that after FOSDEM last weekend the next free software event (in Europe(?)) is going to be LinuxTag in Berlin from May 8–10, 2014. I won't be able to attend The location is going to be different this

Re: [coreboot] [RFC] board_status: Add serial log to `serial_console.txt`

On 09.02.2014 13:50, Paul Menzel wrote: Dear coreboot folks, currently no coreboot messages are stored for boards not supporting CBMEM console Is there any remaining? If so it's an issue to be fixed (or where this option is disabled (currently by default)) Change the defaults. or no

Re: [coreboot] [RFC] board_status: Add serial log to `serial_console.txt`

On 09.02.2014 14:34, Paul Menzel wrote: Am Sonntag, den 09.02.2014, 14:18 +0100 schrieb Vladimir 'φ-coder/phcoder' Serbinenko: On 09.02.2014 13:50, Paul Menzel wrote: currently no coreboot messages are stored for boards not supporting CBMEM console Is there any remaining? If so it's

Re: [coreboot] [RFC] board_status: Add serial log to `serial_console.txt`

some prefix to clearly indicate that user was involved in creating them. E.g. user_serial_log.txt But in general I think I agree with Vladimir. CBMEM console should be supported and if not then that should be fixed. -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc

Re: [coreboot] [RFC] board_status: Add serial log to `serial_console.txt`

On 11.02.2014 01:56, mrnuke wrote: On Tuesday, February 11, 2014 12:04:33 AM Vladimir 'φ-coder/phcoder' Serbinenko wrote: If we let user supply files at all, it should be added to report, not replace files, and it should have some prefix to clearly indicate that user was involved

Re: [coreboot] SeaVGABIOS with native vga init (Need testers)

On 13.02.2014 01:23, Kevin O'Connor wrote: Looking through the output of $ git grep k8t890 src/mainboard/ the boards Asus A8V-E Deluxe, Asus A8V-E SE, Asus K8V-X, Asus M2V-MX SE and Asus M2V should theoretically support that. Okay. The SeaVGABIOS implementation is expecting a

Re: [coreboot] coreboot port for macbook2,1

. That is pretty normal. Some firmwares store debug log or parameters in flash. best regards Mono On Sat, Feb 08, 2014 at 03:37:40PM +0100, Vladimir 'φ-coder/phcoder' Serbinenko wrote: On 08.02.2014 15:27, Mono wrote: Hallo, On Mon, Feb 03, 2014 at 10:16:30PM +0100, Vladimir 'φ-coder/phcoder

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