BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2884
Added new approved ECR for the CXL Protocol Error Section.
Signed-off-by: Ashraf Javeed
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
--
---
MdePkg/Include/Guid/Cper.h | 75
My response inline.
Regards
Ashraf
> -Original Message-
> From: Gao, Liming
> Sent: Monday, July 27, 2020 8:25 PM
> To: devel@edk2.groups.io; l...@nuviainc.com; Javeed, Ashraf
>
> Cc: Kinney, Michael D ; Gao, Liming
>
> Subject: RE: [edk2-devel] [PATC
Leif, Liming,
My comments inline below.
Thanks
Ashraf
> -Original Message-
> From: Ni, Ray
> Sent: Tuesday, July 28, 2020 8:06 AM
> To: devel@edk2.groups.io; Gao, Liming ; Leif Lindholm
> ; Javeed, Ashraf ; Laszlo Ersek
> ; Sean Brogan
> Cc: Kinney, Mich
Thank you Liming and Mike for the review.
I have sent the new patches for this.
Regards
Ashraf
> -Original Message-
> From: Kinney, Michael D
> Sent: Friday, July 24, 2020 10:42 PM
> To: Javeed, Ashraf ; Gao, Liming
> ; devel@edk2.groups.io; Kinney, Michael D
>
&g
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Register definitions from chapter 7 of Compute Express Link
Specification Revision 1.1 are ported into the new Cxl11.h.
The CXL Flex Bus registers are based on the PCIe Extended Capability
DVSEC structure header, led to the inclusion of
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Introducing the Cxl.h as the main header file to support all versions
of Compute Express Link Specification register definitions.
Signed-off-by: Ashraf Javeed
Cc: Michael D Kinney
Cc: Liming Gao
--
V4: fix code style
V3: Copyright date
These 2 patches introduces the Compute Express Link (CXL) Specificition
defined registers.
The Cxl11.h has the actual register definitions of the CXL Specification
Revision 1.1; and the Cxl.h is the main header file to include all
versions of the CXL register definitions.
REF:
Liming.
Thanks for completing the review.
This is just a comment change ask and I can mend the comment to send again.
Ashraf
> -Original Message-
> From: Gao, Liming
> Sent: Thursday, July 23, 2020 3:18 PM
> To: Javeed, Ashraf ; devel@edk2.groups.io
> Cc: Kinney, Micha
Liming;
My response inline.
Thanks for the review.
Ashraf
> -Original Message-
> From: Gao, Liming
> Sent: Thursday, July 23, 2020 3:36 PM
> To: devel@edk2.groups.io; Javeed, Ashraf
> Cc: Kinney, Michael D
> Subject: RE: [edk2-devel] [PATCH V3 1/2] MdePkg/Includ
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Register definitions from chapter 7 of Compute Express Link
Specification Revision 1.1 are ported into the new Cxl11.h.
The CXL Flex Bus registers are based on the PCIe Extended Capability
DVSEC structure header, led to the inclusion of
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Introducing the Cxl.h as the main header file to support all versions
of Compute Express Link Specification register definitions.
Signed-off-by: Ashraf Javeed
Cc: Michael D Kinney
Cc: Liming Gao
--
V2: Indentation and double declaration
These 2 patches introduces the Compute Express Link (CXL) Specificition
registers definitions to the MDE.
The Cxl11.h has the actual register definitions of the CXL Specification
Revision 1.1; and the Cxl.h is the main header file to include all
versions of the CXL register definitions.
REF:
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Register definitions from chapter 7 of Compute Express Link
Specification Revision 1.1 are ported into the new Cxl11.h.
The CXL Flex Bus registers are based on the PCIe Extended Capability
DVSEC structure header, led to the inclusion of
These 2 patches introduces the Compute Express Link (CXL) Specificition
registers definitions to the MDE.
The Cxl11.h has the actual register definitions of the CXL Specification
Revision 1.1; and the Cxl.h is the main header file to include all versions of
the CXL register definitions.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Introducing the Cxl.h as the main header file to support all versions
of Compute Express Link Specification register definitions.
Signed-off-by: Ashraf Javeed
Cc: Michael D Kinney
Cc: Liming Gao
--
V2: Indentation and double declaration
HI Mike,
My response inline.
Thanks for reviewing.
Ashraf
> -Original Message-
> From: Kinney, Michael D
> Sent: Wednesday, July 15, 2020 9:14 AM
> To: devel@edk2.groups.io; Javeed, Ashraf ; Kinney,
> Michael D
> Cc: Gao, Liming
> Subject: RE: [edk2-devel] [
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Register definitions from chapter 7 of Compute Express Link Specification
Revision 1.1 are ported into the new Cxl11.h.
The CXL Flex Bus registers are based on the PCIe Extended Capability
DVSEC structure header, led to the inclusion of
These 2 patches introduces the Compute Express Link (CXL) Specificition
registers definitions to the MDE.
The Cxl11.h has the actual register definitions of the CXL Specification
Revision 1.1; and the Cxl.h is the main header file to include all versions of
the CXL register definitions.
Ashraf
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Introducing the Cxl.h as the main header file to support all versions of
Compute Express Link Specification register definitions.
Signed-off-by: Ashraf Javeed
Cc: Michael D Kinney
Cc: Liming Gao
---
MdePkg/Include/IndustryStandard/Cxl.h
Thanks
Ashraf
> -Original Message-
> From: Ni, Ray
> Sent: Wednesday, May 13, 2020 12:19 PM
> To: Javeed, Ashraf ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Wu, Hao A
>
> Subject: RE: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 12/15]
> MdeModulePkg/PciBu
My response in line.
Thanks
Ashraf
> -Original Message-
> From: Ni, Ray
> Sent: Wednesday, May 13, 2020 12:16 PM
> To: Javeed, Ashraf ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Wu, Hao A
>
> Subject: RE: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 07/15]
> MdeMod
Yes, both the comments shall be fixed.
Thanks
Ashraf
> -Original Message-
> From: Ni, Ray
> Sent: Wednesday, May 13, 2020 12:09 PM
> To: Javeed, Ashraf ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Wu, Hao A
>
> Subject: RE: [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH
These patches are uploaded in the following repo, for your reference:
https://github.com/ashrafj/edk2-staging/commits/UEFI_PCI_ENHANCE-2
Regards
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Sunday, May 10, 2020 9:58 PM
>
of the PCI Express Protocol and code refactoring of the PCIe
features in the PciBusDxe.
Signed-off-by: Ashraf Javeed
Cc: Jian J Wang
Cc: Hao A Wu
Cc: Ray Ni
Cc: Ashraf Javeed
---
Ashraf Javeed (15):
MdePkg/Protocols: Deprecated the EFI encoded macros
MdeModulePkg/PciBusDxe: PciBusDxe Code
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1954
Deprecated the EFI encoded macros for the following PCIe features and
renamed its policy variables in EFI_PCI_EXPRESS_DEVICE_POLICY as
shown below:
1. Maximum Payload Size (MPS) -> MaxPayloadSize
2. Maximum Read Request Size (MRRS) ->
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
The framework
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Add the Program phase
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Add the Program phase
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Add the Program phase
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Add the Scan and
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Add the Program phase
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Rename the cache PCIe
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Add the Program phase
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Add the Scan and
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Add the Program phase
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Refactor the PCIe
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Add the Program phase
REF:
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
Signed-off-by: Ashraf
About the "AtomicOp", I want to retract about the check for the Routing
Capability to set the platform policy about the blocking the AtomicOp requests.
The implementation seems good.
Thanks
Ashraf
> -Original Message-
> From: Javeed, Ashraf
> Sent: Tuesday, Apri
About the "CompletionTimeout ", I want to retract about the AUTO option; the
implementation is good and device initialization should be skipped for this
option.
Regards
Ashraf
> -Original Message-
> From: Javeed, Ashraf
> Sent: Monday, April 20, 2020 6:53 PM
> To
agree?
Thanks
Ashraf
> -Original Message-
> From: Ni, Ray
> Sent: Tuesday, March 17, 2020 9:07 PM
> To: Javeed, Ashraf ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Wu, Hao A
>
> Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH
> 05/12] PciBusDxe:
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Tuesday, March 31, 2020 7:33 AM
> To: devel@edk2.groups.io
> Subject: [edk2-devel] [PATCH V3 0/2] MdePkg-IndustryStandard: CXL Base
> Specification registers
>
> These se
These set of two patches introduces the CXL Base Specification register
definitions
to the MDE; the Cxl11.h has the register definitions for revision 1.1, and the
header
Cxl.h is the main wrapper header file to support all versions of CXL Base
Specification
register definitions.
Ashraf Javeed
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Introducing the Cxl.h as the main header file to support all versions of
CXL Base Specification register definitions.
Signed-off-by: Ashraf Javeed
Cc: Michael D Kinney
Cc: Liming Gao
---
MdePkg/Include/IndustryStandard/Cxl.h | 18
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Register definitions from chapter 7 of CXL Base Specification Rev.1.1
are ported into the new Cxl11.h.
The CXL Flex Bus registers are based on the PCIe Extended Capability
DVSEC structure header, led to the inclusion of upgraded Pci.h.
OK
Thanks
Ashraf
> -Original Message-
> From: Gao, Liming
> Sent: Monday, March 30, 2020 7:27 PM
> To: Javeed, Ashraf ; devel@edk2.groups.io
> Cc: Kinney, Michael D
> Subject: RE: [PATCH V2 2/2] MdePkg-IndustryStandard: CXL 1.1 Base
> Specification registers
&g
OK
Thanks
Ashraf
> -Original Message-
> From: Gao, Liming
> Sent: Monday, March 30, 2020 7:26 PM
> To: Javeed, Ashraf ; devel@edk2.groups.io
> Cc: Kinney, Michael D
> Subject: RE: [PATCH V2 1/2] MdePkg-IndustryStandard: CXL 1.1 Base
> Specification registers
&g
: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Saturday, March 21, 2020 10:37 PM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ; Gao, Liming
>
> Subject: [edk2-deve
-=-=-=-=-=-=-=-=-=-=-=-
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Mute This Topic: https://groups.io/mt/72449748/21656
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Unsubscribe:
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Register definitions from chapter 7 of CXL Base Specification Rev.1.1
are ported into the new Cxl11.h.
The CXL Flex Bus registers are based on the PCIe Extended Capability
DVSEC structure headers, hence the Pci.h has to upgraded.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Introducing the Cxl.h as the main header file to support all versions of
CXL Base Specification register definitions.
Signed-off-by: Ashraf Javeed
Cc: Michael D Kinney
Cc: Liming Gao
---
MdePkg/Include/IndustryStandard/Cxl.h | 18
nal Message-
> From: Kinney, Michael D
> Sent: Friday, March 20, 2020 9:24 PM
> To: Javeed, Ashraf ; devel@edk2.groups.io;
> Kinney, Michael D
> Cc: Gao, Liming
> Subject: RE: [PATCH V1] MdePkg-IndustryStandard: CXL 1.1 Base
> Specification registers
>
> Ashraf,
>
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2611
Register definitions from chapter 7 of CXL Base Specification Rev.1.1
are ported into the new Cxl11.h.
Since CXL uses the underlying PCIe technology for interconnect, it uses
the PCIe Extended Capability DVSEC structures for its Flex Bus
Thursday, March 19, 2020 2:30 PM
> To: Javeed, Ashraf ; Gao, Liming
> ; Liu, Zhiguang ; Kinney,
> Michael D
> Cc: devel@edk2.groups.io
> Subject: RE: [edk2-devel] [PATCH V2] MdePkg-PciExpress40.h: DVSEC
> definition missing
>
> I am sorry I just noticed t
Thanks Liming!
Ashraf
> -Original Message-
> From: Gao, Liming
> Sent: Thursday, March 19, 2020 7:32 AM
> To: devel@edk2.groups.io; Gao, Liming ; Javeed,
> Ashraf ; Liu, Zhiguang
> Cc: Kinney, Michael D
> Subject: RE: [edk2-devel] [PATCH V2] MdePkg-PciExpress40.
Yes, I verified the build with this patch by directly referencing the new data
types in a source file.
Thanks
Ashraf
> -Original Message-
> From: Gao, Liming
> Sent: Wednesday, March 18, 2020 8:11 AM
> To: Liu, Zhiguang ; Javeed, Ashraf
> ; devel@edk2.groups.io
> Cc:
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
All registers definition of DVSEC are defined as per the PCI Express Base
Specification 4.0 chapter 7.9.6.
Signed-off-by: Ashraf Javeed
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
V2: fixed the comment section description for
Kindly ignore this as I have sent only the delta portion of previous patch.
I shall send the whole patch again.
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Tuesday, March 17, 2020 1:22 PM
> To: devel@edk2.groups.
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2598
All registers definition of DVSEC are defined as per the PCI Express Base
Specification 4.0 chapter 7.9.6.
Signed-off-by: Ashraf Javeed
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Zhiguang Liu
V2: fixed the comment section description for
Hi Zhiguang,
Good catch! I shall fix it as per your suggestion.
Thanks
Ashraf
> -Original Message-
> From: Liu, Zhiguang
> Sent: Tuesday, March 17, 2020 12:46 PM
> To: devel@edk2.groups.io; Javeed, Ashraf
> Cc: Kinney, Michael D ; Gao, Liming
>
> Subject: RE: [
My response below.
Thanks
Ashraf
> -Original Message-
> From: Ni, Ray
> Sent: Monday, March 16, 2020 7:30 PM
> To: Javeed, Ashraf ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Wu, Hao A
>
> Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH
> 05/
From: Ni, Ray
> Sent: Thursday, March 5, 2020 7:43 PM
> To: devel@edk2.groups.io; Ni, Ray ; Javeed, Ashraf
>
> Cc: Wang, Jian J ; Wu, Hao A
>
> Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH
> 05/12] PciBusDxe: Setup sub-phases for PCI feature enumeration
>
BZ:https://bugzilla.tianocore.org/show_bug.cgi?id=2598
All registers definition of DVSEC are defined as per the PCI Express Base
Specification 4.0 chapter 7.9.6.
Signed-off-by: Ashraf Javeed
Cc: Michael D Kinney
Cc: Liming Gao
---
MdePkg/Include/IndustryStandard/PciExpress40.h | 24
> -Original Message-
> From: Ni, Ray
> Sent: Monday, February 10, 2020 2:16 PM
> To: Javeed, Ashraf ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Wu, Hao A
> Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12]
> MdeModulePkg/PciBusDxe: Setup P
> -Original Message-
> From: Ni, Ray
> Sent: Monday, February 10, 2020 2:08 PM
> To: Javeed, Ashraf ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Wu, Hao A
> Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 01/12]
> MdeModulePkg/PciBusDxe: Setup for
Ray,
I have responded to your review comments.
These patches has been changed accommodating your previous review comments.
Please check.
Thanks
Ashraf
> -Original Message-
> From: Ni, Ray
> Sent: Monday, February 10, 2020 1:10 PM
> To: Javeed, Ashraf ; devel@edk2.groups.i
Thanks
Ashraf
> -Original Message-
> From: Ni, Ray
> Sent: Monday, February 10, 2020 1:07 PM
> To: Javeed, Ashraf ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Wu, Hao A
> Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 02/12]
> MdeModulePkg/PciBusD
My comments below.
Thanks
Ashraf
> -Original Message-
> From: Ni, Ray
> Sent: Monday, February 10, 2020 12:50 PM
> To: Javeed, Ashraf ; devel@edk2.groups.io
> Cc: Wang, Jian J ; Wu, Hao A
> Subject: RE: [edk2-devel] [edk2-staging/UEFI_PCI_ENHANCE-2 PATCH 01/12]
> M
This patch can also be viewed in the following repo:-
https://github.com/ashrafj/edk2-staging/commit/34a6c33558aed624ca95f719e5df4f3363f7cb05
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Saturday, February 8,
This patch can also be viewed in the following repo:-
https://github.com/ashrafj/edk2-staging/commit/f0d81499e79e4521630a76ae241de6def9aa03b5
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Saturday, February 8,
This patch can also be viewed in the following repo:-
https://github.com/ashrafj/edk2-staging/commit/fd03852add274895880971e38f07e30d5fd79863
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Saturday, February 8,
This patch can also be viewed in the following repo:-
https://github.com/ashrafj/edk2-staging/commit/6c502aea8f5483abbded1023166896c6baa9290d
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Saturday, February 8,
This patch can also be viewed in the following repo:-
https://github.com/ashrafj/edk2-staging/commit/7f0ea5bf87b220b8941bacac99f956948785571d
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Saturday, February 8,
This patch can also be viewed in the following repo:-
https://github.com/ashrafj/edk2-staging/commit/b83f0f959ba7608bd802c19f9a022fad9e5d01cc
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Saturday, February 8,
This patch can also be viewed in the following repo:-
https://github.com/ashrafj/edk2-staging/commit/27d11f3bbba23ff8b55d67da3cc50f8ee6029103
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Saturday, February 8,
This patch can also be viewed in the following repo:-
https://github.com/ashrafj/edk2-staging/commit/91e85bdb96600e72d5d7ab4d170089abcf1fe4fb
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Saturday, February 8,
This patch can also be viewed in the following repo:-
https://github.com/ashrafj/edk2-staging/commit/5c835eb3a75da8a65198ba255442e112f0970f39
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Saturday, February 8,
This patch can also be viewed in the following repo:-
https://github.com/ashrafj/edk2-staging/commit/8c06ec777429cde1bddf368b16a886b3083ec12c
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Saturday, February 8,
This patch can also be viewed in the following repo:-
https://github.com/ashrafj/edk2-staging/commit/9d9f47b271f2c8fe7f7fa2a72bc98db3c28b3312
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Saturday, February 8,
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2194
The code changes are made to enable the configuration of new PCI Express
feature Max_Payload_Size (MPS), which defines the data packet size for
the PCI transactions, as per the PCI Base Specification 4 Revision 1.
The code changes are made
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2313
The code changes are made to enable the configuration of PCI Express
feature Relax Ordering (OR), that enables the PCI function to initiate
requests if it does not require strong write ordering for its transact-
ions; as per the PCI Express
References:-
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
This code
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2313
The code changes are made; as per the PCI Express Base Specification 4
Revision 1; to enable the configuration of PCI Express feature Completion
Timeout (CTO), that enables the PCI function to wait on programmed dura-
tion for its
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2499
This code change handles two PCI Express features related to AtomicOp,
in compliance with the PCI Express Base SPecification 5:
(1) configuring PCI function as an AtomicOp Requester
(2) Enabling of Port Egress blocking depending on AtomicOp
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2500
This code change is to enable the common ASPM state for all the connected
devices, as per the PCI Express Base Specification 5, Revision 1.
This feature is not applicable to RCiEP, and to a vacant bridge device.
The device policy request
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2313
The code changes are made; as per the PCI Express Base Specification 4
Revision 1; to enable the configuration of PCI Express feature No-Snoop
(NS), that enables the PCI function to initiate requests if it does not
require hardware enforced
References:-
https://bugzilla.tianocore.org/show_bug.cgi?id=1954
https://bugzilla.tianocore.org/show_bug.cgi?id=2194
https://bugzilla.tianocore.org/show_bug.cgi?id=2313
https://bugzilla.tianocore.org/show_bug.cgi?id=2499
https://bugzilla.tianocore.org/show_bug.cgi?id=2500
This code
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2194
The code changes are made to enable the configuration of PCI Express
feature Max_Read_Req_Size (MRRS), which defines the memory read request
size for the PCI transactions, as per the PCI Base Specification 4
Revision 1.
The code changes are
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2500
This code change enforces the Link Control register CCC field as per the
following conditions:-
(1) When the Clock Configuration device policy for all the devices are
set to EFI_PCI_EXPRESS_CLK_CFG_AUTO:-
- Based on the Link Status
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2499
This code change enables the PCI Express feature LTR, in compliance
with the PCI Express Base Specification 5, as well as in accordance its
device policy, as follows:
(1) all the devices capability register needs to indicate that LTR mecha-
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2499
This code change enables the PCI Express feature Extended Tag, in
compliance with the PCI Express Base Specification 5, and uses the device
policy under the following conditions:
(1) As per the PCI Express Base Specification, all the devices
The PciBusDxe is enhanced to initialize 10 PCI Express features (patch
index 3 to 12).
All these PCI Express features attributes are defined based on the new
PCI Express Platform Protocol definition (as per its ECR draft version
0.8): https://bugzilla.tianocore.org/show_bug.cgi?id=1954.
For MPS,
This patch is also in the following repo for your review:-
https://github.com/ashrafj/edk2-staging/commit/cdcc078659a82536233c328c771507584235bcd0
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Thursday, February 6,
Signed-off-by: Ashraf Javeed
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Ray Ni
---
MdePkg/Include/Protocol/PciExpressPlatform.h | 13 -
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/MdePkg/Include/Protocol/PciExpressPlatform.h
Resending the previous change; and also in the following repo:-
https://github.com/ashrafj/edk2-staging/commit/dcc3bec4b0b40895834909500e3c82465693cadc
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Friday, January 10, 2
Signed-off-by: Ashraf Javeed
Cc: Michael D Kinney
Cc: Liming Gao
Cc: Ray Ni
---
---
MdePkg/Include/Protocol/PciExpressPlatform.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MdePkg/Include/Protocol/PciExpressPlatform.h
b/MdePkg/Include/Protocol/PciExpressPlatform.h
Hi Liming,
Here is the updated commit with its title / message corrected, in the following
edk2-staging repo:
https://github.com/ashrafj/edk2-staging/commit/532f2d87a895a1e7b6846ca19c9bbc02f8702a3a
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1954
Three interfaces added to PCI Express Platform Protocol:-
(1) GetDevicePolicy() -> to retrieve device-specific platform policies
(2) NotifyDeviceState() -> to notify platform about device PCI Express
configuration state
(3) GetPolicy()
Hi,
You can also review this patch into the below edk2-staging repo:-
https://github.com/ashrafj/edk2-staging/commit/84ec9f060bab7d5ec97b36367e87124820694934
Thanks
Ashraf
> -Original Message-
> From: devel@edk2.groups.io On Behalf Of Javeed,
> Ashraf
> Sent: Friday, Januar
BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=1954
Three interfaces added to PCI Express Platform Protocol:-
(1) GetDevicePolicy() -> to retrieve device-specific platform policies
(2) NotifyDeviceState() -> to notify platform about device PCI Express
configuration state
(3) GetPolicy()
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