Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)

[Wu, Hao A]

> -Original Message-
> From: Kinney, Michael D
> Sent: Wednesday, August 28, 2019 1:25 PM
> To: Wu, Hao A; Leif Lindholm; Laszlo Ersek; Kinney, Michael D
> Cc: devel@edk2.groups.io; Andrew Fish; Baptiste Gerondeau; Wang, Jian J;
> Feng, Bob C; Gao, Liming
> Subject: RE: [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)
> 
> Hao Wu,
> 
> Please provide a patch to BaseTools to restore the previous behavior.
> 
> We need that to review the complexity of the change to determine
> what to do.  Without that information today, the release date
> of this stable tag is at risk.


Hello Mike,

I confirmed with Bob that he is preparing a new BaseTools patch to restore
the previous behavior.

Best Regards,
Hao Wu


> 
> Mike
> 
> > -Original Message-
> > From: Wu, Hao A
> > Sent: Tuesday, August 27, 2019 6:40 PM
> > To: Leif Lindholm ; Laszlo
> > Ersek ; Kinney, Michael D
> > 
> > Cc: devel@edk2.groups.io; Andrew Fish ;
> > Baptiste Gerondeau ; Wang,
> > Jian J ; Feng, Bob C
> > ; Gao, Liming
> > 
> > Subject: RE: [PATCH 1/1] MdeModulePkg: fix !x86 builds
> > (more)
> >
> > > -Original Message-
> > > From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> > > Sent: Wednesday, August 28, 2019 4:59 AM
> > > To: Laszlo Ersek
> > > Cc: devel@edk2.groups.io; Andrew Fish; Kinney, Michael
> > D; Baptiste
> > > Gerondeau; Wang, Jian J; Wu, Hao A; Feng, Bob C; Gao,
> > Liming
> > > Subject: Re: [PATCH 1/1] MdeModulePkg: fix !x86 builds
> > (more)
> > >
> > > +Bob, Liming,
> > >
> > > On Tue, Aug 27, 2019 at 09:26:05PM +0200, Laszlo Ersek
> > wrote:
> > > > Hi Leif,
> > > >
> > > > On 08/27/19 14:43, Leif Lindholm wrote:
> > > > > Commit 4a1f6b85c184
> > > > > ("MdeModulePkg: add LockBoxNullLib for !IA32/X64 in
> > .dsc") added
> > > > > an ARM/AARCH64 resolution for LockBoxLib. However,
> > this failed to
> > > > > address the overrides provided for PEIM,
> > DXE_DRIVER,
> > > > > DXE_RUNTIME_DRIVER, DXE_SMM_DRIVER and UEFI_DRIVER,
> > so any
> > > modules
> > > > > of those classes still failed to build.
> > > > >
> > > > > Break these out properly into their own
> > LibraryClasses sections.
> > > > >
> > > > > Resolves BZ:
> > https://bugzilla.tianocore.org/show_bug.cgi?id=2134
> > > > >
> > > > > Signed-off-by: Leif Lindholm
> > 
> > > > > Reported-by: Baptiste Gerondeau
> > 
> > > > > Cc: Jian J Wang 
> > > > > Cc: Hao A Wu 
> > > > > ---
> > > > >
> > > > > I don't understand how the above would appear to
> > work back when I
> > > > > submitted the previous patch but not work now, but
> > I haven't dug
> > > > > into it deeper. Including the x86-specific
> > LockBoxLib in the
> > > > > .common section is however clearly not correct.
> > > >
> > > > I agree with you that the present situation is not
> > correct.
> > > >
> > > > According to:
> > > >
> > > >   https://edk2-docs.gitbooks.io/edk-ii-dsc-
> > >
> > specification/2_dsc_overview/26_[libraryclasses]_section_
> > processing.ht
> > > ml
> > > >
> > > > the library class resolutions take effect in the
> > following order
> > > > (entries near the top have higher priority):
> > > >
> > > > > 1.  associated with the INF file in
> > the
> > > > > [Components]
> > > section
> > > > > 2. [LibraryClasses.$(Arch).$(MODULE_TYPE),
> > > LibraryClasses.$(Arch).$(MODULE_TYPE)]
> > > > > 3. [LibraryClasses.$(Arch).$(MODULE_TYPE)]
> > > > > 4. [LibraryClasses.common.$(MODULE_TYPE)]
> > > > > 5. [LibraryClasses.$(Arch)]
> > > > > 6. [LibraryClasses.common] or [LibraryClasses]
> > > >
> > > > (Side comment 1: levels #2 and #3 look very similar;
> > I think the
> > > > difference is that #2 is supposed to be a multi-arch
> > and/or
> > > > multi-module-type section, while #3 is a single-arch
> > and
> > > > single-module-type section.)
> > > >
> > > > Commit 4a1f6b85c184 ("MdeModulePkg: add
> > LockBoxNullLib for !IA32/X64
> > > in
> > > > .dsc", 2019-03-27) provided a LockBoxLib resolution
> > at level #5:
> > >
> > > Yes.
> > >
> > > > > [LibraryClasses.ARM, LibraryClasses.AARCH64]
> > > >
> > > > However, the other LockBoxLib resolutions are at
> > level #4:
> > > >
> > > > > [LibraryClasses.common.PEIM]
> > > > > [LibraryClasses.common.DXE_DRIVER]
> > > > > [LibraryClasses.common.DXE_RUNTIME_DRIVER]
> > > > > [LibraryClasses.common.DXE_SMM_DRIVER]
> > > > > [LibraryClasses.common.UEFI_DRIVER]
> > > >
> > > > So the latter taking priority is actually specified
> > behavior.
> > >
> > > Hmm. That's not great.
> > > Anyway, I stopped being lazy and did a bisect.
> > >
> > > The culprit is
> > > e8449e1d8e3b ("BaseTools: Decouple AutoGen Objects"),
> > marked as
> > > resolving
> > https://bugzilla.tianocore.org/show_bug.cgi?id=1875.
> > >
> > > This also affects SignedCapsulePkg/SignedCapsulePkg.dsc
> > (although once
> > > addressed, AARCH64 also needs a NULL entry added for
> > > CompilerIntrinsicsLib.
> > >
> > > > (Side comment 2: EBC is in the same boat, from commit
> > cbcccd2c9d93
> > > > ("Update Code to pass EBC compiler", 2013-05-13):
> > > >
> > 

Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)

[Michael D Kinney]

Hao Wu,

Please provide a patch to BaseTools to restore the previous behavior.

We need that to review the complexity of the change to determine
what to do.  Without that information today, the release date 
of this stable tag is at risk.

Mike

> -Original Message-
> From: Wu, Hao A
> Sent: Tuesday, August 27, 2019 6:40 PM
> To: Leif Lindholm ; Laszlo
> Ersek ; Kinney, Michael D
> 
> Cc: devel@edk2.groups.io; Andrew Fish ;
> Baptiste Gerondeau ; Wang,
> Jian J ; Feng, Bob C
> ; Gao, Liming
> 
> Subject: RE: [PATCH 1/1] MdeModulePkg: fix !x86 builds
> (more)
> 
> > -Original Message-
> > From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> > Sent: Wednesday, August 28, 2019 4:59 AM
> > To: Laszlo Ersek
> > Cc: devel@edk2.groups.io; Andrew Fish; Kinney, Michael
> D; Baptiste
> > Gerondeau; Wang, Jian J; Wu, Hao A; Feng, Bob C; Gao,
> Liming
> > Subject: Re: [PATCH 1/1] MdeModulePkg: fix !x86 builds
> (more)
> >
> > +Bob, Liming,
> >
> > On Tue, Aug 27, 2019 at 09:26:05PM +0200, Laszlo Ersek
> wrote:
> > > Hi Leif,
> > >
> > > On 08/27/19 14:43, Leif Lindholm wrote:
> > > > Commit 4a1f6b85c184
> > > > ("MdeModulePkg: add LockBoxNullLib for !IA32/X64 in
> .dsc") added
> > > > an ARM/AARCH64 resolution for LockBoxLib. However,
> this failed to
> > > > address the overrides provided for PEIM,
> DXE_DRIVER,
> > > > DXE_RUNTIME_DRIVER, DXE_SMM_DRIVER and UEFI_DRIVER,
> so any
> > modules
> > > > of those classes still failed to build.
> > > >
> > > > Break these out properly into their own
> LibraryClasses sections.
> > > >
> > > > Resolves BZ:
> https://bugzilla.tianocore.org/show_bug.cgi?id=2134
> > > >
> > > > Signed-off-by: Leif Lindholm
> 
> > > > Reported-by: Baptiste Gerondeau
> 
> > > > Cc: Jian J Wang 
> > > > Cc: Hao A Wu 
> > > > ---
> > > >
> > > > I don't understand how the above would appear to
> work back when I
> > > > submitted the previous patch but not work now, but
> I haven't dug
> > > > into it deeper. Including the x86-specific
> LockBoxLib in the
> > > > .common section is however clearly not correct.
> > >
> > > I agree with you that the present situation is not
> correct.
> > >
> > > According to:
> > >
> > >   https://edk2-docs.gitbooks.io/edk-ii-dsc-
> >
> specification/2_dsc_overview/26_[libraryclasses]_section_
> processing.ht
> > ml
> > >
> > > the library class resolutions take effect in the
> following order
> > > (entries near the top have higher priority):
> > >
> > > > 1.  associated with the INF file in
> the
> > > > [Components]
> > section
> > > > 2. [LibraryClasses.$(Arch).$(MODULE_TYPE),
> > LibraryClasses.$(Arch).$(MODULE_TYPE)]
> > > > 3. [LibraryClasses.$(Arch).$(MODULE_TYPE)]
> > > > 4. [LibraryClasses.common.$(MODULE_TYPE)]
> > > > 5. [LibraryClasses.$(Arch)]
> > > > 6. [LibraryClasses.common] or [LibraryClasses]
> > >
> > > (Side comment 1: levels #2 and #3 look very similar;
> I think the
> > > difference is that #2 is supposed to be a multi-arch
> and/or
> > > multi-module-type section, while #3 is a single-arch
> and
> > > single-module-type section.)
> > >
> > > Commit 4a1f6b85c184 ("MdeModulePkg: add
> LockBoxNullLib for !IA32/X64
> > in
> > > .dsc", 2019-03-27) provided a LockBoxLib resolution
> at level #5:
> >
> > Yes.
> >
> > > > [LibraryClasses.ARM, LibraryClasses.AARCH64]
> > >
> > > However, the other LockBoxLib resolutions are at
> level #4:
> > >
> > > > [LibraryClasses.common.PEIM]
> > > > [LibraryClasses.common.DXE_DRIVER]
> > > > [LibraryClasses.common.DXE_RUNTIME_DRIVER]
> > > > [LibraryClasses.common.DXE_SMM_DRIVER]
> > > > [LibraryClasses.common.UEFI_DRIVER]
> > >
> > > So the latter taking priority is actually specified
> behavior.
> >
> > Hmm. That's not great.
> > Anyway, I stopped being lazy and did a bisect.
> >
> > The culprit is
> > e8449e1d8e3b ("BaseTools: Decouple AutoGen Objects"),
> marked as
> > resolving
> https://bugzilla.tianocore.org/show_bug.cgi?id=1875.
> >
> > This also affects SignedCapsulePkg/SignedCapsulePkg.dsc
> (although once
> > addressed, AARCH64 also needs a NULL entry added for
> > CompilerIntrinsicsLib.
> >
> > > (Side comment 2: EBC is in the same boat, from commit
> cbcccd2c9d93
> > > ("Update Code to pass EBC compiler", 2013-05-13):
> > >
> > > > [LibraryClasses.EBC]
> > > >
> > > >
> LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNul
> lLib.inf
> > > )
> > >
> > > As to why this breakage was not exposed right at
> commit 4a1f6b85c184
> > > -- I have no idea. Perhaps it was hidden by a
> BaseTools issue that
> > > has been fixed meanwhile.
> >
> > Yes.
> > But it is also a fundamental change in tool behaviour
> introduced on 9
> > August. I am really uncomfortable about this making it
> into the
> > release this week - but I also believe this is the
> foundation for the
> > multiprocess autogen.
> >
> > Since you have very helpfully analyzed *what* changed
> ... would the
> > better "fix" for 2019.08 be to intentionally break the
> new code to
> > conform to the old behaviour - and then 

Re: [edk2-devel] [edk2-platforms][PATCH V5 2/2] WhiskeylakeOpenBoardPkg: Fix GCC Build Failures

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 

> -Original Message-
> From: Kubacki, Michael A
> Sent: Wednesday, August 28, 2019 12:17 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Gao, Liming 
> Subject: [edk2-platforms][PATCH V5 2/2] WhiskeylakeOpenBoardPkg: Fix GCC
> Build Failures
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2110
> 
> Fixes build failures on GCC7.3.0. Tested on Ubunutu 18.04.1 LTS.
> 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Liming Gao 
> Signed-off-by: Michael Kubacki 
> ---
>  Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> |   6 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiH
> daVerbTableLib.inf |   1 +
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/PeiBoardInitPostMemLib.inf   |   8 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/PeiMultiBoardInitPostMemLib.inf  |   2 +
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/PeiMultiBoardInitPreMemLib.inf   |  12 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.
> h |   2 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Whisk
> eylakeURvpId.h   |  12 -
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/BoardFunc.h  |   2 +
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/PeiWhiskeylakeURvpInitLib.h  |  41 -
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/WhiskeylakeURvpInit.h|  41 +
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI
> nitLib/PeiFspCpuPolicyInitLib.c   |   4 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/Ba
> seGpioExpanderLib.c |   6 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/{Pch
> HdaVerbTables.h => PchHdaVerbTables.c} | 963
> +---
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiH
> daVerbTableLib.c   |   7 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib
> /PeiPchPolicyUpdate.c|   6 -
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib
> /PeiSaPolicyUpdatePreMem.c   |  15 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.
> c   |   4 -
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA
> cpiLib/SmmMultiBoardAcpiSupportLib.c|   2 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardA
> cpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c|   2 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/BoardFuncInit.c  |   1 -
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/BoardFuncInitPreMem.c|   1 -
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/BoardPchInitPreMemLib.c  |  12 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/BoardSaInitPreMemLib.c   |   6 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/{GpioTableDefault.h => GpioTableDefault.c}   |  16 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/{GpioTableWhlUDdr4.h => GpioTableWhiskeylakeUDdr4Rvp.c}  |  20 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/{GpioTableWhlUDdr4PreMem.h => GpioTableWhlUDdr4PreMem.c} |
> 21 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/PeiMultiBoardInitPostMemLib.c|   2 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/PeiMultiBoardInitPreMemLib.c |   2 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/PeiWhiskeylakeURvpDetect.c   |   2 +-
> 
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardI
> nitLib/PeiWhiskeylakeURvpInitPostMemLib.c   |  57 +-
> 
> 

Re: [edk2-devel] [edk2-platforms][PATCH V5 1/2] CoffeelakeSiliconPkg: Fix GCC Build Failures

[Chiu, Chasel]

Reviewed-by: Chasel Chiu 

> -Original Message-
> From: Kubacki, Michael A
> Sent: Wednesday, August 28, 2019 12:17 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Chaganty, Rangasai V
> 
> Subject: [edk2-platforms][PATCH V5 1/2] CoffeelakeSiliconPkg: Fix GCC Build
> Failures
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2124
> 
> Fixes build failures on GCC7.3.0. Tested on Ubuntu 18.04.1 LTS.
> 
> Cc: Chasel Chiu 
> Cc: Sai Chaganty 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h
> | 2 ++
>  Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h
> | 1 +
> 
> Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLi
> b.c | 2 --
>  Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c
> | 1 +
>  4 files changed, 4 insertions(+), 2 deletions(-)
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfi
> g.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfi
> g.h
> index a810d4f1fc..e2c8730f38 100644
> ---
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfi
> g.h
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudio
> +++ Config.h
> @@ -9,7 +9,9 @@
>  #ifndef _HDAUDIO_CONFIG_H_
>  #define _HDAUDIO_CONFIG_H_
> 
> +#include 
>  #include 
> +#include 
> 
>  #define HDAUDIO_PREMEM_CONFIG_REVISION 1  #define
> HDAUDIO_CONFIG_REVISION 2 diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h
> index 25def24fca..ff76e7c60f 100644
> --- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h
> @@ -11,6 +11,7 @@
>  #define _GPIO_LIB_H_
> 
>  #include 
> +#include 
> 
>  #define GPIO_NAME_LENGTH_MAX  32
> 
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolic
> yLib.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolic
> yLib.c
> index 2a1da20667..ece0be8158 100644
> ---
> a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolic
> yLib.c
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/Pei
> +++ PchPolicyLib.c
> @@ -353,10 +353,8 @@ LoadLanConfigDefault (
>)
>  {
>PCH_LAN_CONFIG  *LanConfig;
> -  UINT16  LpcDid;
> 
>LanConfig = ConfigBlockPointer;
> -  LpcDid= PchGetLpcDid ();
> 
>DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Name = %g\n",
> >Header.GuidHob.Name));
>DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Header.HobLength =
> 0x%x\n", LanConfig->Header.GuidHob.Header.HobLength));
> diff --git
> a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c
> b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c
> index d646e60618..e6980f9a65 100644
> --- a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c
> +++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDx
> +++ e.c
> @@ -41,6 +41,7 @@ SaInitEntryPointDxe (
>SaInitEntryPoint ();
> 
>Status = SaAcpiInit (ImageHandle);
> +  ASSERT_EFI_ERROR (Status);
> 
>///
>/// Create PCI Enumeration Completed callback for SA
> --
> 2.16.2.windows.1


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[edk2-devel] [edk2-platforms][PATCH V5 2/2] WhiskeylakeOpenBoardPkg: Fix GCC Build Failures

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2110

Fixes build failures on GCC7.3.0. Tested on Ubunutu 18.04.1 LTS.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Signed-off-by: Michael Kubacki 
---
 Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
  |   6 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
 |   1 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
   |   8 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
  |   2 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
   |  12 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h   
  |   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h
   |  12 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h
  |   2 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h
  |  41 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h
|  41 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
   |   4 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c
 |   6 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/{PchHdaVerbTables.h
 => PchHdaVerbTables.c} | 963 +---
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.c
   |   7 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
|   6 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
   |  15 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c 
  |   4 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
|   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c
|   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c
  |   1 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c
|   1 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
  |  12 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
   |   6 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/{GpioTableDefault.h
 => GpioTableDefault.c}   |  16 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/{GpioTableWhlUDdr4.h
 => GpioTableWhiskeylakeUDdr4Rvp.c}  |  20 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/{GpioTableWhlUDdr4PreMem.h
 => GpioTableWhlUDdr4PreMem.c} |  21 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
|   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
 |   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c
   |   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
   |  57 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
|  82 +-
 31 files changed, 179 insertions(+), 1179 deletions(-)

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
index 9d56f0e841..8de48077f0 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+++ 

[edk2-devel] [edk2-platforms][PATCH V5 0/2] Fix Whiskey Lake GCC Build Failures

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2124
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2110

Fixes GCC build failures in WhiskeylakeOpenBoardPkg and CoffeelakeSiliconPkg
(silicon package used by WhiskeylakeOpenBoardPkg).

V5 Changes:
 * Amended a change missed in V4 to remove the return value from 
BoardConfigInit()

V4 Changes:
 * Removed return value from BoardConfigInitPreMem()
 * Removed return value from BoardConfigInit()

V3 Changes:
 * WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/
   PeiWhiskeylakeURvpInitPreMemLib.c - BoardConfigInitPreMem()
   1. Returns the last failing error code from the function
   2. Updates the function comment accuracy and declaration for style 
guidelines.
 * WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/
   PeiWhiskeylakeURvpInitPostMemLib.c - BoardConfigInit()
   1. Returns the last failing error code from the function
   2. Updates the function comment accuracy and declaration for style 
guidelines.

V2 Changes:
 * Breaks changes into a dedicated patch for each package.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Signed-off-by: Michael Kubacki 

Michael Kubacki (2):
  CoffeelakeSiliconPkg: Fix GCC Build Failures
  WhiskeylakeOpenBoardPkg: Fix GCC Build Failures

 Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
  |   6 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
 |   1 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
   |   8 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
  |   2 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
   |  12 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h   
  |   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h
   |  12 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h
  |   2 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h
  |  41 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h
|  41 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h 
  |   2 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h   
  |   1 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
   |   4 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c
 |   6 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/{PchHdaVerbTables.h
 => PchHdaVerbTables.c} | 963 +---
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.c
   |   7 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
|   6 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
   |  15 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c 
  |   4 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
|   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c
|   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c
  |   1 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c
|   1 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
  |  12 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
   |   6 +-
 

[edk2-devel] [edk2-platforms][PATCH V5 1/2] CoffeelakeSiliconPkg: Fix GCC Build Failures

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2124

Fixes build failures on GCC7.3.0. Tested on Ubuntu 18.04.1 LTS.

Cc: Chasel Chiu 
Cc: Sai Chaganty 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h 
  | 2 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h   
  | 1 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.c
 | 2 --
 Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c  
  | 1 +
 4 files changed, 4 insertions(+), 2 deletions(-)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h
index a810d4f1fc..e2c8730f38 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h
@@ -9,7 +9,9 @@
 #ifndef _HDAUDIO_CONFIG_H_
 #define _HDAUDIO_CONFIG_H_
 
+#include 
 #include 
+#include 
 
 #define HDAUDIO_PREMEM_CONFIG_REVISION 1
 #define HDAUDIO_CONFIG_REVISION 2
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h
index 25def24fca..ff76e7c60f 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h
@@ -11,6 +11,7 @@
 #define _GPIO_LIB_H_
 
 #include 
+#include 
 
 #define GPIO_NAME_LENGTH_MAX  32
 
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.c
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.c
index 2a1da20667..ece0be8158 100644
--- 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.c
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.c
@@ -353,10 +353,8 @@ LoadLanConfigDefault (
   )
 {
   PCH_LAN_CONFIG  *LanConfig;
-  UINT16  LpcDid;
 
   LanConfig = ConfigBlockPointer;
-  LpcDid= PchGetLpcDid ();
 
   DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Name = %g\n", 
>Header.GuidHob.Name));
   DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Header.HobLength = 0x%x\n", 
LanConfig->Header.GuidHob.Header.HobLength));
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c 
b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c
index d646e60618..e6980f9a65 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c
@@ -41,6 +41,7 @@ SaInitEntryPointDxe (
   SaInitEntryPoint ();
 
   Status = SaAcpiInit (ImageHandle);
+  ASSERT_EFI_ERROR (Status);
 
   ///
   /// Create PCI Enumeration Completed callback for SA
-- 
2.16.2.windows.1


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[edk2-devel] [edk2-platforms][PATCH V4 1/2] CoffeelakeSiliconPkg: Fix GCC Build Failures

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2124

Fixes build failures on GCC7.3.0. Tested on Ubuntu 18.04.1 LTS.

Cc: Chasel Chiu 
Cc: Sai Chaganty 
Signed-off-by: Michael Kubacki 
---
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h 
  | 2 ++
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h   
  | 1 +
 
Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.c
 | 2 --
 Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c  
  | 1 +
 4 files changed, 4 insertions(+), 2 deletions(-)

diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h
index a810d4f1fc..e2c8730f38 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h
@@ -9,7 +9,9 @@
 #ifndef _HDAUDIO_CONFIG_H_
 #define _HDAUDIO_CONFIG_H_
 
+#include 
 #include 
+#include 
 
 #define HDAUDIO_PREMEM_CONFIG_REVISION 1
 #define HDAUDIO_CONFIG_REVISION 2
diff --git a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h
index 25def24fca..ff76e7c60f 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h
@@ -11,6 +11,7 @@
 #define _GPIO_LIB_H_
 
 #include 
+#include 
 
 #define GPIO_NAME_LENGTH_MAX  32
 
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.c
 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.c
index 2a1da20667..ece0be8158 100644
--- 
a/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.c
+++ 
b/Silicon/Intel/CoffeelakeSiliconPkg/Pch/Library/PeiPchPolicyLib/PeiPchPolicyLib.c
@@ -353,10 +353,8 @@ LoadLanConfigDefault (
   )
 {
   PCH_LAN_CONFIG  *LanConfig;
-  UINT16  LpcDid;
 
   LanConfig = ConfigBlockPointer;
-  LpcDid= PchGetLpcDid ();
 
   DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Name = %g\n", 
>Header.GuidHob.Name));
   DEBUG ((DEBUG_INFO, "LanConfig->Header.GuidHob.Header.HobLength = 0x%x\n", 
LanConfig->Header.GuidHob.Header.HobLength));
diff --git 
a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c 
b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c
index d646e60618..e6980f9a65 100644
--- a/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c
+++ b/Silicon/Intel/CoffeelakeSiliconPkg/SystemAgent/SaInit/Dxe/SaInitDxe.c
@@ -41,6 +41,7 @@ SaInitEntryPointDxe (
   SaInitEntryPoint ();
 
   Status = SaAcpiInit (ImageHandle);
+  ASSERT_EFI_ERROR (Status);
 
   ///
   /// Create PCI Enumeration Completed callback for SA
-- 
2.16.2.windows.1


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[edk2-devel] [edk2-platforms][PATCH V4 2/2] WhiskeylakeOpenBoardPkg: Fix GCC Build Failures

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2110

Fixes build failures on GCC7.3.0. Tested on Ubunutu 18.04.1 LTS.

Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Signed-off-by: Michael Kubacki 
---
 Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
  |   6 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
 |   1 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
   |   8 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
  |   2 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
   |  12 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h   
  |   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h
   |  12 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h
  |   2 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h
  |  41 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h
|  41 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
   |   4 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c
 |   6 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/{PchHdaVerbTables.h
 => PchHdaVerbTables.c} | 963 +---
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.c
   |   7 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
|   6 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
   |  15 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c 
  |   4 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
|   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c
|   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c
  |   1 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c
|   1 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
  |  12 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
   |   6 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/{GpioTableDefault.h
 => GpioTableDefault.c}   |  16 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/{GpioTableWhlUDdr4.h
 => GpioTableWhiskeylakeUDdr4Rvp.c}  |  20 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/{GpioTableWhlUDdr4PreMem.h
 => GpioTableWhlUDdr4PreMem.c} |  21 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
|   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
 |   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpDetect.c
   |   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPostMemLib.c
   |  55 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitPreMemLib.c
|  82 +-
 31 files changed, 178 insertions(+), 1178 deletions(-)

diff --git a/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec 
b/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
index 9d56f0e841..8de48077f0 100644
--- a/Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
+++ 

[edk2-devel] [edk2-platforms][PATCH V4 0/2] Fix Whiskey Lake GCC Build Failures

[Kubacki, Michael A]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2124
REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2110

Fixes GCC build failures in WhiskeylakeOpenBoardPkg and CoffeelakeSiliconPkg
(silicon package used by WhiskeylakeOpenBoardPkg).

V4 Changes:
 * Removed return value from BoardConfigInitPreMem().
 * Removed return value from BoardConfigInit()

V3 Changes:
 * WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/
   PeiWhiskeylakeURvpInitPreMemLib.c - BoardConfigInitPreMem()
   1. Returns the last failing error code from the function
   2. Updates the function comment accuracy and declaration for style 
guidelines.
 * WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/
   PeiWhiskeylakeURvpInitPostMemLib.c - BoardConfigInit()
   1. Returns the last failing error code from the function
   2. Updates the function comment accuracy and declaration for style 
guidelines.

V2 Changes:
 * Breaks changes into a dedicated patch for each package.

Cc: Sai Chaganty 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Liming Gao 
Signed-off-by: Michael Kubacki 

Michael Kubacki (2):
  CoffeelakeSiliconPkg: Fix GCC Build Failures
  WhiskeylakeOpenBoardPkg: Fix GCC Build Failures

 Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
  |   6 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.inf
 |   1 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
   |   8 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
  |   2 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
   |  12 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTable.h   
  |   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/WhiskeylakeURvpId.h
   |  12 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFunc.h
  |   2 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/PeiWhiskeylakeURvpInitLib.h
  |  41 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/WhiskeylakeURvpInit.h
|  41 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/ConfigBlock/HdAudioConfig.h 
  |   2 +
 Silicon/Intel/CoffeelakeSiliconPkg/Pch/Include/Library/GpioLib.h   
  |   1 +
 
Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c
   |   4 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/BaseGpioExpanderLib.c
 |   6 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/{PchHdaVerbTables.h
 => PchHdaVerbTables.c} | 963 +---
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/PeiHdaVerbTableLib.c
   |   7 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiPchPolicyUpdate.c
|   6 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLib/PeiSaPolicyUpdatePreMem.c
   |  15 +-
 Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib.c 
  |   4 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
|   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardAcpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c
|   2 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInit.c
  |   1 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardFuncInitPreMem.c
|   1 -
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
  |  12 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
   |   6 +-
 
Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/BoardInitLib/{GpioTableDefault.h
 => GpioTableDefault.c}   |  16 +-
 

Re: [edk2-devel] [PATCH 0/2] move PcdRealTimeClockUpdateTimeout from MdeModulePkg to PcAtChipsetPkg

[Wu, Hao A]

> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Zeng, Star
> Sent: Wednesday, August 28, 2019 8:48 AM
> To: devel@edk2.groups.io; Ni, Ray
> Cc: Zeng, Star
> Subject: Re: [edk2-devel] [PATCH 0/2] move
> PcdRealTimeClockUpdateTimeout from MdeModulePkg to PcAtChipsetPkg
> 
> Both XXXPkg.uni need to be updated as the PCD movement.


Agree.


> With that, Reviewed-by: Star Zeng 


Found that the PCD was introduced by commit f8ea30263c. At that time, the
PcatRealTimeClockRuntimeDxe driver was still in MdeModulePkg. Then commit
345e5a6556 moved the driver to PcAtChipsetPkg but forgot to move the PCD.

With Star's comment addressed, for the series:
Reviewed-by: Hao A Wu 

Also, please help to hold the patch after the upcoming stable tag, thanks.

Best Regards,
Hao Wu


> 
> Thanks,
> Star
> 
> > -Original Message-
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> Ni,
> > Ray
> > Sent: Wednesday, August 28, 2019 7:27 AM
> > To: devel@edk2.groups.io
> > Subject: [edk2-devel] [PATCH 0/2] move PcdRealTimeClockUpdateTimeout
> > from MdeModulePkg to PcAtChipsetPkg
> >
> >
> > Ray Ni (2):
> >   PcAtChipsetPkg: add PcdRealTimeClockUpdateTimeout
> >   MdeModulePkg: Remove PcdRealTimeClockUpdateTimeout
> >
> >  MdeModulePkg/MdeModulePkg.dec   | 4 
> >  PcAtChipsetPkg/PcAtChipsetPkg.dec   | 6 +-
> >  .../PcatRealTimeClockRuntimeDxe.inf | 5 ++---
> >  3 files changed, 7 insertions(+), 8 deletions(-)
> >
> > --
> > 2.21.0.windows.1
> >
> >
> >
> 
> 
> 


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Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)

[Wu, Hao A]

> -Original Message-
> From: Leif Lindholm [mailto:leif.lindh...@linaro.org]
> Sent: Wednesday, August 28, 2019 4:59 AM
> To: Laszlo Ersek
> Cc: devel@edk2.groups.io; Andrew Fish; Kinney, Michael D; Baptiste
> Gerondeau; Wang, Jian J; Wu, Hao A; Feng, Bob C; Gao, Liming
> Subject: Re: [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)
> 
> +Bob, Liming,
> 
> On Tue, Aug 27, 2019 at 09:26:05PM +0200, Laszlo Ersek wrote:
> > Hi Leif,
> >
> > On 08/27/19 14:43, Leif Lindholm wrote:
> > > Commit 4a1f6b85c184
> > > ("MdeModulePkg: add LockBoxNullLib for !IA32/X64 in .dsc")
> > > added an ARM/AARCH64 resolution for LockBoxLib. However, this failed
> > > to address the overrides provided for PEIM, DXE_DRIVER,
> > > DXE_RUNTIME_DRIVER, DXE_SMM_DRIVER and UEFI_DRIVER, so any
> modules
> > > of those classes still failed to build.
> > >
> > > Break these out properly into their own LibraryClasses sections.
> > >
> > > Resolves BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2134
> > >
> > > Signed-off-by: Leif Lindholm 
> > > Reported-by: Baptiste Gerondeau 
> > > Cc: Jian J Wang 
> > > Cc: Hao A Wu 
> > > ---
> > >
> > > I don't understand how the above would appear to work back when I
> > > submitted the previous patch but not work now, but I haven't dug
> > > into it deeper. Including the x86-specific LockBoxLib in the
> > > .common section is however clearly not correct.
> >
> > I agree with you that the present situation is not correct.
> >
> > According to:
> >
> >   https://edk2-docs.gitbooks.io/edk-ii-dsc-
> specification/2_dsc_overview/26_[libraryclasses]_section_processing.html
> >
> > the library class resolutions take effect in the following order
> > (entries near the top have higher priority):
> >
> > > 1.  associated with the INF file in the [Components]
> section
> > > 2. [LibraryClasses.$(Arch).$(MODULE_TYPE),
> LibraryClasses.$(Arch).$(MODULE_TYPE)]
> > > 3. [LibraryClasses.$(Arch).$(MODULE_TYPE)]
> > > 4. [LibraryClasses.common.$(MODULE_TYPE)]
> > > 5. [LibraryClasses.$(Arch)]
> > > 6. [LibraryClasses.common] or [LibraryClasses]
> >
> > (Side comment 1: levels #2 and #3 look very similar; I think the
> > difference is that #2 is supposed to be a multi-arch and/or
> > multi-module-type section, while #3 is a single-arch and
> > single-module-type section.)
> >
> > Commit 4a1f6b85c184 ("MdeModulePkg: add LockBoxNullLib for !IA32/X64
> in
> > .dsc", 2019-03-27) provided a LockBoxLib resolution at level #5:
> 
> Yes.
> 
> > > [LibraryClasses.ARM, LibraryClasses.AARCH64]
> >
> > However, the other LockBoxLib resolutions are at level #4:
> >
> > > [LibraryClasses.common.PEIM]
> > > [LibraryClasses.common.DXE_DRIVER]
> > > [LibraryClasses.common.DXE_RUNTIME_DRIVER]
> > > [LibraryClasses.common.DXE_SMM_DRIVER]
> > > [LibraryClasses.common.UEFI_DRIVER]
> >
> > So the latter taking priority is actually specified behavior.
> 
> Hmm. That's not great.
> Anyway, I stopped being lazy and did a bisect.
> 
> The culprit is
> e8449e1d8e3b ("BaseTools: Decouple AutoGen Objects"), marked as
> resolving https://bugzilla.tianocore.org/show_bug.cgi?id=1875.
> 
> This also affects SignedCapsulePkg/SignedCapsulePkg.dsc (although once
> addressed, AARCH64 also needs a NULL entry added for
> CompilerIntrinsicsLib.
> 
> > (Side comment 2: EBC is in the same boat, from commit cbcccd2c9d93
> > ("Update Code to pass EBC compiler", 2013-05-13):
> >
> > > [LibraryClasses.EBC]
> > >   LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
> > )
> >
> > As to why this breakage was not exposed right at commit 4a1f6b85c184 --
> > I have no idea. Perhaps it was hidden by a BaseTools issue that has been
> > fixed meanwhile.
> 
> Yes.
> But it is also a fundamental change in tool behaviour introduced on 9
> August. I am really uncomfortable about this making it into the
> release this week - but I also believe this is the foundation for the
> multiprocess autogen.
> 
> Since you have very helpfully analyzed *what* changed ... would the
> better "fix" for 2019.08 be to intentionally break the new code to
> conform to the old behaviour - and then revert that patch after the
> tag?
> 
> If we do that, this patch could then wait and indeed be merged as part
> of the same set.
> 
> > On 08/27/19 14:43, Leif Lindholm wrote:
> > > I think a fix for this issue needs to go into 2019.08,
> >
> > I agree the problem should be fixed in 2019.08 -- taking your word that
> > commit 4a1f6b85c184 *appeared* to fix the MdeModulePkg.dsc build for
> > ARM/AARCH64, we now have a regression since that commit (dated
> > 2019-03-27).
> >
> > > but if someone has a prettier suggestion, I am not wedded to this one.
> >
> > I think this is good enough. The lib class resolutions are raised to
> > level #2, but they will no longer match ARM / AARCH64, so your level#5
> > addition from commit 4a1f6b85c184 will take effect.
> >
> > >
> > >  MdeModulePkg/MdeModulePkg.dsc | 16 +---
> > >  1 file changed, 13 insertions(+), 3 

Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)

[Bob Feng]

I'll work on this Basetools regression issue today.

Thanks,
Bob

-Original Message-
From: Kinney, Michael D 
Sent: Wednesday, August 28, 2019 5:27 AM
To: devel@edk2.groups.io; leif.lindh...@linaro.org; Laszlo Ersek 
; Kinney, Michael D 
Cc: Andrew Fish ; Baptiste Gerondeau 
; Wang, Jian J ; Wu, Hao 
A ; Feng, Bob C ; Gao, Liming 

Subject: RE: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)

Leif,

Looking at the DSC Spec in looks like the priority change from Aug 9 was to 
invert the priority 4 and priority 5 items:

1.  associated with the INF file in the [Components] section 2. 
[LibraryClasses.$(Arch).$(MODULE_TYPE), LibraryClasses.$(Arch).$(MODULE_TYPE)]
3. [LibraryClasses.$(Arch).$(MODULE_TYPE)]
4. [LibraryClasses.common.$(MODULE_TYPE)]
5. [LibraryClasses.$(Arch)]
6. [LibraryClasses.common] or [LibraryClasses]

If BaseTools were updated to make (5) higher priority than (4), then the 
previous behavior would be restored and no DSC file changes would be required.  
This means an arch specific mapping for all module types is higher priority 
than a module specific mapping for all archs.

We can update DSC Spec to match the behavior that has been implemented for a 
long time.

Mike

> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of 
> Leif Lindholm
> Sent: Tuesday, August 27, 2019 1:59 PM
> To: Laszlo Ersek 
> Cc: devel@edk2.groups.io; Andrew Fish ; Kinney, 
> Michael D ; Baptiste Gerondeau 
> ; Wang, Jian J ; 
> Wu, Hao A ; Feng, Bob C ; 
> Gao, Liming 
> Subject: Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix
> !x86 builds (more)
> 
> +Bob, Liming,
> 
> On Tue, Aug 27, 2019 at 09:26:05PM +0200, Laszlo Ersek
> wrote:
> > Hi Leif,
> >
> > On 08/27/19 14:43, Leif Lindholm wrote:
> > > Commit 4a1f6b85c184
> > > ("MdeModulePkg: add LockBoxNullLib for !IA32/X64 in
> .dsc") added an
> > > ARM/AARCH64 resolution for LockBoxLib. However, this
> failed to
> > > address the overrides provided for PEIM, DXE_DRIVER, 
> > > DXE_RUNTIME_DRIVER, DXE_SMM_DRIVER and UEFI_DRIVER,
> so any modules
> > > of those classes still failed to build.
> > >
> > > Break these out properly into their own
> LibraryClasses sections.
> > >
> > > Resolves BZ:
> https://bugzilla.tianocore.org/show_bug.cgi?id=2134
> > >
> > > Signed-off-by: Leif Lindholm
> 
> > > Reported-by: Baptiste Gerondeau
> 
> > > Cc: Jian J Wang 
> > > Cc: Hao A Wu 
> > > ---
> > >
> > > I don't understand how the above would appear to
> work back when I
> > > submitted the previous patch but not work now, but I
> haven't dug
> > > into it deeper. Including the x86-specific
> LockBoxLib in the .common
> > > section is however clearly not correct.
> >
> > I agree with you that the present situation is not
> correct.
> >
> > According to:
> >
> >
> > https://edk2-docs.gitbooks.io/edk-ii-dsc-
> specification/2_dsc_overview/
> > 26_[libraryclasses]_section_processing.html
> >
> > the library class resolutions take effect in the
> following order
> > (entries near the top have higher priority):
> >
> > > 1.  associated with the INF file in
> the [Components]
> > > section 2. [LibraryClasses.$(Arch).$(MODULE_TYPE),
> > > LibraryClasses.$(Arch).$(MODULE_TYPE)]
> > > 3. [LibraryClasses.$(Arch).$(MODULE_TYPE)]
> > > 4. [LibraryClasses.common.$(MODULE_TYPE)]
> > > 5. [LibraryClasses.$(Arch)]
> > > 6. [LibraryClasses.common] or [LibraryClasses]
> >
> > (Side comment 1: levels #2 and #3 look very similar; I
> think the
> > difference is that #2 is supposed to be a multi-arch
> and/or
> > multi-module-type section, while #3 is a single-arch
> and
> > single-module-type section.)
> >
> > Commit 4a1f6b85c184 ("MdeModulePkg: add LockBoxNullLib
> for !IA32/X64
> > in .dsc", 2019-03-27) provided a LockBoxLib resolution
> at level #5:
> 
> Yes.
> 
> > > [LibraryClasses.ARM, LibraryClasses.AARCH64]
> >
> > However, the other LockBoxLib resolutions are at level
> #4:
> >
> > > [LibraryClasses.common.PEIM]
> > > [LibraryClasses.common.DXE_DRIVER]
> > > [LibraryClasses.common.DXE_RUNTIME_DRIVER]
> > > [LibraryClasses.common.DXE_SMM_DRIVER]
> > > [LibraryClasses.common.UEFI_DRIVER]
> >
> > So the latter taking priority is actually specified
> behavior.
> 
> Hmm. That's not great.
> Anyway, I stopped being lazy and did a bisect.
> 
> The culprit is
> e8449e1d8e3b ("BaseTools: Decouple AutoGen Objects"), marked as 
> resolving https://bugzilla.tianocore.org/show_bug.cgi?id=1875.
> 
> This also affects SignedCapsulePkg/SignedCapsulePkg.dsc
> (although once addressed, AARCH64 also needs a NULL entry added for 
> CompilerIntrinsicsLib.
> 
> > (Side comment 2: EBC is in the same boat, from commit
> cbcccd2c9d93
> > ("Update Code to pass EBC compiler", 2013-05-13):
> >
> > > [LibraryClasses.EBC]
> > >
> LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNu
> llLib.inf
> > )
> >
> > As to why this breakage was not exposed right at
> commit 4a1f6b85c184
> > -- I have no idea. Perhaps it was hidden by a
> BaseTools issue 

Re: [edk2-devel] [PATCH 0/2] move PcdRealTimeClockUpdateTimeout from MdeModulePkg to PcAtChipsetPkg

[Zeng, Star]

Both XXXPkg.uni need to be updated as the PCD movement.
With that, Reviewed-by: Star Zeng 

Thanks,
Star

> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of Ni,
> Ray
> Sent: Wednesday, August 28, 2019 7:27 AM
> To: devel@edk2.groups.io
> Subject: [edk2-devel] [PATCH 0/2] move PcdRealTimeClockUpdateTimeout
> from MdeModulePkg to PcAtChipsetPkg
> 
> 
> Ray Ni (2):
>   PcAtChipsetPkg: add PcdRealTimeClockUpdateTimeout
>   MdeModulePkg: Remove PcdRealTimeClockUpdateTimeout
> 
>  MdeModulePkg/MdeModulePkg.dec   | 4 
>  PcAtChipsetPkg/PcAtChipsetPkg.dec   | 6 +-
>  .../PcatRealTimeClockRuntimeDxe.inf | 5 ++---
>  3 files changed, 7 insertions(+), 8 deletions(-)
> 
> --
> 2.21.0.windows.1
> 
> 
> 


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Re: [edk2-devel] [PATCH] IntelFsp2Pkg/FspSecCore: Remove unneeded MdeModulePkg dependency

[Zeng, Star]

Reviewed-by: Star Zeng 

> -Original Message-
> From: Ni, Ray
> Sent: Wednesday, August 28, 2019 6:41 AM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star 
> Subject: [PATCH] IntelFsp2Pkg/FspSecCore: Remove unneeded
> MdeModulePkg dependency
> 
> Signed-off-by: Ray Ni 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Star Zeng 
> ---
>  IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 1 -
> IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf | 1 -
> IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf | 1 -
>  3 files changed, 3 deletions(-)
> 
> diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
> b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
> index 571ed9bc44..25f2a109ab 100644
> --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
> +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
> @@ -40,7 +40,6 @@ [Binaries.Ia32]
> 
>  [Packages]
>MdePkg/MdePkg.dec
> -  MdeModulePkg/MdeModulePkg.dec
>IntelFsp2Pkg/IntelFsp2Pkg.dec
> 
>  [LibraryClasses]
> diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
> b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
> index 17924b118c..1d9c2554d1 100644
> --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
> +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
> @@ -35,7 +35,6 @@ [Binaries.Ia32]
> 
>  [Packages]
>MdePkg/MdePkg.dec
> -  MdeModulePkg/MdeModulePkg.dec
>IntelFsp2Pkg/IntelFsp2Pkg.dec
> 
>  [LibraryClasses]
> diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
> b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
> index e66ea4593b..6f65e69e77 100644
> --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
> +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
> @@ -34,7 +34,6 @@ [Binaries.Ia32]
> 
>  [Packages]
>MdePkg/MdePkg.dec
> -  MdeModulePkg/MdeModulePkg.dec
>IntelFsp2Pkg/IntelFsp2Pkg.dec
> 
>  [LibraryClasses]
> --
> 2.21.0.windows.1


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[edk2-devel] [edk2-non-osi PATCH v2 0/1] Add UNDI ROM for SIMICS QSP Platform

[David Wei]

Add UNDI option ROM to provide the support for SIMICS quick start platform.
it uses X58/ICH10 and emulated by SIMICS model.

Different from V1: Use UndiDxe.inf instead of Binary file

David Wei (1):
  SimicsICH10SiliconBinPkg:  Add UNDI ROM for SIMICS QSP Platform

 Silicon/Intel/SimicsIch10SiliconBinPkg/License.txt |  30 ++
 .../UndiBinary/GigUndiDxe.efi  | Bin 0 -> 195360 bytes
 .../UndiBinary/IntelProprietaryLicense.txt |  43 +
 .../UndiBinary/UndiDxe.inf |  25 
 4 files changed, 98 insertions(+)
 create mode 100644 Silicon/Intel/SimicsIch10SiliconBinPkg/License.txt
 create mode 100644 
Silicon/Intel/SimicsIch10SiliconBinPkg/UndiBinary/GigUndiDxe.efi
 create mode 100644 
Silicon/Intel/SimicsIch10SiliconBinPkg/UndiBinary/IntelProprietaryLicense.txt
 create mode 100644 
Silicon/Intel/SimicsIch10SiliconBinPkg/UndiBinary/UndiDxe.inf

-- 
2.16.2.windows.1


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[edk2-devel] [edk2-non-osi PATCH v2 1/1] SimicsICH10SiliconBinPkg: Add UNDI ROM for SIMICS QSP Platform

[David Wei]

Add UNDI option ROM for SIMICS QSP Network support

Cc: Hao Wu 
Cc: Liming Gao 
Cc: Ankit Sinha 
Cc: Agyeman Prince 
Cc: Kubacki Michael A 
Cc: Nate DeSimone 
Cc: Michael D Kinney 

Signed-off-by: David Wei 
---
 Silicon/Intel/SimicsIch10SiliconBinPkg/License.txt |  30 ++
 .../UndiBinary/GigUndiDxe.efi  | Bin 0 -> 195360 bytes
 .../UndiBinary/IntelProprietaryLicense.txt |  43 +
 .../UndiBinary/UndiDxe.inf |  25 
 4 files changed, 98 insertions(+)
 create mode 100644 Silicon/Intel/SimicsIch10SiliconBinPkg/License.txt
 create mode 100644 
Silicon/Intel/SimicsIch10SiliconBinPkg/UndiBinary/GigUndiDxe.efi
 create mode 100644 
Silicon/Intel/SimicsIch10SiliconBinPkg/UndiBinary/IntelProprietaryLicense.txt
 create mode 100644 
Silicon/Intel/SimicsIch10SiliconBinPkg/UndiBinary/UndiDxe.inf

diff --git a/Silicon/Intel/SimicsIch10SiliconBinPkg/License.txt 
b/Silicon/Intel/SimicsIch10SiliconBinPkg/License.txt
new file mode 100644
index 000..5507dd0
--- /dev/null
+++ b/Silicon/Intel/SimicsIch10SiliconBinPkg/License.txt
@@ -0,0 +1,30 @@
+Copyright (c) 2012 - 2019, Intel Corporation. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+* Redistributions of source code must retain the above copyright
+  notice, this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
+  notice, this list of conditions and the following disclaimer in
+  the documentation and/or other materials provided with the
+  distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGE.
+
+Some files are subject to a license documented in the
+IntelProprietaryLicense.txt file. These files are in the same
+directory as IntelProprietaryLicense.txt, and they do not have
+a license specified within the file.
diff --git a/Silicon/Intel/SimicsIch10SiliconBinPkg/UndiBinary/GigUndiDxe.efi 
b/Silicon/Intel/SimicsIch10SiliconBinPkg/UndiBinary/GigUndiDxe.efi
new file mode 100644
index 
..7b8e0d7be00dccedb84ebed5c5c87a0e79078983
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[edk2-devel] [edk2-platforms PATCH v2 7/7] Platform/Intel: Add build option for SIMICS QSP Platform

[David Wei]

Add build option in build script for SIMICS QSP Platform
Add Maintainers of Simics QSP related packages

Cc: Hao Wu 
Cc: Liming Gao 
Cc: Ankit Sinha 
Cc: Agyeman Prince 
Cc: Kubacki Michael A 
Cc: Nate DeSimone 
Cc: Michael D Kinney 

Signed-off-by: David Wei 
---
 Maintainers.txt  | 12 
 Platform/Intel/build.cfg |  2 ++
 Platform/Intel/build_bios.py |  3 +++
 3 files changed, 17 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index b16432bf87..90eb3c3dd0 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -103,6 +103,10 @@ M: Chasel Chiu 
 M: Michael Kubacki 
 M: Nate DeSimone 
 
+Platform/Intel/SimicsOpenBoardPkg
+M: Wei David Y 
+M: Agyeman Prince 
+
 Platform/Intel/Tools
 M: Bob Feng 
 M: Liming Gao 
@@ -155,6 +159,14 @@ M: Gillispie, Thad 
 M: Bu, Daocheng 
 M: Oram, Isaac W 
 
+Silicon/Intel/SimicsX58SktPkg
+M: Wei David Y 
+M: Agyeman Prince 
+
+Silicon/Intel/SimicsIch10Pkg
+M: Wei David Y 
+M: Agyeman Prince 
+
 Silicon/Intel/Tools
 M: Bob Feng 
 M: Liming Gao 
diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg
index b6d32ada49..75cb446aa5 100644
--- a/Platform/Intel/build.cfg
+++ b/Platform/Intel/build.cfg
@@ -11,6 +11,7 @@ WORKSPACE =
 WORKSPACE_FSP_BIN = FSP
 EDK_TOOLS_BIN = edk2-BaseTools-win32
 EDK_BASETOOLS = BaseTools
+WORKSPACE_DRIVERS = edk2-platforms/Drivers
 WORKSPACE_PLATFORM = edk2-platforms/Platform/Intel
 WORKSPACE_SILICON = edk2-platforms/Silicon/Intel
 WORKSPACE_PLATFORM_BIN =
@@ -52,6 +53,7 @@ NUMBER_OF_PROCESSORS = 0
 [PLATFORMS]
 # board_name = path_to_board_build_config.cfg
 BoardMtOlympus = PurleyOpenBoardPkg/BoardMtOlympus/build_config.cfg
+BoardX58Ich10 = SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg
 KabylakeRvp3 = KabylakeOpenBoardPkg/KabylakeRvp3/build_config.cfg
 N1xxWU = ClevoOpenBoardPkg/N1xxWU/build_config.cfg
 WhiskeylakeURvp = WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/build_config.cfg
diff --git a/Platform/Intel/build_bios.py b/Platform/Intel/build_bios.py
index 9152670dcb..46285df19a 100644
--- a/Platform/Intel/build_bios.py
+++ b/Platform/Intel/build_bios.py
@@ -104,6 +104,8 @@ def pre_build(build_config, build_type="DEBUG", 
silent=False, toolchain=None):
 config["WORKSPACE_PLATFORM"])
 config["WORKSPACE_SILICON"] = os.path.join(config["WORKSPACE"],
config["WORKSPACE_SILICON"])
+config["WORKSPACE_DRIVERS"] = os.path.join(config["WORKSPACE"],
+   config["WORKSPACE_DRIVERS"])
 config["WORKSPACE_PLATFORM_BIN"] = \
 os.path.join(config["WORKSPACE"], config["WORKSPACE_PLATFORM_BIN"])
 config["WORKSPACE_SILICON_BIN"] = \
@@ -115,6 +117,7 @@ def pre_build(build_config, build_type="DEBUG", 
silent=False, toolchain=None):
 config["PACKAGES_PATH"] = config["WORKSPACE_PLATFORM"]
 config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_SILICON"]
 config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_SILICON_BIN"]
+config["PACKAGES_PATH"] += os.pathsep + config["WORKSPACE_DRIVERS"]
 config["PACKAGES_PATH"] += os.pathsep + \
 os.path.join(config["WORKSPACE"], "FSP")
 config["PACKAGES_PATH"] += os.pathsep + \
-- 
2.16.2.windows.1


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[edk2-devel] [edk2-platforms PATCH v2 1/7] SimicsX58SktPkg: Add CPU Pkg for SimicsX58

[David Wei]

Add CPU Pkg for SimicsX58. It is added for simics QSP project support

Cc: Hao Wu 
Cc: Liming Gao 
Cc: Ankit Sinha 
Cc: Agyeman Prince 
Cc: Kubacki Michael A 
Cc: Nate DeSimone 
Cc: Michael D Kinney 

Signed-off-by: David Wei 
---
 .../SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.c | 148 +
 .../SimicsX58SktPkg/Smm/Access/SmmAccessPei.c  | 346 +
 .../SimicsX58SktPkg/Smm/Access/SmramInternal.c | 200 
 .../Include/Register/X58SmramSaveStateMap.h| 178 +++
 Silicon/Intel/SimicsX58SktPkg/SktPkg.dec   |  37 +++
 Silicon/Intel/SimicsX58SktPkg/SktPkgPei.dsc|  14 +
 .../Intel/SimicsX58SktPkg/SktPostMemoryInclude.fdf |   9 +
 .../Intel/SimicsX58SktPkg/SktPreMemoryInclude.fdf  |  10 +
 Silicon/Intel/SimicsX58SktPkg/SktSecInclude.fdf|  16 +
 .../Intel/SimicsX58SktPkg/SktUefiBootInclude.fdf   |  14 +
 .../SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.inf   |  54 
 .../SimicsX58SktPkg/Smm/Access/SmmAccessPei.inf|  65 
 .../SimicsX58SktPkg/Smm/Access/SmramInternal.h |  81 +
 13 files changed, 1172 insertions(+)
 create mode 100644 Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.c
 create mode 100644 Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.c
 create mode 100644 Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmramInternal.c
 create mode 100644 
Silicon/Intel/SimicsX58SktPkg/Include/Register/X58SmramSaveStateMap.h
 create mode 100644 Silicon/Intel/SimicsX58SktPkg/SktPkg.dec
 create mode 100644 Silicon/Intel/SimicsX58SktPkg/SktPkgPei.dsc
 create mode 100644 Silicon/Intel/SimicsX58SktPkg/SktPostMemoryInclude.fdf
 create mode 100644 Silicon/Intel/SimicsX58SktPkg/SktPreMemoryInclude.fdf
 create mode 100644 Silicon/Intel/SimicsX58SktPkg/SktSecInclude.fdf
 create mode 100644 Silicon/Intel/SimicsX58SktPkg/SktUefiBootInclude.fdf
 create mode 100644 Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.inf
 create mode 100644 Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccessPei.inf
 create mode 100644 Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmramInternal.h

diff --git a/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.c 
b/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.c
new file mode 100644
index 00..771fddb487
--- /dev/null
+++ b/Silicon/Intel/SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.c
@@ -0,0 +1,148 @@
+/** @file
+  A DXE_DRIVER providing SMRAM access by producing EFI_SMM_ACCESS2_PROTOCOL.
+
+  X58 TSEG is expected to have been verified and set up by the SmmAccessPei
+  driver.
+
+  Copyright (C) 2013, 2015, Red Hat, Inc.
+  Copyright (c) 2009 - 2010, Intel Corporation. All rights reserved.
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+#include 
+#include 
+#include 
+
+#include "SmramInternal.h"
+
+/**
+  Opens the SMRAM area to be accessible by a boot-service driver.
+
+  This function "opens" SMRAM so that it is visible while not inside of SMM.
+  The function should return EFI_UNSUPPORTED if the hardware does not support
+  hiding of SMRAM. The function should return EFI_DEVICE_ERROR if the SMRAM
+  configuration is locked.
+
+  @param[in] This   The EFI_SMM_ACCESS2_PROTOCOL instance.
+
+  @retval EFI_SUCCESS   The operation was successful.
+  @retval EFI_UNSUPPORTED   The system does not support opening and closing of
+SMRAM.
+  @retval EFI_DEVICE_ERROR  SMRAM cannot be opened, perhaps because it is
+locked.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+SmmAccess2DxeOpen (
+  IN EFI_SMM_ACCESS2_PROTOCOL  *This
+  )
+{
+  return SmramAccessOpen (>LockState, >OpenState);
+}
+
+/**
+  Inhibits access to the SMRAM.
+
+  This function "closes" SMRAM so that it is not visible while outside of SMM.
+  The function should return EFI_UNSUPPORTED if the hardware does not support
+  hiding of SMRAM.
+
+  @param[in] This   The EFI_SMM_ACCESS2_PROTOCOL instance.
+
+  @retval EFI_SUCCESS   The operation was successful.
+  @retval EFI_UNSUPPORTED   The system does not support opening and closing of
+SMRAM.
+  @retval EFI_DEVICE_ERROR  SMRAM cannot be closed.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+SmmAccess2DxeClose (
+  IN EFI_SMM_ACCESS2_PROTOCOL  *This
+  )
+{
+  return SmramAccessClose (>LockState, >OpenState);
+}
+
+/**
+  Inhibits access to the SMRAM.
+
+  This function prohibits access to the SMRAM region.  This function is usually
+  implemented such that it is a write-once operation.
+
+  @param[in] This  The EFI_SMM_ACCESS2_PROTOCOL instance.
+
+  @retval EFI_SUCCESS  The device was successfully locked.
+  @retval EFI_UNSUPPORTED  The system does not support locking of SMRAM.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+SmmAccess2DxeLock (
+  IN EFI_SMM_ACCESS2_PROTOCOL  *This
+  )
+{
+  return SmramAccessLock (>LockState, >OpenState);
+}
+
+/**
+  Queries the memory controller for the possible regions that will support
+  SMRAM.
+
+  @param[in] This   The 

[edk2-devel] [edk2-platforms PATCH v2 4/7] SimicsOpenBoardPkg: Add DXE driver for Legacy Sio

[David Wei]

Add DXE driver for Legacy Sio support

Cc: Hao Wu 
Cc: Liming Gao 
Cc: Ankit Sinha 
Cc: Agyeman Prince 
Cc: Kubacki Michael A 
Cc: Nate DeSimone 
Cc: Michael D Kinney 

Signed-off-by: David Wei 
---
 .../LegacySioDxe/ComponentName.c   | 173 ++
 .../SimicsOpenBoardPkg/LegacySioDxe/SioChip.c  | 272 ++
 .../SimicsOpenBoardPkg/LegacySioDxe/SioDriver.c| 600 +
 .../SimicsOpenBoardPkg/LegacySioDxe/SioService.c   | 249 +
 .../LegacySioDxe/ComponentName.h   |  87 +++
 .../LegacySioDxe/LegacySioDxe.inf  |  54 ++
 .../SimicsOpenBoardPkg/LegacySioDxe/Register.h |  15 +
 .../SimicsOpenBoardPkg/LegacySioDxe/SioChip.h  | 195 +++
 .../SimicsOpenBoardPkg/LegacySioDxe/SioDriver.h| 134 +
 .../SimicsOpenBoardPkg/LegacySioDxe/SioService.h   | 143 +
 10 files changed, 1922 insertions(+)
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/LegacySioDxe/ComponentName.c
 create mode 100644 Platform/Intel/SimicsOpenBoardPkg/LegacySioDxe/SioChip.c
 create mode 100644 Platform/Intel/SimicsOpenBoardPkg/LegacySioDxe/SioDriver.c
 create mode 100644 Platform/Intel/SimicsOpenBoardPkg/LegacySioDxe/SioService.c
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/LegacySioDxe/ComponentName.h
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/LegacySioDxe/LegacySioDxe.inf
 create mode 100644 Platform/Intel/SimicsOpenBoardPkg/LegacySioDxe/Register.h
 create mode 100644 Platform/Intel/SimicsOpenBoardPkg/LegacySioDxe/SioChip.h
 create mode 100644 Platform/Intel/SimicsOpenBoardPkg/LegacySioDxe/SioDriver.h
 create mode 100644 Platform/Intel/SimicsOpenBoardPkg/LegacySioDxe/SioService.h

diff --git a/Platform/Intel/SimicsOpenBoardPkg/LegacySioDxe/ComponentName.c 
b/Platform/Intel/SimicsOpenBoardPkg/LegacySioDxe/ComponentName.c
new file mode 100644
index 00..4ba02f92c0
--- /dev/null
+++ b/Platform/Intel/SimicsOpenBoardPkg/LegacySioDxe/ComponentName.c
@@ -0,0 +1,173 @@
+/** @file
+  Install Base and Size Info Ppi for Firmware Volume Recovery.
+
+  Copyright (c) 2013 - 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "SioDriver.h"
+
+///
+/// Component Name Protocol instance
+///
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME_PROTOCOL  mSioComponentName = 
{
+  SioComponentNameGetDriverName,
+  SioComponentNameGetControllerName,
+  "eng"
+};
+
+///
+/// Component Name 2 Protocol instance
+///
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_COMPONENT_NAME2_PROTOCOL mSioComponentName2 
= {
+  (EFI_COMPONENT_NAME2_GET_DRIVER_NAME)SioComponentNameGetDriverName,
+  (EFI_COMPONENT_NAME2_GET_CONTROLLER_NAME)SioComponentNameGetControllerName,
+  "en"
+};
+
+///
+/// Table of driver names
+///
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE mSioDriverNameTable[] = 
{
+  {
+"eng;en",
+L"Super I/O Driver"
+  },
+  {
+NULL,
+NULL
+  }
+};
+
+///
+/// Table of Controller names
+///
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_UNICODE_STRING_TABLE 
mSioControllerNameTable[] = {
+  {
+"eng;en",
+L"Super I/O Controller"
+  },
+  {
+NULL,
+NULL
+  }
+};
+
+/**
+  Retrieves a Unicode string that is the user-readable name of the EFI Driver.
+
+  @param  This   A pointer to the EFI_COMPONENT_NAME_PROTOCOL instance.
+  @param  Language   A pointer to a three-character ISO 639-2 language 
identifier.
+ This is the language of the driver name that that the 
caller
+ is requesting, and it must match one of the languages 
specified
+ in SupportedLanguages.  The number of languages supported 
by a
+ driver is up to the driver writer.
+  @param  DriverName A pointer to the Unicode string to return.  This Unicode 
string
+ is the name of the driver specified by This in the 
language
+ specified by Language.
+
+  @retval EFI_SUCCESS   The Unicode string for the Driver specified by 
This
+and the language specified by Language was 
returned
+in DriverName.
+  @retval EFI_INVALID_PARAMETER Language is NULL.
+  @retval EFI_INVALID_PARAMETER DriverName is NULL.
+  @retval EFI_UNSUPPORTED   The driver specified by This does not support 
the
+language specified by Language.
+
+**/
+EFI_STATUS
+EFIAPI
+SioComponentNameGetDriverName (
+  IN  EFI_COMPONENT_NAME_PROTOCOL  *This,
+  IN  CHAR8*Language,
+  OUT CHAR16   **DriverName
+  )
+{
+  return LookupUnicodeString2 (
+   Language,
+   This->SupportedLanguages,
+   mSioDriverNameTable,
+   DriverName,
+   (BOOLEAN)(This == )
+   );
+}
+
+/**
+  Retrieves a Unicode string that is the user readable name of the controller
+  that is being managed by an EFI Driver.
+
+  @param  This A 

[edk2-devel] [edk2-platforms PATCH v2 0/7] Add Initial QSP MinPlatform Pkg for SIMICS

[David Wei]

Create the SimicsOpenBoardPkg and its silicon Pkg to provide the support
for SIMICS quick start platform. it uses X58/ICH10 and emulated by SIMICS
model.

Different from V1:
  Fix coding style and file naming convention issues
  Fix dependency issue for DEC file
  Change some codes to more intuitive place
  Change Board related GUID names
  Remove old build bat file to use the python build tool
  Use platform Logo Library instead of Logo driver under EDK2

David Wei (7):
  SimicsX58SktPkg:  Add CPU Pkg for SimicsX58
  SimicsICH10Pkg:  Add PCH Pkg for SimicsICH10
  SimicsOpenBoardPkg:  Add SimicsOpenBoardPkg and its modules
  SimicsOpenBoardPkg: Add DXE driver for Legacy Sio
  SimicsOpenBoardPkg: Add Overrides modules and Logo image for SIMICS
QSP Platform
  SimicsOpenBoardPkg/BoardX58Ich10: Add board module for QSP Build tip
  Platform/Intel:  Add build option for SIMICS QSP Platform

 .../Library/BoardInitLib/PeiBoardInitPostMemLib.c  |   44 +
 .../Library/BoardInitLib/PeiBoardInitPreMemLib.c   |  110 ++
 .../Library/BoardInitLib/PeiX58Ich10Detect.c   |   26 +
 .../BoardInitLib/PeiX58Ich10InitPostMemLib.c   |   34 +
 .../BoardInitLib/PeiX58Ich10InitPreMemLib.c|  111 ++
 .../LegacySioDxe/ComponentName.c   |  173 +++
 .../SimicsOpenBoardPkg/LegacySioDxe/SioChip.c  |  272 
 .../SimicsOpenBoardPkg/LegacySioDxe/SioDriver.c|  600 
 .../SimicsOpenBoardPkg/LegacySioDxe/SioService.c   |  249 +++
 .../SimicsOpenBoardPkg/Library/DxeLogoLib/Logo.c   |  647 
 .../Library/LoadLinuxLib/Linux.c   |  662 
 .../Library/LoadLinuxLib/LinuxGdt.c|  175 +++
 .../Library/NvVarsFileLib/FsAccess.c   |  507 +++
 .../Library/NvVarsFileLib/NvVarsFileLib.c  |   77 +
 .../Library/PciHostBridgeLib/PciHostBridgeLib.c|  419 ++
 .../SimicsOpenBoardPkg/Library/PeiReportFvLib/Fv.c |  100 ++
 .../Library/PeiReportFvLib/PeiReportFvLib.c|  118 ++
 .../Library/PlatformBootManagerLib/BdsPlatform.c   | 1553 +++
 .../Library/PlatformBootManagerLib/PlatformData.c  |   35 +
 .../SerializeVariablesLib/SerializeVariablesLib.c  |  869 +++
 .../MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c  | 1579 
 .../MinPlatformPkg/Acpi/AcpiTables/Facs/Facs.c |   84 ++
 .../MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c |  359 +
 .../MinPlatformPkg/Acpi/AcpiTables/Hpet/Hpet.c |   78 +
 .../MinPlatformPkg/Acpi/AcpiTables/Wsmt/Wsmt.c |   46 +
 .../Overrides/OvmfPkg/QemuVideoDxe/ComponentName.c |  205 +++
 .../Overrides/OvmfPkg/QemuVideoDxe/Driver.c| 1011 +
 .../QemuVideoDxe/DriverSupportedEfiVersion.c   |   15 +
 .../Overrides/OvmfPkg/QemuVideoDxe/Gop.c   |  416 ++
 .../Overrides/OvmfPkg/QemuVideoDxe/Initialize.c|  341 +
 .../Overrides/OvmfPkg/QemuVideoDxe/VbeShim.c   |  302 
 .../SiliconPolicyInitLib/SiliconPolicyInitLib.c|  108 ++
 .../SiliconPolicyUpdateLib.c   |   70 +
 .../Intel/SimicsOpenBoardPkg/SecCore/SecMain.c |  956 
 .../Intel/SimicsOpenBoardPkg/SimicsDxe/Platform.c  |  865 +++
 .../SimicsOpenBoardPkg/SimicsDxe/PlatformConfig.c  |  123 ++
 Platform/Intel/SimicsOpenBoardPkg/SimicsPei/Cmos.c |   57 +
 .../SimicsOpenBoardPkg/SimicsPei/FeatureControl.c  |  114 ++
 .../Intel/SimicsOpenBoardPkg/SimicsPei/MemDetect.c |  568 +++
 .../Intel/SimicsOpenBoardPkg/SimicsPei/Platform.c  |  630 
 .../SmbiosPlatformDxe/SmbiosPlatformDxe.c  |  148 ++
 .../Library/ResetSystemLib/ResetSystemLib.c|  137 ++
 .../Library/SmmSpiFlashCommonLib/SpiFlashCommon.c  |  194 +++
 .../SmmSpiFlashCommonLib/SpiFlashCommonSmmLib.c|   54 +
 .../LibraryPrivate/BasePchSpiCommonLib/SpiCommon.c |  935 
 .../SmmControl/RuntimeDxe/SmmControl2Dxe.c |  410 +
 Silicon/Intel/SimicsIch10Pkg/Spi/Smm/PchSpi.c  |  175 +++
 .../SimicsX58SktPkg/Smm/Access/SmmAccess2Dxe.c |  148 ++
 .../SimicsX58SktPkg/Smm/Access/SmmAccessPei.c  |  346 +
 .../SimicsX58SktPkg/Smm/Access/SmramInternal.c |  200 +++
 Maintainers.txt|   12 +
 .../SimicsOpenBoardPkg/AcpiTables/AcpiTables.inf   |   31 +
 .../Intel/SimicsOpenBoardPkg/AcpiTables/Dsdt.asl   |  821 ++
 .../Intel/SimicsOpenBoardPkg/AcpiTables/Platform.h |   75 +
 .../BoardX58Ich10/DecomprScratchEnd.fdf.inc|   66 +
 .../BoardInitLib/PeiBoardInitPostMemLib.inf|   36 +
 .../Library/BoardInitLib/PeiBoardInitPreMemLib.inf |   39 +
 .../Library/BoardInitLib/PeiX58Ich10InitLib.h  |   16 +
 .../BoardX58Ich10/OpenBoardPkg.dsc |  233 +++
 .../BoardX58Ich10/OpenBoardPkg.fdf |  304 
 .../BoardX58Ich10/OpenBoardPkg.fdf.inc |   54 +
 .../BoardX58Ich10/OpenBoardPkgBuildOption.dsc  |   78 +
 .../BoardX58Ich10/OpenBoardPkgConfig.dsc   |   56 +
 .../BoardX58Ich10/OpenBoardPkgPcd.dsc  

[edk2-devel] [edk2-platforms PATCH v2 6/7] SimicsOpenBoardPkg/BoardX58Ich10: Add board module for QSP Build tip

[David Wei]

Add BoardX58ICH10 module for QSP Build tip

Cc: Hao Wu 
Cc: Liming Gao 
Cc: Ankit Sinha 
Cc: Agyeman Prince 
Cc: Kubacki Michael A 
Cc: Nate DeSimone 
Cc: Michael D Kinney 

Signed-off-by: David Wei 
---
 .../Library/BoardInitLib/PeiBoardInitPostMemLib.c  |  44 +++
 .../Library/BoardInitLib/PeiBoardInitPreMemLib.c   | 110 
 .../Library/BoardInitLib/PeiX58Ich10Detect.c   |  26 ++
 .../BoardInitLib/PeiX58Ich10InitPostMemLib.c   |  34 +++
 .../BoardInitLib/PeiX58Ich10InitPreMemLib.c| 111 
 .../BoardX58Ich10/DecomprScratchEnd.fdf.inc|  66 +
 .../BoardInitLib/PeiBoardInitPostMemLib.inf|  36 +++
 .../Library/BoardInitLib/PeiBoardInitPreMemLib.inf |  39 +++
 .../Library/BoardInitLib/PeiX58Ich10InitLib.h  |  16 ++
 .../BoardX58Ich10/OpenBoardPkg.dsc | 233 
 .../BoardX58Ich10/OpenBoardPkg.fdf | 304 +
 .../BoardX58Ich10/OpenBoardPkg.fdf.inc |  54 
 .../BoardX58Ich10/OpenBoardPkgBuildOption.dsc  |  78 ++
 .../BoardX58Ich10/OpenBoardPkgConfig.dsc   |  56 
 .../BoardX58Ich10/OpenBoardPkgPcd.dsc  | 281 +++
 .../BoardX58Ich10/VarStore.fdf.inc |  53 
 .../BoardX58Ich10/build_config.cfg |  31 +++
 17 files changed, 1572 insertions(+)
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiBoardInitPostMemLib.c
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiBoardInitPreMemLib.c
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiX58Ich10Detect.c
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiX58Ich10InitPostMemLib.c
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiX58Ich10InitPreMemLib.c
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/DecomprScratchEnd.fdf.inc
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiX58Ich10InitLib.h
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.dsc
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkg.fdf.inc
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgBuildOption.dsc
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgConfig.dsc
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/VarStore.fdf.inc
 create mode 100644 
Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/build_config.cfg

diff --git 
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiBoardInitPostMemLib.c
 
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiBoardInitPostMemLib.c
new file mode 100644
index 00..5ece8c6e34
--- /dev/null
+++ 
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiBoardInitPostMemLib.c
@@ -0,0 +1,44 @@
+/** @file
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+EFI_STATUS
+EFIAPI
+X58Ich10BoardInitBeforeSiliconInit (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+X58Ich10BoardInitAfterSiliconInit (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+BoardInitBeforeSiliconInit (
+  VOID
+  )
+{
+  X58Ich10BoardInitBeforeSiliconInit ();
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+BoardInitAfterSiliconInit (
+  VOID
+  )
+{
+  X58Ich10BoardInitAfterSiliconInit ();
+  return EFI_SUCCESS;
+}
diff --git 
a/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiBoardInitPreMemLib.c
 
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiBoardInitPreMemLib.c
new file mode 100644
index 00..d16e649d34
--- /dev/null
+++ 
b/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/Library/BoardInitLib/PeiBoardInitPreMemLib.c
@@ -0,0 +1,110 @@
+/** @file
+  Copyright (c) 2019 Intel Corporation. All rights reserved. 
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+EFI_STATUS
+EFIAPI
+X58Ich10BoardDetect(
+  VOID
+  );
+
+EFI_BOOT_MODE
+EFIAPI
+X58Ich10BoardBootModeDetect (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+X58Ich10BoardDebugInit (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+X58Ich10BoardInitBeforeMemoryInit (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+X58Ich10BoardInitAfterMemoryInit (
+  VOID

Re: [edk2-devel] [edk2-platforms][PATCH V1 1/1] UserInterfacePkg/UserAuthentication: Fix NULL pointer dereferences

[Dandan Bi]

Reviewed-by: Dandan Bi 


Thanks,
Dandan

> -Original Message-
> From: Kubacki, Michael A
> Sent: Tuesday, August 27, 2019 9:36 AM
> To: devel@edk2.groups.io
> Cc: Bi, Dandan ; Gao, Liming 
> Subject: [edk2-platforms][PATCH V1 1/1]
> UserInterfacePkg/UserAuthentication: Fix NULL pointer dereferences
> 
> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2115
> 
> Cc: Dandan Bi 
> Cc: Liming Gao 
> Signed-off-by: Michael Kubacki 
> ---
> 
> Platform/Intel/UserInterfaceFeaturePkg/UserAuthentication/UserAuthentic
> ation2Dxe.c | 8 +++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git
> a/Platform/Intel/UserInterfaceFeaturePkg/UserAuthentication/UserAuthen
> tication2Dxe.c
> b/Platform/Intel/UserInterfaceFeaturePkg/UserAuthentication/UserAuthen
> tication2Dxe.c
> index 55b264f4ff..b4326d380f 100644
> ---
> a/Platform/Intel/UserInterfaceFeaturePkg/UserAuthentication/UserAuthen
> tication2Dxe.c
> +++
> b/Platform/Intel/UserInterfaceFeaturePkg/UserAuthentication/UserAuthen
> tication2Dxe.c
> @@ -300,13 +300,16 @@ UserAuthenticationCallback (
>  switch (mUserAuthenticationData->PasswordState) {
>  case BROWSER_STATE_VALIDATE_PASSWORD:
>UserInputPassword = HiiGetString (mUserAuthenticationData-
> >HiiHandle, Value->string, NULL);
> +  if (UserInputPassword == NULL) {
> +return EFI_UNSUPPORTED;
> +  }
>if ((StrLen (UserInputPassword) >= PASSWORD_MAX_SIZE)) {
>  Status = EFI_NOT_READY;
>  break;
>}
>if (UserInputPassword[0] == 0) {
>  //
> -// Setup will use a NULL password to check whether the old 
> password
> is set,
> +// Setup will use an empty password to check whether the old
> password is set,
>  // If the validation is successful, means there is no old 
> password,
> return
>  // success to set the new password. Or need to return
> EFI_NOT_READY to
>  // let user input the old password.
> @@ -343,6 +346,9 @@ UserAuthenticationCallback (
> 
>  case BROWSER_STATE_SET_PASSWORD:
>UserInputPassword = HiiGetString (mUserAuthenticationData-
> >HiiHandle, Value->string, NULL);
> +  if (UserInputPassword == NULL) {
> +return EFI_UNSUPPORTED;
> +  }
>if ((StrLen (UserInputPassword) >= PASSWORD_MAX_SIZE)) {
>  Status = EFI_NOT_READY;
>  break;
> --
> 2.16.2.windows.1


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Re: [edk2-devel] [edk2-platforms][PATCH V3 2/2] WhiskeylakeOpenBoardPkg: Fix GCC Build Failures

[Chiu, Chasel]

Sorry that I overlooked that the last part I questioned was just a cleanup.
I'm ok with what you are going to do. Thanks for clarification!


> -Original Message-
> From: Desimone, Nathaniel L
> Sent: Wednesday, August 28, 2019 6:54 AM
> To: Kubacki, Michael A ; Chiu, Chasel
> ; devel@edk2.groups.io
> Cc: Gao, Liming 
> Subject: RE: [edk2-platforms][PATCH V3 2/2] WhiskeylakeOpenBoardPkg: Fix
> GCC Build Failures
> 
> Hi Michael,
> 
> Your responses address my comments from PATCH V2 as well. If Chasel has no
> further comments, go ahead and send a PATCH V4 and I will provide a
> reviewed-by.
> 
> Thanks,
> Nate
> 
> -Original Message-
> From: Kubacki, Michael A
> Sent: Monday, August 26, 2019 7:45 PM
> To: Chiu, Chasel ; devel@edk2.groups.io
> Cc: Desimone, Nathaniel L ; Gao, Liming
> 
> Subject: RE: [edk2-platforms][PATCH V3 2/2] WhiskeylakeOpenBoardPkg: Fix
> GCC Build Failures
> 
> My responses are inline [makubacki]. I will wait for your response before I 
> send
> the next patchset.
> 
> Thanks,
> Michael
> 
> > -Original Message-
> > From: Chiu, Chasel
> > Sent: Monday, August 26, 2019 7:14 PM
> > To: Kubacki, Michael A ;
> > devel@edk2.groups.io
> > Cc: Desimone, Nathaniel L ; Gao, Liming
> > 
> > Subject: RE: [edk2-platforms][PATCH V3 2/2] WhiskeylakeOpenBoardPkg: Fix
> > GCC Build Failures
> >
> >
> > Please see 3 questions below inline. (tagged by [chasel])
> >
> > Thanks!
> > Chasel
> >
> >
> > > -Original Message-
> > > From: Kubacki, Michael A
> > > Sent: Tuesday, August 27, 2019 2:48 AM
> > > To: devel@edk2.groups.io
> > > Cc: Chiu, Chasel ; Desimone, Nathaniel L
> > > ; Gao, Liming 
> > > Subject: [edk2-platforms][PATCH V3 2/2] WhiskeylakeOpenBoardPkg: Fix
> > GCC
> > > Build Failures
> > >
> > > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2110
> > >
> > > Fixes build failures on GCC7.3.0. Tested on Ubunutu 18.04.1 LTS.
> > >
> > > Cc: Chasel Chiu 
> > > Cc: Nate DeSimone 
> > > Cc: Liming Gao 
> > > Signed-off-by: Michael Kubacki 
> > > ---
> > >  Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> > > |   6 +-
> > >
> > >
> > Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei
> > H
> > > daVerbTableLib.inf |   1 +
> > >
> > >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> > I
> > > nitLib/PeiBoardInitPostMemLib.inf   |   8 +-
> > >
> > >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> > I
> > > nitLib/PeiMultiBoardInitPostMemLib.inf  |   2 +
> > >
> > >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> > I
> > > nitLib/PeiMultiBoardInitPreMemLib.inf   |  12 +-
> > >
> > >
> > Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTabl
> > e.
> > > h |   2 +-
> > >
> > >
> > Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Whis
> > k
> > > eylakeURvpId.h   |  12 -
> > >
> > >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> > I
> > > nitLib/BoardFunc.h  |   2 +
> > >
> > >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> > I
> > > nitLib/PeiWhiskeylakeURvpInitLib.h  |  41 -
> > >
> > >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> > I
> > > nitLib/WhiskeylakeURvpInit.h|  41 +
> > >
> > >
> > Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic
> > yI
> > > nitLib/PeiFspCpuPolicyInitLib.c   |   4 +-
> > >
> > >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/Ba
> > > seGpioExpanderLib.c |   6 +-
> > >
> > >
> > Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/{Pc
> > h
> > > HdaVerbTables.h => PchHdaVerbTables.c} | 963
> > > +---
> > >
> > >
> > Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei
> > H
> > > daVerbTableLib.c   |   7 +-
> > >
> > >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi
> > b
> > > /PeiPchPolicyUpdate.c|   6 -
> > >
> > >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi
> > b
> > > /PeiSaPolicyUpdatePreMem.c   |  15 +-
> > >
> > >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib
> > .
> > > c   |   4 -
> > >
> > >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> > A
> > > cpiLib/SmmMultiBoardAcpiSupportLib.c

Re: [edk2-devel] [PATCH] IntelFsp2Pkg/FspSecCore: Remove unneeded MdeModulePkg dependency

[Chiu, Chasel]

Same findings as Nate, with FspSecCoreT.inf copyright updated, Reviewed-by: 
Chasel Chiu 

> -Original Message-
> From: Desimone, Nathaniel L
> Sent: Wednesday, August 28, 2019 7:21 AM
> To: Ni, Ray ; devel@edk2.groups.io
> Cc: Chiu, Chasel ; Zeng, Star 
> Subject: RE: [PATCH] IntelFsp2Pkg/FspSecCore: Remove unneeded
> MdeModulePkg dependency
> 
> Actually, please make sure you update copyright year on FspSecCoreT.inf. With
> that change...
> 
> Reviewed-by: Nate DeSimone 
> 
> -Original Message-
> From: Ni, Ray
> Sent: Tuesday, August 27, 2019 3:41 PM
> To: devel@edk2.groups.io
> Cc: Chiu, Chasel ; Desimone, Nathaniel L
> ; Zeng, Star 
> Subject: [PATCH] IntelFsp2Pkg/FspSecCore: Remove unneeded MdeModulePkg
> dependency
> 
> Signed-off-by: Ray Ni 
> Cc: Chasel Chiu 
> Cc: Nate DeSimone 
> Cc: Star Zeng 
> ---
>  IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 1 -
> IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf | 1 -
> IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf | 1 -
>  3 files changed, 3 deletions(-)
> 
> diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
> b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
> index 571ed9bc44..25f2a109ab 100644
> --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
> +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
> @@ -40,7 +40,6 @@ [Binaries.Ia32]
> 
>  [Packages]
>MdePkg/MdePkg.dec
> -  MdeModulePkg/MdeModulePkg.dec
>IntelFsp2Pkg/IntelFsp2Pkg.dec
> 
>  [LibraryClasses]
> diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
> b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
> index 17924b118c..1d9c2554d1 100644
> --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
> +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
> @@ -35,7 +35,6 @@ [Binaries.Ia32]
> 
>  [Packages]
>MdePkg/MdePkg.dec
> -  MdeModulePkg/MdeModulePkg.dec
>IntelFsp2Pkg/IntelFsp2Pkg.dec
> 
>  [LibraryClasses]
> diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
> b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
> index e66ea4593b..6f65e69e77 100644
> --- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
> +++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
> @@ -34,7 +34,6 @@ [Binaries.Ia32]
> 
>  [Packages]
>MdePkg/MdePkg.dec
> -  MdeModulePkg/MdeModulePkg.dec
>IntelFsp2Pkg/IntelFsp2Pkg.dec
> 
>  [LibraryClasses]
> --
> 2.21.0.windows.1


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[edk2-devel] [PATCH 1/2] PcAtChipsetPkg: add PcdRealTimeClockUpdateTimeout

[Ni, Ray]

PcdRealTimeClockUpdateTimeout is now defined in MdeModulePkg.dec.
This is the only reason that causes PcAtChipsetPkg depends on
MdeModulePkg.
Move the PCD from MdeModulePkg.dec to PcAtChipsetPkg.dec removes
such dependency.

Signed-off-by: Ray Ni 
Cc: Hao A Wu 
---
 PcAtChipsetPkg/PcAtChipsetPkg.dec   | 6 +-
 .../PcatRealTimeClockRuntimeDxe.inf | 5 ++---
 2 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/PcAtChipsetPkg/PcAtChipsetPkg.dec 
b/PcAtChipsetPkg/PcAtChipsetPkg.dec
index d99d91496b..aad53b07c8 100644
--- a/PcAtChipsetPkg/PcAtChipsetPkg.dec
+++ b/PcAtChipsetPkg/PcAtChipsetPkg.dec
@@ -4,7 +4,7 @@
 # This package is designed to public interfaces and implementation which 
follows
 # PcAt defacto standard.
 #
-# Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2009 - 2019, Intel Corporation. All rights reserved.
 # Copyright (c) 2017, AMD Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -138,5 +138,9 @@ [PcdsFixedAtBuild, PcdsPatchableInModule]
   # @Prompt RTC Target Register address
   gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x71|UINT8|0x001F
 
+  ## RTC Update Timeout Value(microsecond).
+  # @Prompt RTC Update Timeout Value.
+  
gPcAtChipsetPkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout|10|UINT32|0x0020
+
 [UserExtensions.TianoCore."ExtraFiles"]
   PcAtChipsetPkgExtra.uni
diff --git 
a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf 
b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
index 9a0948be70..c73ee98105 100644
--- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
@@ -4,7 +4,7 @@
 # This driver provides GetTime, SetTime, GetWakeupTime, SetWakeupTime services 
to Runtime Service Table.
 # It will install a tagging protocol with gEfiRealTimeClockArchProtocolGuid.
 #
-# Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.
+# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.
 # Copyright (c) 2017, AMD Inc. All rights reserved.
 #
 # SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -33,7 +33,6 @@ [Sources]
 
 [Packages]
   MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
   PcAtChipsetPkg/PcAtChipsetPkg.dec
 
 [LibraryClasses]
@@ -68,7 +67,7 @@ [FixedPcd]
   gPcAtChipsetPkgTokenSpaceGuid.PcdInitialValueRtcRegisterD ## CONSUMES
 
 [Pcd]
-  gEfiMdeModulePkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout  ## CONSUMES
+  gPcAtChipsetPkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout   ## CONSUMES
   gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear ## CONSUMES
   gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear ## CONSUMES
   gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister ## CONSUMES
-- 
2.21.0.windows.1


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[edk2-devel] [PATCH 0/2] move PcdRealTimeClockUpdateTimeout from MdeModulePkg to PcAtChipsetPkg

[Ni, Ray]

Ray Ni (2):
  PcAtChipsetPkg: add PcdRealTimeClockUpdateTimeout
  MdeModulePkg: Remove PcdRealTimeClockUpdateTimeout

 MdeModulePkg/MdeModulePkg.dec   | 4 
 PcAtChipsetPkg/PcAtChipsetPkg.dec   | 6 +-
 .../PcatRealTimeClockRuntimeDxe.inf | 5 ++---
 3 files changed, 7 insertions(+), 8 deletions(-)

-- 
2.21.0.windows.1


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[edk2-devel] [PATCH 2/2] MdeModulePkg: Remove PcdRealTimeClockUpdateTimeout

[Ni, Ray]

The PCD is moved to PcAtChipsetPkg so remove it from
MdeModulePkg.
Signed-off-by: Ray Ni 
Cc: Hao A Wu 
Cc: Jian J Wang 
---
 MdeModulePkg/MdeModulePkg.dec | 4 
 1 file changed, 4 deletions(-)

diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec
index 19935c88fa..17beb45235 100644
--- a/MdeModulePkg/MdeModulePkg.dec
+++ b/MdeModulePkg/MdeModulePkg.dec
@@ -1128,10 +1128,6 @@ [PcdsFixedAtBuild, PcdsPatchableInModule]
   # @Prompt Maximum number of PEI performance log entries.
   
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries16|0|UINT16|0x00010035
 
-  ## RTC Update Timeout Value(microsecond).
-  # @Prompt RTC Update Timeout Value.
-  
gEfiMdeModulePkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout|10|UINT32|0x00010034
-
   ## Indicates the 16550 serial port registers are in MMIO space, or in I/O 
space. Default is I/O space.
   #   TRUE  - 16550 serial port registers are in MMIO space.
   #   FALSE - 16550 serial port registers are in I/O space.
-- 
2.21.0.windows.1


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Re: [edk2-devel] [PATCH] IntelFsp2Pkg/FspSecCore: Remove unneeded MdeModulePkg dependency

[Nate DeSimone]

Actually, please make sure you update copyright year on FspSecCoreT.inf. With 
that change...

Reviewed-by: Nate DeSimone 

-Original Message-
From: Ni, Ray 
Sent: Tuesday, August 27, 2019 3:41 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L 
; Zeng, Star 
Subject: [PATCH] IntelFsp2Pkg/FspSecCore: Remove unneeded MdeModulePkg 
dependency

Signed-off-by: Ray Ni 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
---
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 1 -  
IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf | 1 -  
IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf | 1 -
 3 files changed, 3 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
index 571ed9bc44..25f2a109ab 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
@@ -40,7 +40,6 @@ [Binaries.Ia32]
 
 [Packages]
   MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
   IntelFsp2Pkg/IntelFsp2Pkg.dec
 
 [LibraryClasses]
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
index 17924b118c..1d9c2554d1 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
@@ -35,7 +35,6 @@ [Binaries.Ia32]
 
 [Packages]
   MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
   IntelFsp2Pkg/IntelFsp2Pkg.dec
 
 [LibraryClasses]
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
index e66ea4593b..6f65e69e77 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
@@ -34,7 +34,6 @@ [Binaries.Ia32]
 
 [Packages]
   MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
   IntelFsp2Pkg/IntelFsp2Pkg.dec
 
 [LibraryClasses]
--
2.21.0.windows.1


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Re: [edk2-devel] [PATCH] IntelFsp2Pkg/FspSecCore: Remove unneeded MdeModulePkg dependency

[Nate DeSimone]

Reviewed-by: Nate DeSimone 

-Original Message-
From: Ni, Ray 
Sent: Tuesday, August 27, 2019 3:41 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel ; Desimone, Nathaniel L 
; Zeng, Star 
Subject: [PATCH] IntelFsp2Pkg/FspSecCore: Remove unneeded MdeModulePkg 
dependency

Signed-off-by: Ray Ni 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
---
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 1 -  
IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf | 1 -  
IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf | 1 -
 3 files changed, 3 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
index 571ed9bc44..25f2a109ab 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
@@ -40,7 +40,6 @@ [Binaries.Ia32]
 
 [Packages]
   MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
   IntelFsp2Pkg/IntelFsp2Pkg.dec
 
 [LibraryClasses]
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
index 17924b118c..1d9c2554d1 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
@@ -35,7 +35,6 @@ [Binaries.Ia32]
 
 [Packages]
   MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
   IntelFsp2Pkg/IntelFsp2Pkg.dec
 
 [LibraryClasses]
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
index e66ea4593b..6f65e69e77 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
@@ -34,7 +34,6 @@ [Binaries.Ia32]
 
 [Packages]
   MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
   IntelFsp2Pkg/IntelFsp2Pkg.dec
 
 [LibraryClasses]
--
2.21.0.windows.1


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Re: [edk2-devel] [edk2-platforms][PATCH V3 2/2] WhiskeylakeOpenBoardPkg: Fix GCC Build Failures

[Nate DeSimone]

Hi Michael,

Your responses address my comments from PATCH V2 as well. If Chasel has no 
further comments, go ahead and send a PATCH V4 and I will provide a reviewed-by.

Thanks,
Nate

-Original Message-
From: Kubacki, Michael A 
Sent: Monday, August 26, 2019 7:45 PM
To: Chiu, Chasel ; devel@edk2.groups.io
Cc: Desimone, Nathaniel L ; Gao, Liming 

Subject: RE: [edk2-platforms][PATCH V3 2/2] WhiskeylakeOpenBoardPkg: Fix GCC 
Build Failures

My responses are inline [makubacki]. I will wait for your response before I 
send the next patchset.

Thanks,
Michael

> -Original Message-
> From: Chiu, Chasel
> Sent: Monday, August 26, 2019 7:14 PM
> To: Kubacki, Michael A ;
> devel@edk2.groups.io
> Cc: Desimone, Nathaniel L ; Gao, Liming
> 
> Subject: RE: [edk2-platforms][PATCH V3 2/2] WhiskeylakeOpenBoardPkg: Fix
> GCC Build Failures
> 
> 
> Please see 3 questions below inline. (tagged by [chasel])
> 
> Thanks!
> Chasel
> 
> 
> > -Original Message-
> > From: Kubacki, Michael A
> > Sent: Tuesday, August 27, 2019 2:48 AM
> > To: devel@edk2.groups.io
> > Cc: Chiu, Chasel ; Desimone, Nathaniel L
> > ; Gao, Liming 
> > Subject: [edk2-platforms][PATCH V3 2/2] WhiskeylakeOpenBoardPkg: Fix
> GCC
> > Build Failures
> >
> > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2110
> >
> > Fixes build failures on GCC7.3.0. Tested on Ubunutu 18.04.1 LTS.
> >
> > Cc: Chasel Chiu 
> > Cc: Nate DeSimone 
> > Cc: Liming Gao 
> > Signed-off-by: Michael Kubacki 
> > ---
> >  Platform/Intel/WhiskeylakeOpenBoardPkg/OpenBoardPkg.dec
> > |   6 +-
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei
> H
> > daVerbTableLib.inf |   1 +
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> I
> > nitLib/PeiBoardInitPostMemLib.inf   |   8 +-
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> I
> > nitLib/PeiMultiBoardInitPostMemLib.inf  |   2 +
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> I
> > nitLib/PeiMultiBoardInitPreMemLib.inf   |  12 +-
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/Include/PcieDeviceOverrideTabl
> e.
> > h |   2 +-
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Include/Whis
> k
> > eylakeURvpId.h   |  12 -
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> I
> > nitLib/BoardFunc.h  |   2 +
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> I
> > nitLib/PeiWhiskeylakeURvpInitLib.h  |  41 -
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> I
> > nitLib/WhiskeylakeURvpInit.h|  41 +
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/FspWrapper/Library/PeiFspPolic
> yI
> > nitLib/PeiFspCpuPolicyInitLib.c   |   4 +-
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/Library/BaseGpioExpanderLib/Ba
> > seGpioExpanderLib.c |   6 +-
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/{Pc
> h
> > HdaVerbTables.h => PchHdaVerbTables.c} | 963
> > +---
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/Library/PeiHdaVerbTableLib/Pei
> H
> > daVerbTableLib.c   |   7 +-
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi
> b
> > /PeiPchPolicyUpdate.c|   6 -
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/Library/PeiPolicyUpdateLi
> b
> > /PeiSaPolicyUpdatePreMem.c   |  15 +-
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/Policy/PolicyInitDxe/BoardInitLib
> .
> > c   |   4 -
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> A
> > cpiLib/SmmMultiBoardAcpiSupportLib.c|   2 +-
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> A
> > cpiLib/SmmWhiskeylakeURvpAcpiEnableLib.c|   2 +-
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> I
> > nitLib/BoardFuncInit.c  |   1 -
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> I
> > nitLib/BoardFuncInitPreMem.c|   1 -
> >
> >
> Platform/Intel/WhiskeylakeOpenBoardPkg/WhiskeylakeURvp/Library/Board
> I
> > nitLib/BoardPchInitPreMemLib.c  |  12 +-
> >
> >
> 

[edk2-devel] [PATCH] IntelFsp2Pkg/FspSecCore: Remove unneeded MdeModulePkg dependency

[Ni, Ray]

Signed-off-by: Ray Ni 
Cc: Chasel Chiu 
Cc: Nate DeSimone 
Cc: Star Zeng 
---
 IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf | 1 -
 IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf | 1 -
 IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf | 1 -
 3 files changed, 3 deletions(-)

diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
index 571ed9bc44..25f2a109ab 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreM.inf
@@ -40,7 +40,6 @@ [Binaries.Ia32]
 
 [Packages]
   MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
   IntelFsp2Pkg/IntelFsp2Pkg.dec
 
 [LibraryClasses]
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
index 17924b118c..1d9c2554d1 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreS.inf
@@ -35,7 +35,6 @@ [Binaries.Ia32]
 
 [Packages]
   MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
   IntelFsp2Pkg/IntelFsp2Pkg.dec
 
 [LibraryClasses]
diff --git a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf 
b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
index e66ea4593b..6f65e69e77 100644
--- a/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
+++ b/IntelFsp2Pkg/FspSecCore/FspSecCoreT.inf
@@ -34,7 +34,6 @@ [Binaries.Ia32]
 
 [Packages]
   MdePkg/MdePkg.dec
-  MdeModulePkg/MdeModulePkg.dec
   IntelFsp2Pkg/IntelFsp2Pkg.dec
 
 [LibraryClasses]
-- 
2.21.0.windows.1


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Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)

[Michael D Kinney]

Leif,

Looking at the DSC Spec in looks like the priority
change from Aug 9 was to invert the priority 4 and
priority 5 items:

1.  associated with the INF file in the [Components] section
2. [LibraryClasses.$(Arch).$(MODULE_TYPE), 
LibraryClasses.$(Arch).$(MODULE_TYPE)]
3. [LibraryClasses.$(Arch).$(MODULE_TYPE)]
4. [LibraryClasses.common.$(MODULE_TYPE)]
5. [LibraryClasses.$(Arch)]
6. [LibraryClasses.common] or [LibraryClasses]

If BaseTools were updated to make (5) higher priority than (4),
then the previous behavior would be restored and no DSC file 
changes would be required.  This means an arch specific mapping
for all module types is higher priority than a module specific
mapping for all archs.

We can update DSC Spec to match the behavior that has been
implemented for a long time.

Mike

> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io]
> On Behalf Of Leif Lindholm
> Sent: Tuesday, August 27, 2019 1:59 PM
> To: Laszlo Ersek 
> Cc: devel@edk2.groups.io; Andrew Fish ;
> Kinney, Michael D ; Baptiste
> Gerondeau ; Wang, Jian J
> ; Wu, Hao A ;
> Feng, Bob C ; Gao, Liming
> 
> Subject: Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix
> !x86 builds (more)
> 
> +Bob, Liming,
> 
> On Tue, Aug 27, 2019 at 09:26:05PM +0200, Laszlo Ersek
> wrote:
> > Hi Leif,
> >
> > On 08/27/19 14:43, Leif Lindholm wrote:
> > > Commit 4a1f6b85c184
> > > ("MdeModulePkg: add LockBoxNullLib for !IA32/X64 in
> .dsc") added an
> > > ARM/AARCH64 resolution for LockBoxLib. However, this
> failed to
> > > address the overrides provided for PEIM, DXE_DRIVER,
> > > DXE_RUNTIME_DRIVER, DXE_SMM_DRIVER and UEFI_DRIVER,
> so any modules
> > > of those classes still failed to build.
> > >
> > > Break these out properly into their own
> LibraryClasses sections.
> > >
> > > Resolves BZ:
> https://bugzilla.tianocore.org/show_bug.cgi?id=2134
> > >
> > > Signed-off-by: Leif Lindholm
> 
> > > Reported-by: Baptiste Gerondeau
> 
> > > Cc: Jian J Wang 
> > > Cc: Hao A Wu 
> > > ---
> > >
> > > I don't understand how the above would appear to
> work back when I
> > > submitted the previous patch but not work now, but I
> haven't dug
> > > into it deeper. Including the x86-specific
> LockBoxLib in the .common
> > > section is however clearly not correct.
> >
> > I agree with you that the present situation is not
> correct.
> >
> > According to:
> >
> >
> > https://edk2-docs.gitbooks.io/edk-ii-dsc-
> specification/2_dsc_overview/
> > 26_[libraryclasses]_section_processing.html
> >
> > the library class resolutions take effect in the
> following order
> > (entries near the top have higher priority):
> >
> > > 1.  associated with the INF file in
> the [Components]
> > > section 2. [LibraryClasses.$(Arch).$(MODULE_TYPE),
> > > LibraryClasses.$(Arch).$(MODULE_TYPE)]
> > > 3. [LibraryClasses.$(Arch).$(MODULE_TYPE)]
> > > 4. [LibraryClasses.common.$(MODULE_TYPE)]
> > > 5. [LibraryClasses.$(Arch)]
> > > 6. [LibraryClasses.common] or [LibraryClasses]
> >
> > (Side comment 1: levels #2 and #3 look very similar; I
> think the
> > difference is that #2 is supposed to be a multi-arch
> and/or
> > multi-module-type section, while #3 is a single-arch
> and
> > single-module-type section.)
> >
> > Commit 4a1f6b85c184 ("MdeModulePkg: add LockBoxNullLib
> for !IA32/X64
> > in .dsc", 2019-03-27) provided a LockBoxLib resolution
> at level #5:
> 
> Yes.
> 
> > > [LibraryClasses.ARM, LibraryClasses.AARCH64]
> >
> > However, the other LockBoxLib resolutions are at level
> #4:
> >
> > > [LibraryClasses.common.PEIM]
> > > [LibraryClasses.common.DXE_DRIVER]
> > > [LibraryClasses.common.DXE_RUNTIME_DRIVER]
> > > [LibraryClasses.common.DXE_SMM_DRIVER]
> > > [LibraryClasses.common.UEFI_DRIVER]
> >
> > So the latter taking priority is actually specified
> behavior.
> 
> Hmm. That's not great.
> Anyway, I stopped being lazy and did a bisect.
> 
> The culprit is
> e8449e1d8e3b ("BaseTools: Decouple AutoGen Objects"),
> marked as resolving
> https://bugzilla.tianocore.org/show_bug.cgi?id=1875.
> 
> This also affects SignedCapsulePkg/SignedCapsulePkg.dsc
> (although once addressed, AARCH64 also needs a NULL
> entry added for CompilerIntrinsicsLib.
> 
> > (Side comment 2: EBC is in the same boat, from commit
> cbcccd2c9d93
> > ("Update Code to pass EBC compiler", 2013-05-13):
> >
> > > [LibraryClasses.EBC]
> > >
> LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNu
> llLib.inf
> > )
> >
> > As to why this breakage was not exposed right at
> commit 4a1f6b85c184
> > -- I have no idea. Perhaps it was hidden by a
> BaseTools issue that has
> > been fixed meanwhile.
> 
> Yes.
> But it is also a fundamental change in tool behaviour
> introduced on 9 August. I am really uncomfortable about
> this making it into the release this week - but I also
> believe this is the foundation for the multiprocess
> autogen.
> 
> Since you have very helpfully analyzed *what* changed
> ... would the better "fix" for 2019.08 be to
> intentionally break the new code to 

Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)

[Michael D Kinney]

Laszlo,

Thanks for the analysis of the DSC Specification.

It appears a behavior change was introduced with the
following commit.

https://github.com/tianocore/edk2/commit/e8449e1d8e3b40186eb16ff25242397cffb00a63

The new code follows the DSC Specification, but 
changes the library selection priority.  The EBC
library class selection for LockBoxLib has been
the following for a long time:

[LibraryClasses.EBC]
  LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf

e8449e1d8e fails  for EBC for the SmmLockLock mapping
197ca7febf builds for EBC

We need to decide if we prefer the priority documented
in the DSC Specification or the priority in BaseTools
before e8449e1d8e.

We will likely need to wait a couple of hours for Liming
and Bob to be online and review this issue.

Best regards,

Mike

> -Original Message-
> From: devel@edk2.groups.io [mailto:devel@edk2.groups.io]
> On Behalf Of Laszlo Ersek
> Sent: Tuesday, August 27, 2019 12:26 PM
> To: Leif Lindholm ;
> devel@edk2.groups.io
> Cc: Andrew Fish ; Kinney, Michael D
> ; Baptiste Gerondeau
> ; Wang, Jian J
> ; Wu, Hao A 
> Subject: Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix
> !x86 builds (more)
> 
> Hi Leif,
> 
> On 08/27/19 14:43, Leif Lindholm wrote:
> > Commit 4a1f6b85c184
> > ("MdeModulePkg: add LockBoxNullLib for !IA32/X64 in
> .dsc") added an
> > ARM/AARCH64 resolution for LockBoxLib. However, this
> failed to address
> > the overrides provided for PEIM, DXE_DRIVER,
> DXE_RUNTIME_DRIVER,
> > DXE_SMM_DRIVER and UEFI_DRIVER, so any modules of
> those classes still
> > failed to build.
> >
> > Break these out properly into their own LibraryClasses
> sections.
> >
> > Resolves BZ:
> https://bugzilla.tianocore.org/show_bug.cgi?id=2134
> >
> > Signed-off-by: Leif Lindholm
> 
> > Reported-by: Baptiste Gerondeau
> 
> > Cc: Jian J Wang 
> > Cc: Hao A Wu 
> > ---
> >
> > I don't understand how the above would appear to work
> back when I
> > submitted the previous patch but not work now, but I
> haven't dug into
> > it deeper. Including the x86-specific LockBoxLib in
> the .common
> > section is however clearly not correct.
> 
> I agree with you that the present situation is not
> correct.
> 
> According to:
> 
>   https://edk2-docs.gitbooks.io/edk-ii-dsc-
> specification/2_dsc_overview/26_[libraryclasses]_section
> _processing.html
> 
> the library class resolutions take effect in the
> following order (entries near the top have higher
> priority):
> 
> > 1.  associated with the INF file in
> the [Components]
> > section 2. [LibraryClasses.$(Arch).$(MODULE_TYPE),
> > LibraryClasses.$(Arch).$(MODULE_TYPE)]
> > 3. [LibraryClasses.$(Arch).$(MODULE_TYPE)]
> > 4. [LibraryClasses.common.$(MODULE_TYPE)]
> > 5. [LibraryClasses.$(Arch)]
> > 6. [LibraryClasses.common] or [LibraryClasses]
> 
> (Side comment 1: levels #2 and #3 look very similar; I
> think the difference is that #2 is supposed to be a
> multi-arch and/or multi-module-type section, while #3 is
> a single-arch and single-module-type section.)
> 
> Commit 4a1f6b85c184 ("MdeModulePkg: add LockBoxNullLib
> for !IA32/X64 in .dsc", 2019-03-27) provided a
> LockBoxLib resolution at level #5:
> 
> > [LibraryClasses.ARM, LibraryClasses.AARCH64]
> 
> However, the other LockBoxLib resolutions are at level
> #4:
> 
> > [LibraryClasses.common.PEIM]
> > [LibraryClasses.common.DXE_DRIVER]
> > [LibraryClasses.common.DXE_RUNTIME_DRIVER]
> > [LibraryClasses.common.DXE_SMM_DRIVER]
> > [LibraryClasses.common.UEFI_DRIVER]
> 
> So the latter taking priority is actually specified
> behavior.
> 
> (Side comment 2: EBC is in the same boat, from commit
> cbcccd2c9d93 ("Update Code to pass EBC compiler", 2013-
> 05-13):
> 
> > [LibraryClasses.EBC]
> >
> LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNu
> llLib.inf
> )
> 
> As to why this breakage was not exposed right at commit
> 4a1f6b85c184 -- I have no idea. Perhaps it was hidden by
> a BaseTools issue that has been fixed meanwhile.
> 
> On 08/27/19 14:43, Leif Lindholm wrote:
> > I think a fix for this issue needs to go into 2019.08,
> 
> I agree the problem should be fixed in 2019.08 -- taking
> your word that commit 4a1f6b85c184 *appeared* to fix the
> MdeModulePkg.dsc build for ARM/AARCH64, we now have a
> regression since that commit (dated 2019-03-27).
> 
> > but if someone has a prettier suggestion, I am not
> wedded to this one.
> 
> I think this is good enough. The lib class resolutions
> are raised to level #2, but they will no longer match
> ARM / AARCH64, so your level#5 addition from commit
> 4a1f6b85c184 will take effect.
> 
> >
> >  MdeModulePkg/MdeModulePkg.dsc | 16 +---
> >  1 file changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/MdeModulePkg/MdeModulePkg.dsc
> > b/MdeModulePkg/MdeModulePkg.dsc index
> 4320839abfb5..15ba96cecbed
> > 100644
> > --- a/MdeModulePkg/MdeModulePkg.dsc
> > +++ b/MdeModulePkg/MdeModulePkg.dsc
> > @@ -109,6 +109,8 @@ [LibraryClasses.common.PEIM]
> >

Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)

[Leif Lindholm]

+Bob, Liming,

On Tue, Aug 27, 2019 at 09:26:05PM +0200, Laszlo Ersek wrote:
> Hi Leif,
> 
> On 08/27/19 14:43, Leif Lindholm wrote:
> > Commit 4a1f6b85c184
> > ("MdeModulePkg: add LockBoxNullLib for !IA32/X64 in .dsc")
> > added an ARM/AARCH64 resolution for LockBoxLib. However, this failed
> > to address the overrides provided for PEIM, DXE_DRIVER,
> > DXE_RUNTIME_DRIVER, DXE_SMM_DRIVER and UEFI_DRIVER, so any modules
> > of those classes still failed to build.
> >
> > Break these out properly into their own LibraryClasses sections.
> >
> > Resolves BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2134
> >
> > Signed-off-by: Leif Lindholm 
> > Reported-by: Baptiste Gerondeau 
> > Cc: Jian J Wang 
> > Cc: Hao A Wu 
> > ---
> >
> > I don't understand how the above would appear to work back when I
> > submitted the previous patch but not work now, but I haven't dug
> > into it deeper. Including the x86-specific LockBoxLib in the
> > .common section is however clearly not correct.
> 
> I agree with you that the present situation is not correct.
> 
> According to:
> 
>   
> https://edk2-docs.gitbooks.io/edk-ii-dsc-specification/2_dsc_overview/26_[libraryclasses]_section_processing.html
> 
> the library class resolutions take effect in the following order
> (entries near the top have higher priority):
> 
> > 1.  associated with the INF file in the [Components] section
> > 2. [LibraryClasses.$(Arch).$(MODULE_TYPE), 
> > LibraryClasses.$(Arch).$(MODULE_TYPE)]
> > 3. [LibraryClasses.$(Arch).$(MODULE_TYPE)]
> > 4. [LibraryClasses.common.$(MODULE_TYPE)]
> > 5. [LibraryClasses.$(Arch)]
> > 6. [LibraryClasses.common] or [LibraryClasses]
> 
> (Side comment 1: levels #2 and #3 look very similar; I think the
> difference is that #2 is supposed to be a multi-arch and/or
> multi-module-type section, while #3 is a single-arch and
> single-module-type section.)
> 
> Commit 4a1f6b85c184 ("MdeModulePkg: add LockBoxNullLib for !IA32/X64 in
> .dsc", 2019-03-27) provided a LockBoxLib resolution at level #5:

Yes.

> > [LibraryClasses.ARM, LibraryClasses.AARCH64]
> 
> However, the other LockBoxLib resolutions are at level #4:
> 
> > [LibraryClasses.common.PEIM]
> > [LibraryClasses.common.DXE_DRIVER]
> > [LibraryClasses.common.DXE_RUNTIME_DRIVER]
> > [LibraryClasses.common.DXE_SMM_DRIVER]
> > [LibraryClasses.common.UEFI_DRIVER]
> 
> So the latter taking priority is actually specified behavior.

Hmm. That's not great.
Anyway, I stopped being lazy and did a bisect.

The culprit is
e8449e1d8e3b ("BaseTools: Decouple AutoGen Objects"), marked as
resolving https://bugzilla.tianocore.org/show_bug.cgi?id=1875.

This also affects SignedCapsulePkg/SignedCapsulePkg.dsc (although once
addressed, AARCH64 also needs a NULL entry added for
CompilerIntrinsicsLib.

> (Side comment 2: EBC is in the same boat, from commit cbcccd2c9d93
> ("Update Code to pass EBC compiler", 2013-05-13):
> 
> > [LibraryClasses.EBC]
> >   LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
> )
> 
> As to why this breakage was not exposed right at commit 4a1f6b85c184 --
> I have no idea. Perhaps it was hidden by a BaseTools issue that has been
> fixed meanwhile.

Yes.
But it is also a fundamental change in tool behaviour introduced on 9
August. I am really uncomfortable about this making it into the
release this week - but I also believe this is the foundation for the
multiprocess autogen.

Since you have very helpfully analyzed *what* changed ... would the
better "fix" for 2019.08 be to intentionally break the new code to
conform to the old behaviour - and then revert that patch after the
tag?

If we do that, this patch could then wait and indeed be merged as part
of the same set.

> On 08/27/19 14:43, Leif Lindholm wrote:
> > I think a fix for this issue needs to go into 2019.08,
> 
> I agree the problem should be fixed in 2019.08 -- taking your word that
> commit 4a1f6b85c184 *appeared* to fix the MdeModulePkg.dsc build for
> ARM/AARCH64, we now have a regression since that commit (dated
> 2019-03-27).
> 
> > but if someone has a prettier suggestion, I am not wedded to this one.
> 
> I think this is good enough. The lib class resolutions are raised to
> level #2, but they will no longer match ARM / AARCH64, so your level#5
> addition from commit 4a1f6b85c184 will take effect.
> 
> >
> >  MdeModulePkg/MdeModulePkg.dsc | 16 +---
> >  1 file changed, 13 insertions(+), 3 deletions(-)
> >
> > diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc
> > index 4320839abfb5..15ba96cecbed 100644
> > --- a/MdeModulePkg/MdeModulePkg.dsc
> > +++ b/MdeModulePkg/MdeModulePkg.dsc
> > @@ -109,6 +109,8 @@ [LibraryClasses.common.PEIM]
> >HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
> >
> > MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
> >
> > ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
> > +
> > 

Re: [edk2-rfc] [edk2-devel] CPU hotplug using SMM with QEMU+OVMF

[Laszlo Ersek]

On 08/27/19 18:23, Igor Mammedov wrote:
> On Mon, 26 Aug 2019 17:30:43 +0200
> Laszlo Ersek  wrote:
> 
>> On 08/23/19 17:25, Kinney, Michael D wrote:
>>> Hi Jiewen,
>>>
>>> If a hot add CPU needs to run any code before the
>>> first SMI, I would recommend is only executes code
>>> from a write protected FLASH range without a stack
>>> and then wait for the first SMI.  
>>
>> "without a stack" looks very risky to me. Even if we manage to implement
>> the guest code initially, we'll be trapped without a stack, should we
>> ever need to add more complex stuff there.
> 
> Do we need anything complex in relocation handler, though?
> From what I'd imagine, minimum handler should
>   1: get address of TSEG, possibly read it from chipset

The TSEG base calculation is not trivial in this environment. The 32-bit
RAM size needs to be read from the CMOS (IO port accesses). Then the
extended TSEG size (if any) needs to be detected from PCI config space
(IO port accesses). Both CMOS and PCI config space requires IO port
writes too (not just reads). Even if there are enough registers for the
calculations, can we rely on these unprotected IO ports?

Also, can we switch to 32-bit mode without a stack? I assume it would be
necessary to switch to 32-bit mode for 32-bit arithmetic.

Getting the initial APIC ID needs some CPUID instructions IIUC, which
clobber EAX through EDX, if I understand correctly. Given the register
pressure, CPUID might have to be one of the first instructions to call.

>   2: calculate its new SMBASE offset based on its APIC ID
>   3: save new SMBASE
> 
>>> For this OVMF use case, is any CPU init required
>>> before the first SMI?  
>>
>> I expressed a preference for that too: "I wish we could simply wake the
>> new CPU [...] with an SMI".
>>
>> 398b3327-0820-95af-a34d-1a4a1d50cf35@redhat.com">http://mid.mail-archive.com/398b3327-0820-95af-a34d-1a4a1d50cf35@redhat.com
>>
>>
>>> From Paolo's list of steps are steps (8a) and (8b) 
>>> really required?  
> 
> 07b - implies 08b

I agree about that implication, yes. *If* we send an INIT/SIPI/SIPI to
the new CPU, then the new CPU needs a HLT loop, I think.

>8b could be trivial hlt loop and we most likely could skip 08a and 
> signaling host CPU steps
>but we need INIT/SIPI/SIPI sequence to wake up AP so it could handle 
> pending SMI
>before handling SIPI (so behavior would follow SDM).
> 
> 
>> See again my message linked above -- just after the quoted sentence, I
>> wrote, "IOW, if we could excise steps 07b, 08a, 08b".
>>
>> But, I obviously defer to Paolo and Igor on that.
>>
>> (I do believe we have a dilemma here. In QEMU, we probably prefer to
>> emulate physical hardware as faithfully as possible. However, we do not
>> have Cache-As-RAM (nor do we intend to, IIUC). Does that justify other
>> divergences from physical hardware too, such as waking just by virtue of
>> an SMI?)
> So far we should be able to implement it per spec (at least SDM one),
> but we would still need to invent chipset hardware
> i.e. like adding to Q35 non exiting SMRAM and means to map/unmap it
> to non-SMM address space.
> (and I hope we could avoid adding "parked CPU" thingy)

I think we'll need a separate QEMU tree for this. I'm quite in the dark
-- I can't tell if I'll be able to do something in OVMF without actually
trying it. And for that, we'll need some proposed QEMU code that is
testable, but not upstream yet. (As I might realize that I'm unable to
make it work in OVMF.)

>>> Can the SMI monarch use the Local
>>> APIC to send a directed SMI to the hot added CPU?
>>> The SMI monarch needs to know the APIC ID of the
>>> hot added CPU.  Do we also need to handle the case
>>> where multiple CPUs are added at once?  I think we
>>> would need to serialize the use of 3000:8000 for the
>>> SMM rebase operation on each hot added CPU.  
>>
>> I agree this would be a huge help.
> 
> We can serialize it (for normal hotplug flow) from ACPI handler
> in the guest (i.e. non enforced serialization).
> The only reason for serialization I see is not to allow
> a bunch of new CPU trample over default SMBASE save area
> at the same time.

If the default SMBASE area is corrupted due to concurrent access, could
that lead to invalid relocated SMBASE values? Possibly pointing into
normal RAM?

Thanks
Laszlo

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Re: edk2-stable201908 Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)

[Leif Lindholm]

On Tue, Aug 27, 2019 at 09:28:50PM +0200, Laszlo Ersek wrote:
> On 08/27/19 17:50, Leif Lindholm wrote:
> > Apologies, forgot to tag the subject for stable release (although I
> > did remember to cc the stewards).
> 
> Understood, thus far... (And I commented on the target release under
> your original submission.)
> 
> > We don't appear to have a fix version for edk2-stable201908 in
> > bugzilla, though.
> 
> I don't get this paragraph. What is "fix version for edk2-stable201908"?

The freeze announcement said bugzillas aiming for inclusion in the
stable tag should also be marked accordingly.

I choose to interpret this as the "Release(s) the issues must be
fixed:" field should be set to the corresponding target release tag.
But the most recent version selectable there is edk2-stable201905.

/
Leif

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Re: edk2-stable201908 Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)

[Laszlo Ersek]

On 08/27/19 17:50, Leif Lindholm wrote:
> Apologies, forgot to tag the subject for stable release (although I
> did remember to cc the stewards).

Understood, thus far... (And I commented on the target release under
your original submission.)

> We don't appear to have a fix version for edk2-stable201908 in
> bugzilla, though.

I don't get this paragraph. What is "fix version for edk2-stable201908"?

Thanks
Laszlo

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Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)

[Laszlo Ersek]

Hi Leif,

On 08/27/19 14:43, Leif Lindholm wrote:
> Commit 4a1f6b85c184
> ("MdeModulePkg: add LockBoxNullLib for !IA32/X64 in .dsc")
> added an ARM/AARCH64 resolution for LockBoxLib. However, this failed
> to address the overrides provided for PEIM, DXE_DRIVER,
> DXE_RUNTIME_DRIVER, DXE_SMM_DRIVER and UEFI_DRIVER, so any modules
> of those classes still failed to build.
>
> Break these out properly into their own LibraryClasses sections.
>
> Resolves BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2134
>
> Signed-off-by: Leif Lindholm 
> Reported-by: Baptiste Gerondeau 
> Cc: Jian J Wang 
> Cc: Hao A Wu 
> ---
>
> I don't understand how the above would appear to work back when I
> submitted the previous patch but not work now, but I haven't dug
> into it deeper. Including the x86-specific LockBoxLib in the
> .common section is however clearly not correct.

I agree with you that the present situation is not correct.

According to:

  
https://edk2-docs.gitbooks.io/edk-ii-dsc-specification/2_dsc_overview/26_[libraryclasses]_section_processing.html

the library class resolutions take effect in the following order
(entries near the top have higher priority):

> 1.  associated with the INF file in the [Components] section
> 2. [LibraryClasses.$(Arch).$(MODULE_TYPE), 
> LibraryClasses.$(Arch).$(MODULE_TYPE)]
> 3. [LibraryClasses.$(Arch).$(MODULE_TYPE)]
> 4. [LibraryClasses.common.$(MODULE_TYPE)]
> 5. [LibraryClasses.$(Arch)]
> 6. [LibraryClasses.common] or [LibraryClasses]

(Side comment 1: levels #2 and #3 look very similar; I think the
difference is that #2 is supposed to be a multi-arch and/or
multi-module-type section, while #3 is a single-arch and
single-module-type section.)

Commit 4a1f6b85c184 ("MdeModulePkg: add LockBoxNullLib for !IA32/X64 in
.dsc", 2019-03-27) provided a LockBoxLib resolution at level #5:

> [LibraryClasses.ARM, LibraryClasses.AARCH64]

However, the other LockBoxLib resolutions are at level #4:

> [LibraryClasses.common.PEIM]
> [LibraryClasses.common.DXE_DRIVER]
> [LibraryClasses.common.DXE_RUNTIME_DRIVER]
> [LibraryClasses.common.DXE_SMM_DRIVER]
> [LibraryClasses.common.UEFI_DRIVER]

So the latter taking priority is actually specified behavior.

(Side comment 2: EBC is in the same boat, from commit cbcccd2c9d93
("Update Code to pass EBC compiler", 2013-05-13):

> [LibraryClasses.EBC]
>   LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf
)

As to why this breakage was not exposed right at commit 4a1f6b85c184 --
I have no idea. Perhaps it was hidden by a BaseTools issue that has been
fixed meanwhile.

On 08/27/19 14:43, Leif Lindholm wrote:
> I think a fix for this issue needs to go into 2019.08,

I agree the problem should be fixed in 2019.08 -- taking your word that
commit 4a1f6b85c184 *appeared* to fix the MdeModulePkg.dsc build for
ARM/AARCH64, we now have a regression since that commit (dated
2019-03-27).

> but if someone has a prettier suggestion, I am not wedded to this one.

I think this is good enough. The lib class resolutions are raised to
level #2, but they will no longer match ARM / AARCH64, so your level#5
addition from commit 4a1f6b85c184 will take effect.

>
>  MdeModulePkg/MdeModulePkg.dsc | 16 +---
>  1 file changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc
> index 4320839abfb5..15ba96cecbed 100644
> --- a/MdeModulePkg/MdeModulePkg.dsc
> +++ b/MdeModulePkg/MdeModulePkg.dsc
> @@ -109,6 +109,8 @@ [LibraryClasses.common.PEIM]
>HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
>
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
>
> ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
> +
> +[LibraryClasses.IA32.PEIM,LibraryClasses.X64.PEIM]
>LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf

(1) I suggest replacing "," with ", ". (That's more consistent with
preexistent section headers in the DSC file.) Applies to the other new
section headers too.

>
>  [LibraryClasses.common.DXE_CORE]
> @@ -118,18 +120,22 @@ [LibraryClasses.common.DXE_CORE]
>
>  [LibraryClasses.common.DXE_DRIVER]
>HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> -  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
>
> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
>
> ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
>CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf
>
> +[LibraryClasses.IA32.DXE_DRIVER,LibraryClasses.X64.DXE_DRIVER]
> +  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
> +
>  [LibraryClasses.common.DXE_RUNTIME_DRIVER]
>HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
>
> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
>

Re: [edk2-devel] [PATCH] MdePkg/DxeHstiLib: Added checks to improve error handling.

[Jayanth.Raghuram]

Hi Liming,

I sent the review request based on the description in the links that you 
mentioned below.
I sent it in an Dell Email since I cannot use GIT SMTP to send email out from 
our servers.
Please let me know what is wrong and I can help rectify that.

Regards
Jayanth Raghuram
DellEMC | Server Platform BIOS
office + 1 512 723 1470

From: Gao, Liming 
Sent: Monday, August 26, 2019 8:57 PM
To: devel@edk2.groups.io; Raghuram, Jayanth
Cc: Liu, Wei G
Subject: RE: [PATCH] MdePkg/DxeHstiLib: Added checks to improve error handling.


[EXTERNAL EMAIL]
Can you follow this process to send this patch again?
https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Process

And, the commit message format is
https://github.com/tianocore/tianocore.github.io/wiki/Commit-Message-Format

Thanks
Liming
From: devel@edk2.groups.io 
[mailto:devel@edk2.groups.io] On Behalf Of 
jayanth.raghu...@dell.com
Sent: Tuesday, August 27, 2019 3:55 AM
To: devel@edk2.groups.io
Cc: wei.g@dell.com
Subject: [edk2-devel] [PATCH] MdePkg/DxeHstiLib: Added checks to improve error 
handling.

Subject: [PATCH] MdePkg/DxeHstiLib: Added checks to improve error handling.
Added checks for return parameters of LocateHandleBuffer & GetSupportedTypes
function calls in InternalHstiFindAip to improve error handling. An issue was
observed on Dell Poweredge R740, where the Dell PERC H740P controller UEFI
driver returned InfoTypesBuffer = NULL, InfoTypesBufferCount = 0 and caused
an FreePool assert.

Signed-off-by: Jayanth Raghuram 
mailto:jayanth.raghu...@dell.com>>
Cc: Wei G Liu mailto:wei_g_...@dell.com>>

Attached: 0001-MdePkg-DxeHstiLib-Added-checks-to-improve-error-hand.patch

Regards
Jayanth Raghuram
DellEMC | Server Platform BIOS
office + 1 512 723 1470



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Re: [edk2-rfc] [edk2-devel] CPU hotplug using SMM with QEMU+OVMF

[Igor Mammedov]

On Sat, 24 Aug 2019 01:48:09 +
"Yao, Jiewen"  wrote:

> I give my thought.
> Paolo may add more.
Here are some ideas I have on the topic.

> 
> > -Original Message-
> > From: Kinney, Michael D
> > Sent: Friday, August 23, 2019 11:25 PM
> > To: Yao, Jiewen ; Paolo Bonzini
> > ; Laszlo Ersek ;
> > r...@edk2.groups.io; Kinney, Michael D 
> > Cc: Alex Williamson ; devel@edk2.groups.io;
> > qemu devel list ; Igor Mammedov
> > ; Chen, Yingwen ;
> > Nakajima, Jun ; Boris Ostrovsky
> > ; Joao Marcal Lemos Martins
> > ; Phillip Goerl 
> > Subject: RE: [edk2-rfc] [edk2-devel] CPU hotplug using SMM with
> > QEMU+OVMF
> > 
> > Hi Jiewen,
> > 
> > If a hot add CPU needs to run any code before the
> > first SMI, I would recommend is only executes code
> > from a write protected FLASH range without a stack
> > and then wait for the first SMI.
> [Jiewen] Right.
> 
> Another option from Paolo, the new CPU will not run until 0x7b.
> To mitigate DMA threat, someone need guarantee the low memory SIPI vector is 
> DMA protected.
> 
> NOTE: The LOW memory *could* be mapped to write protected FLASH AREA via PAM 
> register. The Host CPU may setup that in SMM.
> If that is the case, we don’t need worry DMA.
> 
> I copied the detail step here, because I found it is hard to dig them out 
> again.

*) In light of using dedicated SMRAM at 3 with pre-configured
relocation vector for initial relocation which is not reachable from
non-SMM mode:

> 
> (01a) QEMU: create new CPU.  The CPU already exists, but it does not
>  start running code until unparked by the CPU hotplug controller.
we might not need parked CPU (if we ignore attacker's attempt to send
SMI to several new CPUs, see below for issue it causes)

> (01b) QEMU: trigger SCI
> 
> (02-03) no equivalent
> 
> (04) Host CPU: (OS) execute GPE handler from DSDT
> 
> (05) Host CPU: (OS) Port 0xB2 write, all CPUs enter SMM (NOTE: New CPU
>  will not enter CPU because SMI is disabled)
I think only CPU that does the write will enter SMM
and we might not need to pull in all already initialized CPUs into SMM.

At this step we could also send a directed SMI to a new CPU from host
CPU that entered SMM on write.

> (06) Host CPU: (SMM) Save 38000, Update 38000 -- fill simple SMM
>  rebase code.
could skip this step as well (*)


> (07a) Host CPU: (SMM) Write to CPU hotplug controller to enable
>  new CPU
ditto
 
> (07b) Host CPU: (SMM) Send INIT/SIPI/SIPI to new CPU.
we need to wake up new CPU somehow so it would process (09) pending (05) SMI
before jumping to SIPI vector

> (08a) New CPU: (Low RAM) Enter protected mode.
> 
> (08b) New CPU: (Flash) Signals host CPU to proceed and enter cli;hlt loop.

these both steps could be changed to to just cli;hlt loop or do INIT reset.
if SMI relocation handler and/or host CPU will pull in the new CPU into OVMF,
we actually don't care about SIPI vector as all firmware initialization
for the new CPU is done in SMM mode (07b triggers 10).
Thus eliminating one attack vector to protect from.

> (09) Host CPU: (SMM) Send SMI to the new CPU only.
could be done at (05)
 
> (10) New CPU: (SMM) Run SMM code at 38000, and rebase SMBASE to
>  TSEG.
it could also pull in itself into other OVMF structures
(assuming it can TSEG as stack as that's rather complex) or
just do relocation and let host CPU to fill in OVMF structures for the new CPU 
(12).

> (11) Host CPU: (SMM) Restore 38000.
could skip this step as well (*)

> (12) Host CPU: (SMM) Update located data structure to add the new CPU
>  information. (This step will involve CPU_SERVICE protocol)
> 
> (13) New CPU: (Flash) do whatever other initialization is needed
do we actually need it?

> (14) New CPU: (Flash) Deadloop, and wait for INIT-SIPI-SIPI.
> 
> (15) Host CPU: (OS) Send INIT-SIPI-SIPI to pull new CPU in..
> 
> 
> > 
> > For this OVMF use case, is any CPU init required
> > before the first SMI?
> [Jiewen] I am sure what is the detail action in 08b.
> And I am not sure what your "init" means here?
> Personally, I don’t think we need too much init work, such as Microcode or 
> MTRR.
> But we need detail info.
Wouldn't it be preferable to do in SMM mode?

> > From Paolo's list of steps are steps (8a) and (8b)
> > really required?  Can the SMI monarch use the Local
> > APIC to send a directed SMI to the hot added CPU?
> > The SMI monarch needs to know the APIC ID of the
> > hot added CPU.
> [Jiewen] I think it depend upon virtual hardware design.
> Leave question to Paolo.

it's not really needed as described in (8x), it could be just
cli;hlt loop so that our SIPI could land at sensible code and stop the new CPU,
it even could be an attacker's code if we do all initialization in SMM mode.

> Do we also need to handle the case
> > where multiple CPUs are added at once?  I think we
> > would need to serialize the use of 3000:8000 for the
> > SMM rebase operation on each hot added CPU.
> > It would be simpler if we can 

Re: [edk2-rfc] [edk2-devel] CPU hotplug using SMM with QEMU+OVMF

[Igor Mammedov]

On Mon, 26 Aug 2019 17:30:43 +0200
Laszlo Ersek  wrote:

> On 08/23/19 17:25, Kinney, Michael D wrote:
> > Hi Jiewen,
> > 
> > If a hot add CPU needs to run any code before the
> > first SMI, I would recommend is only executes code
> > from a write protected FLASH range without a stack
> > and then wait for the first SMI.
> 
> "without a stack" looks very risky to me. Even if we manage to implement
> the guest code initially, we'll be trapped without a stack, should we
> ever need to add more complex stuff there.

Do we need anything complex in relocation handler, though?
>From what I'd imagine, minimum handler should
  1: get address of TSEG, possibly read it from chipset
  2: calculate its new SMBASE offset based on its APIC ID
  3: save new SMBASE

> > For this OVMF use case, is any CPU init required
> > before the first SMI?
> 
> I expressed a preference for that too: "I wish we could simply wake the
> new CPU [...] with an SMI".
> 
> 398b3327-0820-95af-a34d-1a4a1d50cf35@redhat.com">http://mid.mail-archive.com/398b3327-0820-95af-a34d-1a4a1d50cf35@redhat.com
> 
> 
> > From Paolo's list of steps are steps (8a) and (8b) 
> > really required?

07b - implies 08b
   8b could be trivial hlt loop and we most likely could skip 08a and signaling 
host CPU steps
   but we need INIT/SIPI/SIPI sequence to wake up AP so it could handle pending 
SMI
   before handling SIPI (so behavior would follow SDM).


> See again my message linked above -- just after the quoted sentence, I
> wrote, "IOW, if we could excise steps 07b, 08a, 08b".
> 
> But, I obviously defer to Paolo and Igor on that.
> 
> (I do believe we have a dilemma here. In QEMU, we probably prefer to
> emulate physical hardware as faithfully as possible. However, we do not
> have Cache-As-RAM (nor do we intend to, IIUC). Does that justify other
> divergences from physical hardware too, such as waking just by virtue of
> an SMI?)
So far we should be able to implement it per spec (at least SDM one),
but we would still need to invent chipset hardware
i.e. like adding to Q35 non exiting SMRAM and means to map/unmap it
to non-SMM address space.
(and I hope we could avoid adding "parked CPU" thingy)
 
> > Can the SMI monarch use the Local
> > APIC to send a directed SMI to the hot added CPU?
> > The SMI monarch needs to know the APIC ID of the
> > hot added CPU.  Do we also need to handle the case
> > where multiple CPUs are added at once?  I think we
> > would need to serialize the use of 3000:8000 for the
> > SMM rebase operation on each hot added CPU.
> 
> I agree this would be a huge help.

We can serialize it (for normal hotplug flow) from ACPI handler
in the guest (i.e. non enforced serialization).
The only reason for serialization I see is not to allow
a bunch of new CPU trample over default SMBASE save area
at the same time.

There is a consideration though, an OS level attacker
could send broadcast SMI and INIT-SIPI-SIPI sequences
to rigger race, but I don't see it as a threat since
attack shouldn't be able to exploit anything and in
worst case guest OS would crash (taking in account that
SMIs are privileged, OS attacker has a plenty of other
means to kill itself).

> > It would be simpler if we can guarantee that only
> > one CPU can be added or removed at a time and the 
> > complete flow of adding a CPU to SMM and the OS
> > needs to be completed before another add/remove
> > event needs to be processed.
> 
> I don't know if the QEMU monitor command in question can guarantee this
> serialization. I think such a request/response pattern is generally
> implementable between QEMU and guest code.
> 
> But, AIUI, the "device-add" monitor command is quite generic, and used
> for hot-plugging a number of other (non-CPU) device models. I'm unsure
> if the pattern in question can be squeezed into "device-add". (It's not
> a dedicated command for CPU hotplug.)
> 
> ... Apologies that I didn't add much information to the thread, just
> now. I'd like to keep the discussion going.
> 
> Thanks
> Laszlo


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Re: [edk2-devel] [PATCH] [edk2-stable201908] MdePkg/BluetoothLeConfig.h: Add type EfiBluetoothSmpPeerAddressList

[Ni, Ray]

I relegalized the code freeze might be end very soon. I am ok with that.


> -Original Message-
> From: devel@edk2.groups.io  On Behalf Of Laszlo Ersek
> Sent: Tuesday, August 27, 2019 5:48 AM
> To: Ni, Ray ; Kinney, Michael D 
> ; Gao, Liming ;
> devel@edk2.groups.io
> Cc: af...@apple.com; leif.lindh...@linaro.org
> Subject: Re: [edk2-devel] [PATCH] [edk2-stable201908] 
> MdePkg/BluetoothLeConfig.h: Add type
> EfiBluetoothSmpPeerAddressList
> 
> On 08/27/19 02:45, Ni, Ray wrote:
> > The consumers are in close source and won't be in open source in near 
> > future.
> > But consumers depend on open source repo.
> 
> In my interpretation, this patch does not qualify as a bugfix (suitable
> for merging during the hard feature freeze), and should be postponed to
> the next development cycle.
> 
> Thanks
> Laszlo
> 
> >
> >> -Original Message-
> >> From: Kinney, Michael D
> >> Sent: Monday, August 26, 2019 5:20 PM
> >> To: Gao, Liming ; Ni, Ray ; 
> >> devel@edk2.groups.io; Kinney, Michael D
> >> 
> >> Cc: af...@apple.com; leif.lindh...@linaro.org; Laszlo Ersek 
> >> (ler...@redhat.com) 
> >> Subject: RE: [edk2-devel] [PATCH] [edk2-stable201908] 
> >> MdePkg/BluetoothLeConfig.h: Add type
> >> EfiBluetoothSmpPeerAddressList
> >>
> >> Ray,
> >>
> >> Are there any components that need these new enum values?
> >>
> >> The patch looks very straightforward and is from the
> >> UEFI Spec, so I think the risk is low.  But if consumers
> >> will not show up until after the stable tag, perhaps this
> >> should be one of the first patches after the stable tag.
> >>
> >> Thanks,
> >>
> >> Mike
> >>
> >>> -Original Message-
> >>> From: Gao, Liming
> >>> Sent: Monday, August 26, 2019 4:57 PM
> >>> To: Ni, Ray ; devel@edk2.groups.io
> >>> Cc: Kinney, Michael D ;
> >>> af...@apple.com; leif.lindh...@linaro.org; Laszlo Ersek
> >>> (ler...@redhat.com) 
> >>> Subject: RE: [edk2-devel] [PATCH] [edk2-stable201908]
> >>> MdePkg/BluetoothLeConfig.h: Add type
> >>> EfiBluetoothSmpPeerAddressList
> >>>
> >>> Cc to all Stewards.
> >>>
>  -Original Message-
>  From: Ni, Ray
>  Sent: Tuesday, August 27, 2019 2:20 AM
>  To: devel@edk2.groups.io; Ni, Ray 
>  Cc: Kinney, Michael D ;
> >>> Gao, Liming
>  
>  Subject: RE: [edk2-devel] [PATCH] [edk2-stable201908]
>  MdePkg/BluetoothLeConfig.h: Add type
> >>> EfiBluetoothSmpPeerAddressList
> 
>  I understand it's now in code freeze phase.
>  Just make a try to see whether this very clean/simple
> >>> header file
>  change can be included in the stable tag.
>  Any platform that uses BLE stack can get benefit from
> >>> this definition update.
> 
> > -Original Message-
> > From: devel@edk2.groups.io  On
> >>> Behalf Of Ni,
> > Ray
> > Sent: Monday, August 26, 2019 11:16 AM
> > To: devel@edk2.groups.io
> > Cc: Kinney, Michael D ;
> >>> Gao, Liming
>  
> > Subject: [edk2-devel] [PATCH] [edk2-stable201908]
>  MdePkg/BluetoothLeConfig.h: Add type
> >>> EfiBluetoothSmpPeerAddressList
> >
> > To support auto-connection,
> >>> EFI_BLUETOOTH_LE_SMP_DATA_TYPE needs
>  to
> > add a new data type EfiBluetoothSmpPeerAddressList
> >>> which associates
> > with a list of Bluetooth per address connected
> >>> before.
> >
> > This new data type was added in UEFI spec 2.7b.
> >
> > Signed-off-by: Ray Ni 
> > Cc: Michael D Kinney 
> > Cc: Liming Gao 
> > ---
> >  MdePkg/Include/Protocol/BluetoothLeConfig.h | 4 +++-
> >  1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git
> >>> a/MdePkg/Include/Protocol/BluetoothLeConfig.h
>  b/MdePkg/Include/Protocol/BluetoothLeConfig.h
> > index 8c0f881f85..8726a58b15 100644
> > --- a/MdePkg/Include/Protocol/BluetoothLeConfig.h
> > +++ b/MdePkg/Include/Protocol/BluetoothLeConfig.h
> > @@ -2,7 +2,7 @@
> >EFI Bluetooth LE Config Protocol as defined in
> >>> UEFI 2.7.
> >This protocol abstracts user interface
> >>> configuration for BluetoothLe device.
> >
> > -  Copyright (c) 2017, Intel Corporation. All rights
> >>> reserved.
> > +  Copyright (c) 2017 - 2019, Intel Corporation. All
> >>> rights
> > + reserved.
> >SPDX-License-Identifier: BSD-2-Clause-Patent
> >
> >@par Revision Reference:
> > @@ -451,6 +451,8 @@ typedef enum {
> >EfiBluetoothSmpLocalCSRK, /* If Key hierarchy not
> >>> supported */
> >EfiBluetoothSmpLocalSignCounter,
> >EfiBluetoothSmpLocalDIV,
> > +  EfiBluetoothSmpPeerAddressList,
> > +  EfiBluetoothSmpMax,
> >  } EFI_BLUETOOTH_LE_SMP_DATA_TYPE;
> >
> >  /**
> > --
> > 2.21.0.windows.1
> >
> >
> >
> >
> 
> 
> 


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edk2-stable201908 Re: [edk2-devel] [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)

[Leif Lindholm]

Apologies, forgot to tag the subject for stable release (although I
did remember to cc the stewards).

We don't appear to have a fix version for edk2-stable201908 in
bugzilla, though.

On Tue, Aug 27, 2019 at 01:43:28PM +0100, Leif Lindholm via Groups.Io wrote:
> Commit 4a1f6b85c184
> ("MdeModulePkg: add LockBoxNullLib for !IA32/X64 in .dsc")
> added an ARM/AARCH64 resolution for LockBoxLib. However, this failed
> to address the overrides provided for PEIM, DXE_DRIVER,
> DXE_RUNTIME_DRIVER, DXE_SMM_DRIVER and UEFI_DRIVER, so any modules
> of those classes still failed to build.
> 
> Break these out properly into their own LibraryClasses sections.
> 
> Resolves BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2134
> 
> Signed-off-by: Leif Lindholm 
> Reported-by: Baptiste Gerondeau 
> Cc: Jian J Wang 
> Cc: Hao A Wu 
> ---
> 
> I don't understand how the above would appear to work back when I
> submitted the previous patch but not work now, but I haven't dug
> into it deeper. Including the x86-specific LockBoxLib in the
> .common section is however clearly not correct.
> 
> I think a fix for this issue needs to go into 2019.08, but if
> someone has a prettier suggestion, I am not wedded to this one.
> 
>  MdeModulePkg/MdeModulePkg.dsc | 16 +---
>  1 file changed, 13 insertions(+), 3 deletions(-)
> 
> diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc
> index 4320839abfb5..15ba96cecbed 100644
> --- a/MdeModulePkg/MdeModulePkg.dsc
> +++ b/MdeModulePkg/MdeModulePkg.dsc
> @@ -109,6 +109,8 @@ [LibraryClasses.common.PEIM]
>HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
>
> MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
>
> ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
> +
> +[LibraryClasses.IA32.PEIM,LibraryClasses.X64.PEIM]
>LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf
>  
>  [LibraryClasses.common.DXE_CORE]
> @@ -118,18 +120,22 @@ [LibraryClasses.common.DXE_CORE]
>  
>  [LibraryClasses.common.DXE_DRIVER]
>HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
> -  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
>
> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
>
> ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
>CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf
>  
> +[LibraryClasses.IA32.DXE_DRIVER,LibraryClasses.X64.DXE_DRIVER]
> +  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
> +
>  [LibraryClasses.common.DXE_RUNTIME_DRIVER]
>HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
>
> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
>DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
> -  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
>CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf
>  
> +[LibraryClasses.IA32.DXE_RUNTIME_DRIVER,LibraryClasses.X64.DXE_RUNTIME_DRIVER]
> +  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
> +
>  [LibraryClasses.common.SMM_CORE]
>HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
>
> MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationLib.inf
> @@ -143,13 +149,17 @@ [LibraryClasses.common.DXE_SMM_DRIVER]
>
> MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf
>MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf
>
> SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf
> +  SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
> +
> +[LibraryClasses.IA32.DXE_SMM_DRIVER,LibraryClasses.X64.DXE_SMM_DRIVER]
>LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf
> -  SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
>  
>  [LibraryClasses.common.UEFI_DRIVER]
>HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
>
> MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
>DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
> +
> +[LibraryClasses.IA32.UEFI_DRIVER,LibraryClasses.X64.UEFI_DRIVER]
>LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
>  
>  [LibraryClasses.common.UEFI_APPLICATION]
> -- 
> 2.20.1
> 
> 
> 
> 

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[edk2-devel] [PATCH v2 1/1] [platforms/devel-riscv]: U500Pkg: Update Readme.md

[Abner Chang]

Update Readme.md follow sample platform readme guidance.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Abner Chang 
---
 Platform/RiscV/SiFive/U500Pkg/Readme.md | 32 
 1 file changed, 32 insertions(+)

diff --git a/Platform/RiscV/SiFive/U500Pkg/Readme.md 
b/Platform/RiscV/SiFive/U500Pkg/Readme.md
index 3aaaf77..a073e04 100644
--- a/Platform/RiscV/SiFive/U500Pkg/Readme.md
+++ b/Platform/RiscV/SiFive/U500Pkg/Readme.md
@@ -7,6 +7,38 @@ This is a sample RISC-V EDK2 platform package used agaist 
SiFive Freedom U500 VC
 
 This package provides librareis and modules which are SiFive U500 platform 
implementation-specific and incorporate with common RISC-V packages mentioned 
above.
 
+## Download the sources
+```
+git clone https://github.com/tianocore/edk2-staging.git
+# Checkout "RISC-V" branch
+git clone https://github.com/tianocore/edk2-platforms.git
+# Checkout "devel-riscv" branch
+git clone https://github.com/tianocore/edk2-non-osi.git
+```
+
+## Platform Owners
+Chang, Abner 
+Chen, Gilbert 
+
+## Platform Status
+Currently the binary built from U500Pkg can boot SiFive Freedom U500 VC707 
FPGA to EFI shell with console in/out enabled.
+
+## Linux Build Instructions
+You can build the RISC-V platform using below script, 
+`build -a RISCV64 -p Platform/RiscV/SiFive/U500Pkg/U500.dsc -t GCC711RISCV`
+
+## Supported Operating Systems
+Only support to boot to EFI Shell so far
+
+## Known Issues and Limitations
+Only RISC-V RV64 is verified on this platform.
+
+## Related Materials
+- [RISC-V OpenSbi](https://github.com/riscv/opensbi)
+- [SiFive U500 VC707 FPGA Getting Started 
Guide](https://sifive.cdn.prismic.io/sifive%2Fc248fabc-5e44-4412-b1c3-6bb6aac73a2c_sifive-u500-vc707-gettingstarted-v0.2.pdf)
+- [SiFive RISC-V Core Document](https://www.sifive.com/documentation)
+
+## U500 Platform Libraries and Drivers
 ### OpneSbiPlatformLib
 In order to reduce the dependencies with RISC-V OpenSBI project 
(https://github.com/riscv/opensbi) and less burdens to EDK2 build process, the 
implementation of RISC-V EDK2 platform is leverage platform source code from 
OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib  is cloned from 
RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build 
environment.
 
-- 
2.7.4


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[edk2-devel] Upcoming Event: TianoCore Design / Bug Triage - EMEA - Wed, 08/28/2019 8:00am-9:00am #cal-reminder

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Re: [edk2-devel] git submodule update --init --recursive

[Laszlo Ersek]

(+Jordan and Gary)

On 08/27/19 00:29, Andrew Fish via Groups.Io wrote:
> Mike,
> 
> I hit it when I was testing an OVMF build. It looks like the OVMF 
> instructions reference the generic getting started guide that omits the 
> submodule update command. 

I agree that the "BUILDING OVMF" section in "OvmfPkg/README" is out of
date. I think a bugzilla ticket would be justified.

Personally, I wouldn't like to propose actual patches, for improving
this part of "OvmfPkg/README". For me, the best way for building OVMF
has always been to write my own build scripts. In our downstream edk2
repositories at Red Hat, I provide a text file with detailed commands
that basically amount to the same.

I think that, technically speaking, the same could work for the
"OvmfPkg/README" file too. But my understanding is that many in the
upstream community dislike this approach -- many people prefer
"OvmfPkg/build.sh" instead (which I never use -- it *is* a build script
alright, but it's quite different from what I use).

"OvmfPkg/README" does mention "OvmfPkg/build.sh" in the "Build Scripts"
section. So maybe "OvmfPkg/build.sh" should be patched, to verify that
the OpenSSL submodule has been initialized. That could be another BZ (or
another patch in the series for the same BZ).

Thanks
Laszlo

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Re: [edk2-devel] [PATCH] [edk2-stable201908] MdePkg/BluetoothLeConfig.h: Add type EfiBluetoothSmpPeerAddressList

[Laszlo Ersek]

On 08/27/19 02:45, Ni, Ray wrote:
> The consumers are in close source and won't be in open source in near future.
> But consumers depend on open source repo.

In my interpretation, this patch does not qualify as a bugfix (suitable
for merging during the hard feature freeze), and should be postponed to
the next development cycle.

Thanks
Laszlo

> 
>> -Original Message-
>> From: Kinney, Michael D
>> Sent: Monday, August 26, 2019 5:20 PM
>> To: Gao, Liming ; Ni, Ray ; 
>> devel@edk2.groups.io; Kinney, Michael D
>> 
>> Cc: af...@apple.com; leif.lindh...@linaro.org; Laszlo Ersek 
>> (ler...@redhat.com) 
>> Subject: RE: [edk2-devel] [PATCH] [edk2-stable201908] 
>> MdePkg/BluetoothLeConfig.h: Add type
>> EfiBluetoothSmpPeerAddressList
>>
>> Ray,
>>
>> Are there any components that need these new enum values?
>>
>> The patch looks very straightforward and is from the
>> UEFI Spec, so I think the risk is low.  But if consumers
>> will not show up until after the stable tag, perhaps this
>> should be one of the first patches after the stable tag.
>>
>> Thanks,
>>
>> Mike
>>
>>> -Original Message-
>>> From: Gao, Liming
>>> Sent: Monday, August 26, 2019 4:57 PM
>>> To: Ni, Ray ; devel@edk2.groups.io
>>> Cc: Kinney, Michael D ;
>>> af...@apple.com; leif.lindh...@linaro.org; Laszlo Ersek
>>> (ler...@redhat.com) 
>>> Subject: RE: [edk2-devel] [PATCH] [edk2-stable201908]
>>> MdePkg/BluetoothLeConfig.h: Add type
>>> EfiBluetoothSmpPeerAddressList
>>>
>>> Cc to all Stewards.
>>>
 -Original Message-
 From: Ni, Ray
 Sent: Tuesday, August 27, 2019 2:20 AM
 To: devel@edk2.groups.io; Ni, Ray 
 Cc: Kinney, Michael D ;
>>> Gao, Liming
 
 Subject: RE: [edk2-devel] [PATCH] [edk2-stable201908]
 MdePkg/BluetoothLeConfig.h: Add type
>>> EfiBluetoothSmpPeerAddressList

 I understand it's now in code freeze phase.
 Just make a try to see whether this very clean/simple
>>> header file
 change can be included in the stable tag.
 Any platform that uses BLE stack can get benefit from
>>> this definition update.

> -Original Message-
> From: devel@edk2.groups.io  On
>>> Behalf Of Ni,
> Ray
> Sent: Monday, August 26, 2019 11:16 AM
> To: devel@edk2.groups.io
> Cc: Kinney, Michael D ;
>>> Gao, Liming
 
> Subject: [edk2-devel] [PATCH] [edk2-stable201908]
 MdePkg/BluetoothLeConfig.h: Add type
>>> EfiBluetoothSmpPeerAddressList
>
> To support auto-connection,
>>> EFI_BLUETOOTH_LE_SMP_DATA_TYPE needs
 to
> add a new data type EfiBluetoothSmpPeerAddressList
>>> which associates
> with a list of Bluetooth per address connected
>>> before.
>
> This new data type was added in UEFI spec 2.7b.
>
> Signed-off-by: Ray Ni 
> Cc: Michael D Kinney 
> Cc: Liming Gao 
> ---
>  MdePkg/Include/Protocol/BluetoothLeConfig.h | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git
>>> a/MdePkg/Include/Protocol/BluetoothLeConfig.h
 b/MdePkg/Include/Protocol/BluetoothLeConfig.h
> index 8c0f881f85..8726a58b15 100644
> --- a/MdePkg/Include/Protocol/BluetoothLeConfig.h
> +++ b/MdePkg/Include/Protocol/BluetoothLeConfig.h
> @@ -2,7 +2,7 @@
>EFI Bluetooth LE Config Protocol as defined in
>>> UEFI 2.7.
>This protocol abstracts user interface
>>> configuration for BluetoothLe device.
>
> -  Copyright (c) 2017, Intel Corporation. All rights
>>> reserved.
> +  Copyright (c) 2017 - 2019, Intel Corporation. All
>>> rights
> + reserved.
>SPDX-License-Identifier: BSD-2-Clause-Patent
>
>@par Revision Reference:
> @@ -451,6 +451,8 @@ typedef enum {
>EfiBluetoothSmpLocalCSRK, /* If Key hierarchy not
>>> supported */
>EfiBluetoothSmpLocalSignCounter,
>EfiBluetoothSmpLocalDIV,
> +  EfiBluetoothSmpPeerAddressList,
> +  EfiBluetoothSmpMax,
>  } EFI_BLUETOOTH_LE_SMP_DATA_TYPE;
>
>  /**
> --
> 2.21.0.windows.1
>
>
> 
> 


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[edk2-devel] [PATCH 1/1] MdeModulePkg: fix !x86 builds (more)

[Leif Lindholm]

Commit 4a1f6b85c184
("MdeModulePkg: add LockBoxNullLib for !IA32/X64 in .dsc")
added an ARM/AARCH64 resolution for LockBoxLib. However, this failed
to address the overrides provided for PEIM, DXE_DRIVER,
DXE_RUNTIME_DRIVER, DXE_SMM_DRIVER and UEFI_DRIVER, so any modules
of those classes still failed to build.

Break these out properly into their own LibraryClasses sections.

Resolves BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2134

Signed-off-by: Leif Lindholm 
Reported-by: Baptiste Gerondeau 
Cc: Jian J Wang 
Cc: Hao A Wu 
---

I don't understand how the above would appear to work back when I
submitted the previous patch but not work now, but I haven't dug
into it deeper. Including the x86-specific LockBoxLib in the
.common section is however clearly not correct.

I think a fix for this issue needs to go into 2019.08, but if
someone has a prettier suggestion, I am not wedded to this one.

 MdeModulePkg/MdeModulePkg.dsc | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc
index 4320839abfb5..15ba96cecbed 100644
--- a/MdeModulePkg/MdeModulePkg.dsc
+++ b/MdeModulePkg/MdeModulePkg.dsc
@@ -109,6 +109,8 @@ [LibraryClasses.common.PEIM]
   HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
   
MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
   
ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+
+[LibraryClasses.IA32.PEIM,LibraryClasses.X64.PEIM]
   LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf
 
 [LibraryClasses.common.DXE_CORE]
@@ -118,18 +120,22 @@ [LibraryClasses.common.DXE_CORE]
 
 [LibraryClasses.common.DXE_DRIVER]
   HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
-  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
   
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
   
ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeCapsuleLib.inf
 
+[LibraryClasses.IA32.DXE_DRIVER,LibraryClasses.X64.DXE_DRIVER]
+  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
+
 [LibraryClasses.common.DXE_RUNTIME_DRIVER]
   HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
   
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
   DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
-  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibFmp/DxeRuntimeCapsuleLib.inf
 
+[LibraryClasses.IA32.DXE_RUNTIME_DRIVER,LibraryClasses.X64.DXE_RUNTIME_DRIVER]
+  LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
+
 [LibraryClasses.common.SMM_CORE]
   HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
   
MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationLib.inf
@@ -143,13 +149,17 @@ [LibraryClasses.common.DXE_SMM_DRIVER]
   
MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf
   MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf
   
SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf
+  SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
+
+[LibraryClasses.IA32.DXE_SMM_DRIVER,LibraryClasses.X64.DXE_SMM_DRIVER]
   LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf
-  SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
 
 [LibraryClasses.common.UEFI_DRIVER]
   HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
   
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
   DebugLib|MdePkg/Library/UefiDebugLibConOut/UefiDebugLibConOut.inf
+
+[LibraryClasses.IA32.UEFI_DRIVER,LibraryClasses.X64.UEFI_DRIVER]
   LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
 
 [LibraryClasses.common.UEFI_APPLICATION]
-- 
2.20.1


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Re: [edk2-devel] [PATCH] [edk2-stable201908] MdePkg/BluetoothLeConfig.h: Add type EfiBluetoothSmpPeerAddressList

[Leif Lindholm]

Understood.

But that also means they depend on a well tested open source repo.
So I agree with Mike - the value of getting it into the stable tag
would be defeated by getting it in too late for useful testing.
I would prefer for it to go into after the stable tag.

However, that is my procedural opinion. The diff is trivial. So I am
not not saying "no", only that my preference would be to merge it
after the tag.

Best Regards,

Leif

On Tue, Aug 27, 2019 at 12:45:54AM +, Ni, Ray wrote:
> The consumers are in close source and won't be in open source in near future.
> But consumers depend on open source repo.
> 
> > -Original Message-
> > From: Kinney, Michael D
> > Sent: Monday, August 26, 2019 5:20 PM
> > To: Gao, Liming ; Ni, Ray ; 
> > devel@edk2.groups.io; Kinney, Michael D
> > 
> > Cc: af...@apple.com; leif.lindh...@linaro.org; Laszlo Ersek 
> > (ler...@redhat.com) 
> > Subject: RE: [edk2-devel] [PATCH] [edk2-stable201908] 
> > MdePkg/BluetoothLeConfig.h: Add type
> > EfiBluetoothSmpPeerAddressList
> > 
> > Ray,
> > 
> > Are there any components that need these new enum values?
> > 
> > The patch looks very straightforward and is from the
> > UEFI Spec, so I think the risk is low.  But if consumers
> > will not show up until after the stable tag, perhaps this
> > should be one of the first patches after the stable tag.
> > 
> > Thanks,
> > 
> > Mike
> > 
> > > -Original Message-
> > > From: Gao, Liming
> > > Sent: Monday, August 26, 2019 4:57 PM
> > > To: Ni, Ray ; devel@edk2.groups.io
> > > Cc: Kinney, Michael D ;
> > > af...@apple.com; leif.lindh...@linaro.org; Laszlo Ersek
> > > (ler...@redhat.com) 
> > > Subject: RE: [edk2-devel] [PATCH] [edk2-stable201908]
> > > MdePkg/BluetoothLeConfig.h: Add type
> > > EfiBluetoothSmpPeerAddressList
> > >
> > > Cc to all Stewards.
> > >
> > > >-Original Message-
> > > >From: Ni, Ray
> > > >Sent: Tuesday, August 27, 2019 2:20 AM
> > > >To: devel@edk2.groups.io; Ni, Ray 
> > > >Cc: Kinney, Michael D ;
> > > Gao, Liming
> > > >
> > > >Subject: RE: [edk2-devel] [PATCH] [edk2-stable201908]
> > > >MdePkg/BluetoothLeConfig.h: Add type
> > > EfiBluetoothSmpPeerAddressList
> > > >
> > > >I understand it's now in code freeze phase.
> > > >Just make a try to see whether this very clean/simple
> > > header file
> > > >change can be included in the stable tag.
> > > >Any platform that uses BLE stack can get benefit from
> > > this definition update.
> > > >
> > > >> -Original Message-
> > > >> From: devel@edk2.groups.io  On
> > > Behalf Of Ni,
> > > >> Ray
> > > >> Sent: Monday, August 26, 2019 11:16 AM
> > > >> To: devel@edk2.groups.io
> > > >> Cc: Kinney, Michael D ;
> > > Gao, Liming
> > > >
> > > >> Subject: [edk2-devel] [PATCH] [edk2-stable201908]
> > > >MdePkg/BluetoothLeConfig.h: Add type
> > > EfiBluetoothSmpPeerAddressList
> > > >>
> > > >> To support auto-connection,
> > > EFI_BLUETOOTH_LE_SMP_DATA_TYPE needs
> > > >to
> > > >> add a new data type EfiBluetoothSmpPeerAddressList
> > > which associates
> > > >> with a list of Bluetooth per address connected
> > > before.
> > > >>
> > > >> This new data type was added in UEFI spec 2.7b.
> > > >>
> > > >> Signed-off-by: Ray Ni 
> > > >> Cc: Michael D Kinney 
> > > >> Cc: Liming Gao 
> > > >> ---
> > > >>  MdePkg/Include/Protocol/BluetoothLeConfig.h | 4 +++-
> > > >>  1 file changed, 3 insertions(+), 1 deletion(-)
> > > >>
> > > >> diff --git
> > > a/MdePkg/Include/Protocol/BluetoothLeConfig.h
> > > >b/MdePkg/Include/Protocol/BluetoothLeConfig.h
> > > >> index 8c0f881f85..8726a58b15 100644
> > > >> --- a/MdePkg/Include/Protocol/BluetoothLeConfig.h
> > > >> +++ b/MdePkg/Include/Protocol/BluetoothLeConfig.h
> > > >> @@ -2,7 +2,7 @@
> > > >>EFI Bluetooth LE Config Protocol as defined in
> > > UEFI 2.7.
> > > >>This protocol abstracts user interface
> > > configuration for BluetoothLe device.
> > > >>
> > > >> -  Copyright (c) 2017, Intel Corporation. All rights
> > > reserved.
> > > >> +  Copyright (c) 2017 - 2019, Intel Corporation. All
> > > rights
> > > >> + reserved.
> > > >>SPDX-License-Identifier: BSD-2-Clause-Patent
> > > >>
> > > >>@par Revision Reference:
> > > >> @@ -451,6 +451,8 @@ typedef enum {
> > > >>EfiBluetoothSmpLocalCSRK, /* If Key hierarchy not
> > > supported */
> > > >>EfiBluetoothSmpLocalSignCounter,
> > > >>EfiBluetoothSmpLocalDIV,
> > > >> +  EfiBluetoothSmpPeerAddressList,
> > > >> +  EfiBluetoothSmpMax,
> > > >>  } EFI_BLUETOOTH_LE_SMP_DATA_TYPE;
> > > >>
> > > >>  /**
> > > >> --
> > > >> 2.21.0.windows.1
> > > >>
> > > >>
> > > >> 
> 

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[edk2-devel] [PATCH 07/15] [platforms/devel-riscv]: RiscV/SiFive: Initial version of SiFive U500 platform package

[Mr. Gilbert Chen]

The initial version of SiFive U500 platform package.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Platform/RiscV/SiFive/U500Pkg/Readme.md|  30 ++
 Platform/RiscV/SiFive/U500Pkg/U500.dec |  40 ++
 Platform/RiscV/SiFive/U500Pkg/U500.dsc | 596 +
 Platform/RiscV/SiFive/U500Pkg/U500.fdf | 373 
 Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc |  58 +++
 Platform/RiscV/SiFive/U500Pkg/U500.uni | Bin 0 -> 1730 bytes
 Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni | Bin 0 -> 1396 bytes
 Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc |  85 
 8 files changed, 1182 insertions(+)
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Readme.md
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dec
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dsc
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.uni
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc

diff --git a/Platform/RiscV/SiFive/U500Pkg/Readme.md 
b/Platform/RiscV/SiFive/U500Pkg/Readme.md
new file mode 100644
index 000..3aaaf77
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Readme.md
@@ -0,0 +1,30 @@
+# Introduction
+
+## U500 Platform Package
+This is a sample RISC-V EDK2 platform package used agaist SiFive Freedom U500 
VC707 FPGA Dev Kit, please refer to "SiFive Freedom U500 VC707 FPGA Getting 
Started Guide" on https://www.sifive.com/documentation. This package is built 
with below common packages, 
+- **RiscVPlatformPkg**, edk2-platform/Platform/RiscV
+- **RiscVPkg**, edk2 master branch (Currently is in edk2-staging/RISC-V branch)
+
+This package provides librareis and modules which are SiFive U500 platform 
implementation-specific and incorporate with common RISC-V packages mentioned 
above.
+
+### OpneSbiPlatformLib
+In order to reduce the dependencies with RISC-V OpenSBI project 
(https://github.com/riscv/opensbi) and less burdens to EDK2 build process, the 
implementation of RISC-V EDK2 platform is leverage platform source code from 
OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib  is cloned from 
RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build 
environment.
+
+### PeiCoreInfoHobLib
+This is the library to create RISC-V core characteristics for building up 
RISC-V related SMBIOS records to support the unified boot loader and OS image. 
This library leverage the silicon libraries provided in Silicon/SiFive.
+
+### RiscVPlatformTimerLib
+This is U500 platform timer library which has the platform-specific timer 
implementation.
+
+### PlatformPei
+This is the platform-implementation specific library which is executed in 
early PEI phase for platform initialization.
+
+### TimerDxe
+This is U500 platform timer DXE driver whcih has the platform-specific timer 
implementation.
+
+## U500 Platform PCD settings
+
+| **PCD name** |**Usage**|
+||--|
+|PcdNumberofU5Cores| Number of U5 core enabled on U500 platform|
+|PcdE5MCSupported| Indicates whether or not the Monitor Core (E5) is supported 
on U500 platform|
diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.dec 
b/Platform/RiscV/SiFive/U500Pkg/U500.dec
new file mode 100644
index 000..9886328
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/U500.dec
@@ -0,0 +1,40 @@
+## @file  U500.dec
+# This Package provides SiFive U500 modules and libraries.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+#
+# This program and the accompanying materials are licensed and made available 
under
+# the terms and conditions of the BSD License which accompanies this 
distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  DEC_SPECIFICATION  = 0x00010005
+  PACKAGE_NAME   = U500
+  PACKAGE_UNI_FILE   = U500.uni
+  PACKAGE_GUID   = D11E9DB9-5940-4642-979D-2114342140D2
+  PACKAGE_VERSION= 1.0
+
+[Includes]
+  Include
+
+[LibraryClasses]
+
+
+[Guids]
+  gUefiRiscVPlatformU500PkgTokenSpaceGuid  = {0xDFD87009, 0x27A1, 0x41DD, { 
0x84, 0xB1, 0x35, 0xB4, 0xB9, 0x0D, 0x17, 0x63 }}
+
+[PcdsFixedAtBuild]
+  
gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores|0x8|UINT32|0x1000
+  
gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported|TRUE|BOOLEAN|0x1001
+
+[PcdsPatchableInModule]
+
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  U500PkgExtra.uni
diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.dsc 
b/Platform/RiscV/SiFive/U500Pkg/U500.dsc
new file mode 100644
index 

[edk2-devel] [PATCH 05/15] [platforms/devel-riscv]: RiscV/Library: Initial version of libraries introduced in RISC-V platform package

[Mr. Gilbert Chen]

From: Gilbert Chen 

FirmwareContextProcessorSpecificLib
- Common library to consume EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC and build 
up processor specific data HOB.

RealTimClockLibNull
- NULL instance of Real Time Clock library.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../FirmwareContextProcessorSpecificLib.c  |  88 +
 .../FirmwareContextProcessorSpecificLib.inf|  39 
 .../RealTimeClockLibNull/RealTimeClockLibNull.c| 212 +
 .../RealTimeClockLibNull/RealTimeClockLibNull.inf  |  36 
 4 files changed, 375 insertions(+)
 create mode 100644 
Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
 create mode 100644 
Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
 create mode 100644 
Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
 create mode 100644 
Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf

diff --git 
a/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
 
b/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
new file mode 100644
index 000..0ce2570
--- /dev/null
+++ 
b/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
@@ -0,0 +1,88 @@
+/**@file
+  Common library to build upfirmware context processor-specific information
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Build up common firmware context processor-specific information
+
+  @param  FirmwareContextHartSpecific  Pointer to 
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
+  @param  ParentProcessorGuid  Pointer to GUID of Processor which 
contains this core 
+  @param  ParentProcessorUid   Unique ID of pysical processor which 
owns this core.   
+  @param  CoreGuid Pointer to GUID of core
+  @param  HartId   Hart ID of this core.
+  @param  IsBootHart   This is boot hart or not 
+  @param  ProcessorSpecDataHob Pointer to 
RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+
+  @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CommonFirmwareContextHartSpecificInfo (
+  EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
+  EFI_GUID  *ParentProcessorGuid,
+  UINTN ParentProcessorUid,
+  EFI_GUID  *CoreGuid,
+  UINTN HartId,
+  BOOLEAN   IsBootHart,
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecDataHob
+  )
+{
+  //
+  // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+  //
+  CopyGuid (>ParentPrcessorGuid, ParentProcessorGuid);
+  ProcessorSpecDataHob->ParentProcessorUid = ParentProcessorUid;
+  CopyGuid (>CoreGuid, CoreGuid);
+  ProcessorSpecDataHob->Context = NULL;
+  ProcessorSpecDataHob->ProcessorSpecificData.Revision = 
SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION;
+  ProcessorSpecDataHob->ProcessorSpecificData.Length   = sizeof 
(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+  ProcessorSpecDataHob->ProcessorSpecificData.HartId.Value64_L = 
(UINT64)HartId;
+  ProcessorSpecDataHob->ProcessorSpecificData.HartId.Value64_H = 0;
+  ProcessorSpecDataHob->ProcessorSpecificData.BootHartId   = 
(UINT8)IsBootHart;
+  ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported = 
FirmwareContextHartSpecific->IsaExtensionSupported;
+  ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported   = 
SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED;
+  if ((ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported & 
RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED) != 0) {
+ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported |= 
SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED;
+  }
+  if ((ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported & 
RISC_V_ISA_USER_MODE_IMPLEMENTED) != 0) {
+ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported |= 
SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED;
+  }
+  ProcessorSpecDataHob->ProcessorSpecificData.MachineVendorId.Value64_L = 
FirmwareContextHartSpecific->MachineVendorId.Value64_L;
+  ProcessorSpecDataHob->ProcessorSpecificData.MachineVendorId.Value64_H = 

[edk2-devel] [PATCH 11/15] [platforms/devel-riscv]: U500Pkg/Library: Library instances of U500 platform library.

[Mr. Gilbert Chen]

PeiCoreInfoHobLib
- This is the library to create RISC-V core characteristics for building up 
RISC-V related SMBIOS records to support the unified boot loader and OS image.

- RiscVPlatformTimerLib
This is U500 platform timer library which has the platform-specific timer 
implementation.

- SerialPortLib
U500 serial port platform library

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../Library/PeiCoreInfoHobLib/CoreInfoHob.c| 201 +
 .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf|  64 ++
 .../RiscVPlatformTimerLib.inf  |  46 
 .../RiscVPlatformTimerLib/RiscVPlatformTimerLib.s  |  54 +
 .../U500Pkg/Library/SerialIoLib/SerialIoLib.inf|  37 +++
 .../U500Pkg/Library/SerialIoLib/SerialPortLib.c| 247 +
 .../Library/SerialIoLib/U500SerialPortLib.uni  |  22 ++
 7 files changed, 671 insertions(+)
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.s
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib.uni

diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c 
b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 000..2db4fdc
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,201 @@
+/**@file
+  Build up platform processor information.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Build up processor-specific HOB for U5MC Coreplex
+
+  @param  UniqueId  Unique ID of this U5MC Coreplex processor
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCCoreplexProcessorSpecificDataHob (
+  IN UINTN UniqueId
+  )
+{
+  EFI_STATUS Status;
+  UINT32 HartIdNumber;
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *GuidHobData;
+  EFI_GUID *ParentCoreGuid;
+  BOOLEAN MCSupport;
+
+  DEBUG ((EFI_D_INFO, "Building U5 Coreplex processor information HOB\n"));
+
+  HartIdNumber = 0;
+  ParentCoreGuid = PcdGetPtr(PcdSiFiveU5MCCoreplexGuid);
+  MCSupport = PcdGetBool (PcdE5MCSupported);
+  if (MCSupport == TRUE) {
+Status = CreateE51CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, 
HartIdNumber, FALSE, );
+if (EFI_ERROR (Status)) {
+  DEBUG ((EFI_D_ERROR, "Faile to build U5MC processor informatino HOB\n"));
+  ASSERT (FALSE);
+}
+HartIdNumber ++;
+DEBUG ((EFI_D_INFO, "Support E5 Monitor core on U500 platform, HOB at 
address 0x%x\n", GuidHobData));
+  }
+  for (; HartIdNumber < (FixedPcdGet32 (PcdNumberofU5Cores) + 
(UINT32)MCSupport); HartIdNumber ++) {
+Status = CreateU54CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, 
HartIdNumber, (HartIdNumber == FixedPcdGet32 (PcdBootHartId))? TRUE: FALSE, 
);
+if (EFI_ERROR (Status)) {
+  DEBUG ((EFI_D_ERROR, "Faile to build U5MC processor informatino HOB\n"));
+  ASSERT (FALSE);
+}
+DEBUG ((EFI_D_INFO, "Support U5 application core on U500 platform, HOB 
Data at address 0x%x\n", GuidHobData));
+  }
+  DEBUG ((EFI_D_INFO, "Support %d U5 application cores on U500 platform\n", 
HartIdNumber - (UINT32)MCSupport));
+
+  if (HartIdNumber != FixedPcdGet32 (PcdHartCount)) {
+DEBUG ((EFI_D_ERROR, "Improper core settings...\n"));
+DEBUG ((EFI_D_ERROR, "PcdHartCount\n"));
+DEBUG ((EFI_D_ERROR, "PcdNumberofU5Cores\n"));
+DEBUG ((EFI_D_ERROR, "PcdE5MCSupported\n\n"));
+ASSERT (FALSE);
+  }
+  return Status;
+}
+
+/**
+  Function to build processor related SMBIOS information. RISC-V SMBIOS DXE 
driver collect
+  this information and build SMBIOS Type4 and Type7 record.
+
+  @param  ProcessorUidUnique ID of pysical processor which owns this core.
+  @param  

[edk2-devel] [PATCH 02/15] [platforms/devel-riscv]: Silicon/SiFive: Add library module of SiFive RISC-V cores

[Mr. Gilbert Chen]

From: Gilbert Chen 

Initial version of SiFive RISC-V core libraries. Library of each core creates 
processor core SMBIOS data hob for building SMBIOS records in DXE phase.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c| 248 +
 .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf|  57 
 .../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c| 300 +
 .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf|  57 
 .../Library/PeiCoreInfoHobLib/CoreInfoHob.c| 191 +
 .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf|  56 
 6 files changed, 909 insertions(+)
 create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
 create mode 100644 
Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
 create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
 create mode 100644 
Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
 create mode 100644 
Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
 create mode 100644 
Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf

diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c 
b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 000..1009b1e
--- /dev/null
+++ b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,248 @@
+/**@file
+  Build up platform processor information.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Function to build core specific information HOB. RISC-V SMBIOS DXE driver 
collect 
+  this information and build SMBIOS Type44.
+
+  @param  ParentProcessorGuidParent processor od this core. 
ParentProcessorGuid 
+ could be the same as CoreGuid if one 
processor has
+ only one core.
+  @param  ParentProcessorUid Unique ID of pysical processor which owns 
this core.
+  @param  HartId Hart ID of this core.
+  @param  IsBootHart TRUE means this is the boot HART. 
+  @param  GuidHobDataPointer to receive   EFI_HOB_GUID_TYPE.
+   
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51CoreProcessorSpecificDataHob (
+  IN EFI_GUID  *ParentProcessorGuid,
+  IN UINTN ParentProcessorUid,
+  IN UINTN HartId,
+  IN BOOLEAN   IsBootHart,
+  OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobData
+  )
+{
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *CoreGuidHob;
+  EFI_GUID *ProcessorSpecDataHobGuid;
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB ProcessorSpecDataHob;
+  struct sbi_scratch *ThisHartSbiScratch;
+  struct sbi_platform *ThisHartSbiPlatform;
+  EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+  EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific;
+
+  DEBUG ((EFI_D_INFO, "%a: Entry.\n", __FUNCTION__));
+
+  if (GuidHobData == NULL) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  ThisHartSbiScratch = sbi_hart_id_to_scratch (sbi_scratch_thishart_ptr(), 
(UINT32)HartId);
+  DEBUG ((EFI_D_INFO, "SBI Scratch is at 0x%x.\n", ThisHartSbiScratch));
+  ThisHartSbiPlatform = (struct sbi_platform 
*)sbi_platform_ptr(ThisHartSbiScratch);
+  DEBUG ((EFI_D_INFO, "SBI platform is at 0x%x.\n", ThisHartSbiPlatform));
+  FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT 
*)ThisHartSbiPlatform->firmware_context;
+  DEBUG ((EFI_D_INFO, "Firmware Context is at 0x%x.\n", FirmwareContext));
+  FirmwareContextHartSpecific = FirmwareContext->HartSpecific[HartId];
+  DEBUG ((EFI_D_INFO, "Firmware Context Hart specific is at 0x%x.\n", 
FirmwareContextHartSpecific));
+
+  //
+  // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+  //
+  CommonFirmwareContextHartSpecificInfo (
+  FirmwareContextHartSpecific,
+  ParentProcessorGuid,
+  ParentProcessorUid,
+  (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid),
+  HartId,
+  IsBootHart,
+  
+  );
+  ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L
 = TO_BE_FILLED;
+  

[edk2-devel] [PATCH 15/15] [platforms/devel-riscv]: Platforms: Readme file updates

[Mr. Gilbert Chen]

From: Gilbert Chen 

Update Readme.md and Maintainers.txt for RISV-V platforms.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Maintainers.txt | 9 +
 Readme.md   | 5 +
 2 files changed, 14 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index 876ae56..c494c9d 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -108,6 +108,11 @@ R: Marcin Wojtas 
 Platform/SolidRun/Armada80x0McBin
 R: Marcin Wojtas 
 
+Platform/RiscV
+Platform/RiscV/SiFive/U500Pkg
+R: Abner Chang 
+R: Gilbert Chen 
+
 Silicon
 M: Ard Biesheuvel 
 M: Leif Lindholm 
@@ -151,3 +156,7 @@ M: Liming Gao 
 
 Silicon/Marvell
 R: Marcin Wojtas 
+
+Silicon/SiFive
+R: Abner Chang 
+R: Gilbert Chen 
diff --git a/Readme.md b/Readme.md
index 63e59f6..4572d19 100644
--- a/Readme.md
+++ b/Readme.md
@@ -52,6 +52,7 @@ ARM | arm-linux-gnueabihf-
 IA32| i?86-linux-gnu-* _or_ x86_64-linux-gnu-
 IPF | ia64-linux-gnu
 X64 | x86_64-linux-gnu-
+RISCV64 | riscv64-unknown-elf-
 
 \* i386, i486, i586 or i686
 
@@ -243,6 +244,10 @@ For more information, see the
 ## Raspberry Pi
 * [Pi 3](Platform/RaspberryPi/RPi3)
 
+## RISC-V
+### SiFive
+* [Freedom U500 VC707 FPGA](Platform/RiscV/SiFive/U500Pkg)
+
 ## Socionext
 * [SynQuacer](Platform/Socionext/DeveloperBox)
 
-- 
2.7.4


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[edk2-devel] [PATCH 06/15] [platforms/devel-riscv]: RiscV/Universal: Initial version of common RISC-V SEC module

[Mr. Gilbert Chen]

From: Gilbert Chen 

Common RISC-V SEC module for RISC-V platforms.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s | 439 
 Platform/RiscV/Universal/Sec/SecMain.c  | 529 
 Platform/RiscV/Universal/Sec/SecMain.h  |  56 +++
 Platform/RiscV/Universal/Sec/SecMain.inf|  81 
 4 files changed, 1105 insertions(+)
 create mode 100644 Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s
 create mode 100644 Platform/RiscV/Universal/Sec/SecMain.c
 create mode 100644 Platform/RiscV/Universal/Sec/SecMain.h
 create mode 100644 Platform/RiscV/Universal/Sec/SecMain.inf

diff --git a/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s 
b/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s
new file mode 100644
index 000..a5ca481
--- /dev/null
+++ b/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s
@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2019 , Hewlett Packard Enterprise Development LP. All rights 
reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+.text
+.align 3
+.global ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+  /*
+   * Jump to warm-boot if this is not the selected core booting,
+   */
+  csrr a6, CSR_MHARTID
+  li a5, FixedPcdGet32 (PcdBootHartId)
+  bne a6, a5, _wait_for_boot_hart
+
+  // light LED on
+  li a5, 0x54002000
+  li a4, 0xff
+  sw a4, 0x08(a5)
+  li a4, 0x11
+  sw a4, 0x0c(a5)
+
+  li   ra, 0
+  call _reset_regs
+
+  /* Preload HART details
+   * s7 -> HART Count
+   * s8 -> HART Stack Size
+   */
+  li s7, FixedPcdGet32 (PcdHartCount)
+  li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
+
+  /* Setup scratch space for all the HARTs*/
+  li  tp, FixedPcdGet32 (PcdScratchRamBase)
+  mul  a5, s7, s8
+  add  tp, tp, a5
+  /* Keep a copy of tp */
+  add  t3, tp, zero
+  /* Counter */
+  li   t2, 1
+  /* hartid 0 is mandated by ISA */
+  li   t1, 0
+_scratch_init:
+  add  tp, t3, zero
+  mul  a5, s8, t1
+  sub  tp, tp, a5
+  li   a5, SBI_SCRATCH_SIZE
+  sub  tp, tp, a5
+
+  /* Initialize scratch space */
+  li  a4, FixedPcdGet32 (PcdFwStartAddress)
+  li  a5, FixedPcdGet32 (PcdFwEndAddress)
+  sub  a5, a5, a4
+  sd   a4, SBI_SCRATCH_FW_START_OFFSET(tp)
+  sd   a5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
+  /* Note: fw_next_arg1() uses a0, a1, and ra */
+  call fw_next_arg1
+  sd   a0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp)
+  /* Note: fw_next_addr() uses a0, a1, and ra */
+  call fw_next_addr
+  sd   a0, SBI_SCRATCH_NEXT_ADDR_OFFSET(tp)
+  li   a4, PRV_S
+  sd   a4, SBI_SCRATCH_NEXT_MODE_OFFSET(tp)
+  la   a4, _start_warm
+  sd   a4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp)
+  la   a4, platform
+  sd   a4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp)
+  la   a4, _hartid_to_scratch
+  sd   a4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp)
+  sd   zero, SBI_SCRATCH_TMP0_OFFSET(tp)
+#ifdef FW_OPTIONS
+  li   a4, FW_OPTIONS
+  sd   a4, SBI_SCRATCH_OPTIONS_OFFSET(tp)
+#else
+  sd   zero, SBI_SCRATCH_OPTIONS_OFFSET(tp)
+#endif
+  add  t1, t1, t2
+  blt  t1, s7, _scratch_init
+
+  /* Fill-out temporary memory with 55aa*/
+  li   a4, FixedPcdGet32 (PcdTemporaryRamBase)
+  li   a5, FixedPcdGet32 (PcdTemporaryRamSize)
+  add a5, a4, a5
+1:
+  li a3, 0x5AA55AA55AA55AA5
+  sd   a3, (a4)
+  add  a4, a4, __SIZEOF_POINTER__
+  blt  a4, a5, 1b
+
+  /* Update boot hart flag */
+  la   a4, _boot_hart_done
+  li   a5, 1
+  sd   a5, (a4)
+
+  /* Wait for boot hart */
+_wait_for_boot_hart:
+  la   a4, _boot_hart_done
+  ld   a5, (a4)
+  /* Reduce the bus traffic so that boot hart may proceed faster */
+  nop
+  nop
+  nop
+  beqz a5, _wait_for_boot_hart
+
+_start_warm:
+  li   ra, 0
+  call _reset_regs
+
+  /* Disable and clear all interrupts */
+  csrw CSR_MIE, zero
+  csrw CSR_MIP, zero
+
+  li s7, FixedPcdGet32 (PcdHartCount)
+  li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
+
+  /* HART ID should be within expected limit */
+  csrr s6, CSR_MHARTID
+  bge  s6, s7, _start_hang
+
+  /* find the scratch space for this hart */
+  li   tp, FixedPcdGet32 (PcdScratchRamBase)
+  mul  a5, s7, s8
+  add  tp, tp, a5
+  mul  a5, s8, s6
+  sub  tp, tp, a5
+  li   a5, SBI_SCRATCH_SIZE
+  sub  tp, tp, a5
+
+  /* update the mscratch */
+  csrw CSR_MSCRATCH, tp
+
+  /*make room for Hart specific Firmware Context*/
+  li   a5, FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE
+  sub  tp, tp, a5
+
+  /* Setup stack */
+  add sp, tp, zero
+
+  /* Setup stack for the Hart executing EFI to top of temporary ram*/
+  csrr a6, CSR_MHARTID
+  li a5, FixedPcdGet32 (PcdBootHartId)
+  bne a6, a5, 1f
+
+  li a4, FixedPcdGet32(PcdTemporaryRamBase)
+  li a5, FixedPcdGet32(PcdTemporaryRamSize)
+  add  sp, a4, a5
+  1:
+
+  /* Setup trap handler */
+  la   a4, _trap_handler
+  csrw CSR_MTVEC, a4
+  /* Make sure that mtvec is 

[edk2-devel] [PATCH 01/15] [platforms/devel-riscv]: Silicon/SiFive: Initial version of SiFive silicon package

[Mr. Gilbert Chen]

From: Gilbert Chen 

Add SiFive silicon EDK2 metafile and header files of SiFive RISC-V cores.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Silicon/SiFive/Include/Library/SiFiveE51.h | 66 ++
 Silicon/SiFive/Include/Library/SiFiveU54.h | 66 ++
 .../SiFive/Include/Library/SiFiveU54MCCoreplex.h   | 61 
 Silicon/SiFive/SiFive.dec  | 45 +++
 4 files changed, 238 insertions(+)
 create mode 100644 Silicon/SiFive/Include/Library/SiFiveE51.h
 create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54.h
 create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h
 create mode 100644 Silicon/SiFive/SiFive.dec

diff --git a/Silicon/SiFive/Include/Library/SiFiveE51.h 
b/Silicon/SiFive/Include/Library/SiFiveE51.h
new file mode 100644
index 000..96b1082
--- /dev/null
+++ b/Silicon/SiFive/Include/Library/SiFiveE51.h
@@ -0,0 +1,66 @@
+/** @file
+  SiFive E51 Core library definitions.
+   
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.  
+
+  This program and the accompanying materials are licensed and made available 
under 
+  the terms and conditions of the BSD License that accompanies this 
distribution.  
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.  

+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED. 
+
+**/
+#ifndef __SIFIVE_E51_CORE_H__
+#define __SIFIVE_E51_CORE_H__
+
+#include 
+
+#include 
+#include 
+
+/**
+  Function to build core specific information HOB.
+
+  @param  ParentProcessorGuidParent processor od this core. 
ParentProcessorGuid 
+ could be the same as CoreGuid if one 
processor has
+ only one core.
+  @param  ParentProcessorUid Unique ID of pysical processor which owns 
this core.
+  @param  HartId Hart ID of this core.
+  @param  IsBootHart TRUE means this is the boot HART. 
+  @param  GuidHobDataPointer to receive 
RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+   
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51CoreProcessorSpecificDataHob (
+  IN EFI_GUID  *ParentProcessorGuid,
+  IN UINTN ParentProcessorUid,
+  IN UINTN HartId,
+  IN BOOLEAN   IsBootHart,
+  OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobData
+  );
+
+/**
+  Function to build processor related SMBIOS information. RISC-V SMBIOS DXE 
driver collect 
+  this information and build SMBIOS Type4 and Type7 record.
+
+  @param  ProcessorUidUnique ID of pysical processor which owns this core.
+  @param  SmbiosHobPtrPointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_HOB. 
The pointers 
+  maintained in this structure is only valid before 
memory is discovered.
+  Access to those pointers after memory is installed 
will cause unexpected issues. 
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51ProcessorSmbiosDataHob (
+  IN UINTN ProcessorUid,
+  OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr
+  );
+
+#endif
diff --git a/Silicon/SiFive/Include/Library/SiFiveU54.h 
b/Silicon/SiFive/Include/Library/SiFiveU54.h
new file mode 100644
index 000..216b584
--- /dev/null
+++ b/Silicon/SiFive/Include/Library/SiFiveU54.h
@@ -0,0 +1,66 @@
+/** @file
+  SiFive U54 Core library definitions.
+   
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.  
+
+  This program and the accompanying materials are licensed and made available 
under 
+  the terms and conditions of the BSD License that accompanies this 
distribution.  
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.  

+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED. 
+
+**/
+#ifndef __SIFIVE_U54_CORE_H__
+#define __SIFIVE_U54_CORE_H__
+
+#include 
+
+#include 
+#include 
+
+/**
+  Function to build core specific information HOB.
+
+  @param  ParentProcessorGuidParent processor od this core. 
ParentProcessorGuid 
+ could be the same as CoreGuid if one 
processor has
+ only one core.
+  @param  ParentProcessorUid Unique ID of pysical processor which owns 
this core.
+  @param  HartId Hart ID of this core.
+  @param  IsBootHart TRUE means this is the boot HART. 
+  @param  GuidHobdataPointer to 

[edk2-devel] [PATCH 13/15] [platforms/devel-riscv]: U500Pkg/TimerDxe: Platform Timer DXE driver

[Mr. Gilbert Chen]

From: Gilbert Chen 

Timer DXE driver for U500 platform based U500 platform implementation specifc 
timer registers.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c  | 317 +
 .../SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h  | 179 
 .../U500Pkg/Universal/Dxe/TimerDxe/Timer.uni   | Bin 0 -> 1678 bytes
 .../U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf|  54 
 .../U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni  | Bin 0 -> 1374 bytes
 5 files changed, 550 insertions(+)
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.uni
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni

diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
new file mode 100644
index 000..8f8eeb6
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
@@ -0,0 +1,317 @@
+/** @file
+  RISC-V Timer Architectural Protocol for U500 platform.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution. The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include "Timer.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CLINT_REG_MTIME 0x0200BFF8
+#define CLINT_REG_MTIMECMP0 0x02004000
+#define CLINT_REG_MTIMECMP1 0x02004008
+#define CLINT_REG_MTIMECMP2 0x02004010
+#define CLINT_REG_MTIMECMP3 0x02004018
+#define CLINT_REG_MTIMECMP4 0x02004020
+
+static volatile void * const p_mtime = (void *)CLINT_REG_MTIME;
+#define MTIME  (*p_mtime)
+#define MTIMECMP(i)(p_mtimecmp[i])
+
+//
+// The handle onto which the Timer Architectural Protocol will be installed
+//
+EFI_HANDLEmTimerHandle = NULL;
+
+//
+// The Timer Architectural Protocol that this driver produces
+//
+EFI_TIMER_ARCH_PROTOCOL   mTimer = {
+  TimerDriverRegisterHandler,
+  TimerDriverSetTimerPeriod,
+  TimerDriverGetTimerPeriod,
+  TimerDriverGenerateSoftInterrupt
+};
+
+//
+// Pointer to the CPU Architectural Protocol instance
+//
+EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+//
+// The notification function to call on every timer interrupt.
+// A bug in the compiler prevents us from initializing this here.
+//
+EFI_TIMER_NOTIFY mTimerNotifyFunction;
+
+//
+// The current period of the timer interrupt
+//
+volatile UINT64 mTimerPeriod = 0;
+
+
+/**
+  8254 Timer #0 Interrupt Handler.
+
+  @param InterruptTypeThe type of interrupt that occured
+  @param SystemContextA pointer to the system context when the interrupt 
occured
+**/
+
+VOID
+EFIAPI
+TimerInterruptHandler (
+  IN EFI_EXCEPTION_TYPE   InterruptType,
+  IN EFI_SYSTEM_CONTEXT   SystemContext
+  )
+{
+  EFI_TPL OriginalTPL;
+  UINT64 RiscvTimer;
+
+  csr_clear(CSR_SIE, MIP_STIP); // enable timer int
+  OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+  if (mTimerPeriod == 0) {
+gBS->RestoreTPL (OriginalTPL);
+mCpu->DisableInterrupt(mCpu);
+return;
+  }
+  if (mTimerNotifyFunction != NULL) {
+mTimerNotifyFunction (mTimerPeriod);
+  }
+  gBS->RestoreTPL (OriginalTPL);
+
+
+  RiscvTimer = readq_relaxed(p_mtime);
+  sbi_set_timer(RiscvTimer += mTimerPeriod);
+  csr_set(CSR_SIE, MIP_STIP); // enable timer int
+
+}
+
+/**
+
+  This function registers the handler NotifyFunction so it is called every time
+  the timer interrupt fires.  It also passes the amount of time since the last
+  handler call to the NotifyFunction.  If NotifyFunction is NULL, then the
+  handler is unregistered.  If the handler is registered, then EFI_SUCCESS is
+  returned.  If the CPU does not support registering a timer interrupt handler,
+  then EFI_UNSUPPORTED is returned.  If an attempt is made to register a 
handler
+  when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+  If an attempt is made to unregister a handler when a handler is not 
registered,
+  then EFI_INVALID_PARAMETER is returned.  If an error occurs attempting to
+  register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+  is returned.
+
+  @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+  @param NotifyFunction   The function to call when a timer interrupt fires.  
This
+  function executes at 

[edk2-devel] [PATCH 11/15] [platforms/devel-riscv]: U500Pkg/Library: Library instances of U500 platform library.

[Mr. Gilbert Chen]

From: Gilbert Chen 

PeiCoreInfoHobLib
- This is the library to create RISC-V core characteristics for building up 
RISC-V related SMBIOS records to support the unified boot loader and OS image.

- RiscVPlatformTimerLib
This is U500 platform timer library which has the platform-specific timer 
implementation.

- SerialPortLib
U500 serial port platform library

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../Library/PeiCoreInfoHobLib/CoreInfoHob.c| 201 +
 .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf|  64 ++
 .../RiscVPlatformTimerLib.inf  |  46 
 .../RiscVPlatformTimerLib/RiscVPlatformTimerLib.s  |  54 +
 .../U500Pkg/Library/SerialIoLib/SerialIoLib.inf|  37 +++
 .../U500Pkg/Library/SerialIoLib/SerialPortLib.c| 247 +
 .../Library/SerialIoLib/U500SerialPortLib.uni  |  22 ++
 7 files changed, 671 insertions(+)
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.s
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib.uni

diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c 
b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 000..2db4fdc
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,201 @@
+/**@file
+  Build up platform processor information.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Build up processor-specific HOB for U5MC Coreplex
+
+  @param  UniqueId  Unique ID of this U5MC Coreplex processor
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCCoreplexProcessorSpecificDataHob (
+  IN UINTN UniqueId
+  )
+{
+  EFI_STATUS Status;
+  UINT32 HartIdNumber;
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *GuidHobData;
+  EFI_GUID *ParentCoreGuid;
+  BOOLEAN MCSupport;
+
+  DEBUG ((EFI_D_INFO, "Building U5 Coreplex processor information HOB\n"));
+
+  HartIdNumber = 0;
+  ParentCoreGuid = PcdGetPtr(PcdSiFiveU5MCCoreplexGuid); 
+  MCSupport = PcdGetBool (PcdE5MCSupported);
+  if (MCSupport == TRUE) {
+Status = CreateE51CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, 
HartIdNumber, FALSE, );
+if (EFI_ERROR (Status)) {
+  DEBUG ((EFI_D_ERROR, "Faile to build U5MC processor informatino HOB\n"));
+  ASSERT (FALSE);
+}
+HartIdNumber ++;
+DEBUG ((EFI_D_INFO, "Support E5 Monitor core on U500 platform, HOB at 
address 0x%x\n", GuidHobData));
+  }
+  for (; HartIdNumber < (FixedPcdGet32 (PcdNumberofU5Cores) + 
(UINT32)MCSupport); HartIdNumber ++) {
+Status = CreateU54CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, 
HartIdNumber, (HartIdNumber == FixedPcdGet32 (PcdBootHartId))? TRUE: FALSE, 
);
+if (EFI_ERROR (Status)) {
+  DEBUG ((EFI_D_ERROR, "Faile to build U5MC processor informatino HOB\n"));
+  ASSERT (FALSE);
+}
+DEBUG ((EFI_D_INFO, "Support U5 application core on U500 platform, HOB 
Data at address 0x%x\n", GuidHobData));
+  }
+  DEBUG ((EFI_D_INFO, "Support %d U5 application cores on U500 platform\n", 
HartIdNumber - (UINT32)MCSupport));
+
+  if (HartIdNumber != FixedPcdGet32 (PcdHartCount)) {
+DEBUG ((EFI_D_ERROR, "Improper core settings...\n"));
+DEBUG ((EFI_D_ERROR, "PcdHartCount\n"));
+DEBUG ((EFI_D_ERROR, "PcdNumberofU5Cores\n"));
+DEBUG ((EFI_D_ERROR, "PcdE5MCSupported\n\n"));
+ASSERT (FALSE);
+  }
+  return Status; 
+}
+
+/**
+  Function to build processor related SMBIOS information. RISC-V SMBIOS DXE 
driver collect 
+  this information and build SMBIOS Type4 and Type7 record.
+
+  @param  ProcessorUidUnique ID of pysical processor which owns 

[edk2-devel] [PATCH 14/15] [platforms/devel-riscv]: U500Pkg/PlatformPei: Platform initialization PEIM

[Mr. Gilbert Chen]

This is the platform-implementation specific library which is executed in early 
PEI phase for platform initialization.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c  |  55 
 .../U500Pkg/Universal/Pei/PlatformPei/MemDetect.c  |  80 ++
 .../U500Pkg/Universal/Pei/PlatformPei/Platform.c   | 319 +
 .../U500Pkg/Universal/Pei/PlatformPei/Platform.h   |  97 +++
 .../Universal/Pei/PlatformPei/PlatformPei.inf  |  82 ++
 5 files changed, 633 insertions(+)
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.inf

diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
new file mode 100644
index 000..04ac7ac
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
@@ -0,0 +1,55 @@
+/** @file
+  Build FV related hobs for platform.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PiPei.h"
+#include "Platform.h"
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
+  and DXE know about them.
+
+  @retval EFI_SUCCESS   Platform PEI FVs were initialized successfully.
+
+**/
+EFI_STATUS
+PeiFvInitialization (
+  VOID
+  )
+{
+  DEBUG ((EFI_D_INFO, "Platform PEI Firmware Volume Initialization\n"));
+  //
+  // Let DXE know about the DXE FV
+  //
+  BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize));
+  DEBUG ((EFI_D_INFO, "Platform builds DXE FV at %x, size %x.\n", PcdGet32 
(PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize)));
+
+  //
+  // Let PEI know about the DXE FV so it can find the DXE Core
+  //
+  PeiServicesInstallFvInfoPpi (
+NULL,
+(VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase),
+PcdGet32 (PcdRiscVDxeFvSize),
+NULL,
+NULL
+);
+
+  return EFI_SUCCESS;
+}
diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
new file mode 100644
index 000..3c047f1
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
@@ -0,0 +1,80 @@
+/**@file
+  Memory Detection for Virtual Machines.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  MemDetect.c
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "Platform.h"
+
+
+/**
+  Publish PEI core memory
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+PublishPeiMemory (
+  VOID
+  )
+{
+  EFI_STATUS  Status;
+  EFI_PHYSICAL_ADDRESSMemoryBase;
+  UINT64  MemorySize;
+
+  MemoryBase = 0x8000UL + 0x100UL;
+  MemorySize = 0x4000UL - 0x100UL; //1GB - 16MB
+
+  DEBUG((EFI_D_INFO, "%a: MemoryBase:0x%x MemorySize:%d\n", __FUNCTION__, 
MemoryBase, MemorySize));
+
+  //
+  // Publish this memory to the PEI Core
+  //
+  Status = PublishSystemMemory(MemoryBase, MemorySize);
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
+/**
+  Publish system RAM and reserve memory regions
+
+**/
+VOID
+InitializeRamRegions (
+  VOID
+  )
+{
+  AddMemoryRangeHob(0x8100UL, 0x8100UL + 0x3F00UL);
+
+}
diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c 

[edk2-devel] [PATCH 10/15] [platforms/devel-riscv]: U500Pkg/Library: Library instances of U500 platform library.

[Mr. Gilbert Chen]

From: Gilbert Chen 

OpneSbiPlatformLib
- In order to reduce the dependencies with RISC-V OpenSBI project 
(https://github.com/riscv/opensbi) and less burdens to EDK2 build process, the 
implementation of RISC-V EDK2 platform is leverage platform source code from 
OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib is cloned from 
RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build 
environment.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../OpenSbiPlatformLib/OpenSbiPlatformLib.inf  |  53 +
 .../U500Pkg/Library/OpenSbiPlatformLib/platform.c  | 214 +
 2 files changed, 267 insertions(+)
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c

diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
 
b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
new file mode 100644
index 000..1823e48
--- /dev/null
+++ 
b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
@@ -0,0 +1,53 @@
+## @file
+#  RISC-V OpenSbi Platform Library
+#  This is the the required library which provides platform
+#  level opensbi functions follow RISC-V opensbi implementation.
+#
+#  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution. The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = OpenSbiPlatformLib
+  FILE_GUID  = 9424ED54-EBDA-4FB5-8FF6-8291B07BB151
+  MODULE_TYPE= SEC
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = OpenSbiPlatformLib
+
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+#  VALID_ARCHITECTURES   = RISCV64 EBC
+#
+
+[Sources]
+  platform.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  RiscVPkg/RiscVPkg.dec
+  Platform/RiscV/RiscVPlatformPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  BaseMemoryLib
+  PcdLib
+  DebugAgentLib
+  RiscVCpuLib
+  PrintLib
+
+[FixedPcd]
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c 
b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
new file mode 100644
index 000..887a279
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
@@ -0,0 +1,214 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ * 
+ * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Atish Patra 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+#define U500_HART_COUNTFixedPcdGet32(PcdHartCount)
+#define U500_HART_STACK_SIZE   FixedPcdGet32(PcdOpenSbiStackSize)
+#define U500_BOOT_HART_ID   FixedPcdGet32(PcdBootHartId)
+
+#define U500_SYS_CLK   1
+
+#define U500_CLINT_ADDR0x200
+
+#define U500_PLIC_ADDR 0xc00
+#define U500_PLIC_NUM_SOURCES  0x35
+#define U500_PLIC_NUM_PRIORITIES   7
+
+#define U500_UART_ADDR 0x5400
+
+#define U500_UART_BAUDRATE 115200
+
+/**
+ * The U500 SoC has 8 HARTs but HART ID 0 doesn't have S mode.
+ * HARTs 1 is selected as boot HART
+ */
+#ifndef U500_ENABLED_HART_MASK
+#define U500_ENABLED_HART_MASK (1 << U500_BOOT_HART_ID)
+#endif
+
+#define U500_HARTID_DISABLED   ~(U500_ENABLED_HART_MASK)
+
+/* PRCI clock related macros */
+//TODO: Do we need a separate driver for this ?
+#define U500_PRCI_BASE_ADDR0x1000
+#define U500_PRCI_CLKMUXSTATUSREG  0x002C
+#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL   (0x1 << 1)
+
+static void U500_modify_dt(void *fdt)
+{
+   u32 i, size;
+   int chosen_offset, err;
+   int cpu_offset;
+   char cpu_node[32] = "";
+   const char *mmu_type;
+
+   for (i = 0; i < U500_HART_COUNT; i++) {
+   sbi_sprintf(cpu_node, "/cpus/cpu@%d", i);
+   cpu_offset = fdt_path_offset(fdt, cpu_node);
+   

[edk2-devel] [PATCH 04/15] [platforms/devel-riscv]: RiscV/Include: Initial version of header files in RISC-V platform package

[Mr. Gilbert Chen]

FirmwareContextProcessorSpecificLib.h
- The difinitions of Firmware Context EDK2 implementaion based on RISC-V 
OpenSBI.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../Library/FirmwareContextProcessorSpecificLib.h  | 47 ++
 1 file changed, 47 insertions(+)
 create mode 100644 
Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h

diff --git 
a/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h 
b/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h
new file mode 100644
index 000..3bfd39f
--- /dev/null
+++ b/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h
@@ -0,0 +1,47 @@
+
+/** @file
+  Firmware Context Processor-specific common library
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License that accompanies this 
distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H__
+#define __FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H__
+
+#include 
+
+/**
+  Build up common firmware context processor-specific information
+
+  @param  FirmwareContextHartSpecific  Pointer to 
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
+  @param  ParentProcessorGuid  Pointer to GUID of Processor which 
contains this core
+  @param  ParentProcessorUid   Unique ID of pysical processor which 
owns this core.
+  @param  CoreGuid Pointer to GUID of core
+  @param  HartId   Hart ID of this core.
+  @param  IsBootHart   This is boot hart or not
+  @param  ProcessorSpecDataHob Pointer to 
RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+
+  @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CommonFirmwareContextHartSpecificInfo (
+  EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
+  EFI_GUID  *ParentProcessorGuid,
+  UINTN ParentProcessorUid,
+  EFI_GUID  *CoreGuid,
+  UINTN HartId,
+  BOOLEAN   IsBootHart,
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecDataHob
+  );
+
+#endif
--
2.7.4


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[edk2-devel] [PATCH 03/15] [platforms/devel-riscv]: platforms/RiscV: Initial version of RISC-V platform package

[Mr. Gilbert Chen]

From: Gilbert Chen 

Initial version of RISC-V platform package which provides the common libraries, 
drivers, PCD and etc. for RISC-V platform development.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Platform/RiscV/Readme.md |  88 +++
 Platform/RiscV/RiscVPlatformPkg.dec  |  75 ++
 Platform/RiscV/RiscVPlatformPkg.uni  | Bin 0 -> 1754 bytes
 Platform/RiscV/RiscVPlatformPkgExtra.uni | Bin 0 -> 1392 bytes
 4 files changed, 163 insertions(+)
 create mode 100644 Platform/RiscV/Readme.md
 create mode 100644 Platform/RiscV/RiscVPlatformPkg.dec
 create mode 100644 Platform/RiscV/RiscVPlatformPkg.uni
 create mode 100644 Platform/RiscV/RiscVPlatformPkgExtra.uni

diff --git a/Platform/RiscV/Readme.md b/Platform/RiscV/Readme.md
new file mode 100644
index 000..dd817eb
--- /dev/null
+++ b/Platform/RiscV/Readme.md
@@ -0,0 +1,88 @@
+# Introduction
+
+## EDK2 RISC-V Platform Package
+RISC-V platform package provides the generic and common modules for RISC-V 
platforms. RISC-V platform package could include RiscPlatformPkg.dec to use the 
common drivers, libraries, definitions, PCDs and etc. for the platform 
development. 
+
+## EDK2 RISC-V Platforms
+RISC-V platform is created and maintained by RISC-V platform vendors. The 
directory of RISC-V platform should be created under Platform/RiscV. Vendor 
should create the folder under Platform/RiscV and name it using vendor name, 
under the vendor folder is the platform folder named by platform model name, 
code name or etc. (e.g. Platform/RiscV/SiFive/U500Pkg)
+
+## Build EDK2 RISC-V Platforms
+RISC-V platform package should provide EDK2 metafiles under RISC-V platform 
package folder (Platform/RiscV/{Vendor}/{Platform}). Build RISC-V platform 
package against edk2 and follow the build guidence mentioned in Readme.md under 
below link.
+https://github.com/tianocore/edk2-platforms
+
+### Download the sources ###
+```
+git clone https://github.com/tianocore/edk2-staging.git
+# Checkout RISC-V branch
+git clone https://github.com/tianocore/edk2-platforms.git
+# Checkout devel-riscv branch
+git clone https://github.com/tianocore/edk2-non-osi.git
+```
+
+### Requirements
+Build EDK2 RISC-V platform requires GCC RISC-V toolchain. Refer to 
https://github.com/riscv/riscv-gnu-toolchain for the details.
+
+### EDK2 project
+Currently, the EDK2 RISC-V platform can only build with edk2 project in 
**edk2-staging/RISC-V** branch. The build architecture whcih is supported and 
verified so far is "RISCV64". The verified RISC-V toolchain is GCC 7.1.1, 
toolchain tag is "GCC711RISCV" declared in tools_def.txt
+
+### Linux Build Instructions
+You can build the RISC-V platform using below script, 
+`build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t 
GCC711RISCV`
+
+Or modify target.txt to set up your build parameters.
+
+## RISC-V Platform PCD settings
+### EDK2 Firmware Volume Settings
+EDK2 Firmware volume related PCDs which declared in platform FDF file.
+
+| **PCD name** |**Usage**|
+||--|
+|PcdRiscVSecFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVSecFvSize| The size of SEC Firmware Volume|
+|PcdRiscVPeiFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVPeiFvSize| The size of SEC Firmware Volume|
+|PcdRiscVDxeFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVDxeFvSize| The size of SEC Firmware Volume|
+
+### EDK2 EFI Variable Region Settings
+The PCD settings regard to EFI Variable
+
+| **PCD name** |**Usage**|
+||--|
+|PcdVariableFdBaseAddress| The EFI variable firmware device base address|
+|PcdVariableFdSize| The EFI variable firmware device size|
+|PcdVariableFdBlockSize| The block size of EFI variable firmware device|
+|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within 
firmware device|
+|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable 
fault tolerance worksapce (FTW) within firmware device|
+|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable spare 
FTW within firmware device|
+
+### RISC-V Physical Memory Protection (PMP) Region Settings
+Below PCDs could be set in platform FDF file.
+
+| **PCD name** |**Usage**|
+||--|
+|PcdFwStartAddress| The starting address of firmware region to protected by 
PMP|
+|PcdFwEndAddress| The ending address of firmware region to protected by PMP|
+
+### RISC-V Processor HART Settings
+
+| **PCD name** |**Usage**|
+||--|
+|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation 
specific|
+|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot 
system to OS|
+
+### RISC-V OpenSBI Settings
+
+| **PCD name** |**Usage**|
+||--|
+|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RISC-V 
HARTs|
+|PcdScratchRamSize| The total size of 

[edk2-devel] [PATCH 08/15] [platforms/devel-riscv]: U500Pkg/Include: Header files of SiFive U500 platform

[Mr. Gilbert Chen]

From: Gilbert Chen 

The initial header file commit for SiFive U5-MC Coreplex and U500 Core Local 
interrupt definitions.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h| 57 ++
 Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h  | 24 +
 2 files changed, 81 insertions(+)
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h

diff --git a/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h 
b/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h
new file mode 100644
index 000..c0323a5
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h
@@ -0,0 +1,57 @@
+/** @file
+  SiFive U54 Coreplex library definitions.
+   
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.  
+
+  This program and the accompanying materials are licensed and made available 
under 
+  the terms and conditions of the BSD License that accompanies this 
distribution.  
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.  

+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED. 
+
+**/
+#ifndef __SIFIVE_U5MC_COREPLEX_H__
+#define __SIFIVE_U5MC_COREPLEX_H__
+
+#include 
+
+#include 
+#include 
+
+#define SIFIVE_U5MC_COREPLEX_MC_HART_ID 0
+
+/**
+  Build up U5MC coreplex processor core-specific information.
+
+  @param  UniqueId  U5MC unique ID.
+
+  @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCCoreplexProcessorSpecificDataHob (
+  IN UINTN UniqueId
+  );
+
+/**
+  Function to build processor related SMBIOS information. RISC-V SMBIOS DXE 
driver collect 
+  this information and build SMBIOS Type4 and Type7 record.
+
+  @param  ProcessorUidUnique ID of pysical processor which owns this 
core.
+  @param  SmbiosDataHobPtrPointer to receive 
RISC_V_PROCESSOR_SMBIOS_DATA_HOB. The pointers 
+  maintained in this structure is only valid 
before memory is discovered.
+  Access to those pointers after memory is 
installed will cause unexpected issues. 
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCProcessorSmbiosDataHob (
+  IN UINTN ProcessorUid,
+  OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosDataHobPtr
+  );
+#endif
diff --git a/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h 
b/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h
new file mode 100644
index 000..426bf43
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h
@@ -0,0 +1,24 @@
+/** @file
+  RISC-V Timer Architectural definition for U500 platform.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution. The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#ifndef _U500_H_
+#define _U500_H_
+
+#define CLINT_REG_MTIME 0x0200BFF8
+#define CLINT_REG_MTIMECMP0 0x02004000
+#define CLINT_REG_MTIMECMP1 0x02004008
+#define CLINT_REG_MTIMECMP2 0x02004010
+#define CLINT_REG_MTIMECMP3 0x02004018
+#define CLINT_REG_MTIMECMP4 0x02004020
+
+#endif
\ No newline at end of file
-- 
2.7.4


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[edk2-devel] [PATCH 12/15] [platforms/devel-riscv]: U500Pkg/RamFvbServiceruntimeDxe: FVB driver for EFI variable.

[Mr. Gilbert Chen]

Firmware Volume Block driver instance for ram based EFI variable on U500 
platform.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c |  133 +++
 .../FvbServicesRuntimeDxe.inf  |   88 ++
 .../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c  | 1129 
 .../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h  |  193 
 .../RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c   |  156 +++
 .../Dxe/RamFvbServicesRuntimeDxe/RamFlash.c|  151 +++
 .../Dxe/RamFvbServicesRuntimeDxe/RamFlash.h|   92 ++
 .../Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c |   26 +
 8 files changed, 1968 insertions(+)
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c

diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
new file mode 100644
index 000..bfed741
--- /dev/null
+++ 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
@@ -0,0 +1,133 @@
+/**@file
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2006, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Module Name:
+
+FvbInfo.c
+
+  Abstract:
+
+Defines data structure that is the volume header found.These data is intent
+to decouple FVB driver with FV header.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The protocols, PPI and GUID defintions for this module
+//
+#include 
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+
+typedef struct {
+  UINT64  FvLength;
+  EFI_FIRMWARE_VOLUME_HEADER  FvbInfo;
+  //
+  // EFI_FV_BLOCK_MAP_ENTRYExtraBlockMap[n];//n=0
+  //
+  EFI_FV_BLOCK_MAP_ENTRY  End[1];
+} EFI_FVB_MEDIA_INFO;
+
+EFI_FVB_MEDIA_INFO  mPlatformFvbMediaInfo[] = {
+  //
+  // Systen NvStorage FVB
+  //
+  {
+FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+{
+  {
+0,
+  },  // ZeroVector[16]
+  EFI_SYSTEM_NV_DATA_FV_GUID,
+  FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+  FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+  FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+  EFI_FVH_SIGNATURE,
+  EFI_FVB2_MEMORY_MAPPED |
+EFI_FVB2_READ_ENABLED_CAP |
+EFI_FVB2_READ_STATUS |
+EFI_FVB2_WRITE_ENABLED_CAP |
+EFI_FVB2_WRITE_STATUS |
+EFI_FVB2_ERASE_POLARITY |
+EFI_FVB2_ALIGNMENT_16,
+  sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
+  0,  // CheckSum
+  0,  // ExtHeaderOffset
+  {
+0,
+  },  // Reserved[1]
+  2,  // Revision
+  {
+{
+  (FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+   FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+   FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)) /
+  FixedPcdGet32 (PcdVariableFdBlockSize),
+  FixedPcdGet32 (PcdVariableFdBlockSize),
+}
+  } // BlockMap[1]
+},
+{
+  {
+0,
+0
+  }
+}  // End[1]
+  }
+};
+
+EFI_STATUS
+GetFvbInfo (
+  IN  UINT64FvLength,
+  OUT EFI_FIRMWARE_VOLUME_HEADER**FvbInfo
+  )
+{
+  STATIC BOOLEAN Checksummed = FALSE;
+  UINTN Index;
+
+  if (!Checksummed) {
+for (Index = 0;
+ Index < sizeof (mPlatformFvbMediaInfo) / sizeof (EFI_FVB_MEDIA_INFO);
+ Index += 1) {
+  UINT16 Checksum;
+  mPlatformFvbMediaInfo[Index].FvbInfo.Checksum = 0;
+  Checksum = 

[edk2-devel] [PATCH 09/15] [platforms/devel-riscv]: U500Pkg/Library: Initial version of PlatformBootManagerLib

[Mr. Gilbert Chen]

From: Gilbert Chen 

SiFive RISC-V U500 Platform Boot Manager library.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../Library/PlatformBootManagerLib/MemoryTest.c| 1110 
 .../PlatformBootManagerLib/PlatformBootManager.c   |  269 +
 .../PlatformBootManagerLib/PlatformBootManager.h   |  141 +++
 .../PlatformBootManagerLib.inf |   72 ++
 .../Library/PlatformBootManagerLib/PlatformData.c  |   54 +
 .../Library/PlatformBootManagerLib/Strings.uni |  Bin 0 -> 3922 bytes
 6 files changed, 1646 insertions(+)
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManager.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManager.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformData.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/Strings.uni

diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c 
b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
new file mode 100644
index 000..841e3d9
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
@@ -0,0 +1,1110 @@
+/** @file
+  Perform the RISC-V platform memory test
+
+Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD 
License
+which accompanies this distribution.  The full text of the license may be 
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformBootManager.h"
+
+EFI_HII_HANDLE gStringPackHandle = NULL;
+EFI_GUID   mPlatformBootManagerStringPackGuid = {
+  0x154dd51, 0x9079, 0x4a10, { 0x89, 0x5c, 0x9c, 0x7, 0x72, 0x81, 0x57, 0x88 }
+  };
+// extern UINT8  BdsDxeStrings[];
+
+//
+// BDS Platform Functions
+//
+/**
+
+  Show progress bar with title above it. It only works in Graphics mode.
+
+  @param TitleForeground Foreground color for Title.
+  @param TitleBackground Background color for Title.
+  @param Title   Title above progress bar.
+  @param ProgressColor   Progress bar color.
+  @param ProgressProgress (0-100)
+  @param PreviousValue   The previous value of the progress.
+
+  @retval  EFI_STATUS   Success update the progress bar
+
+**/
+EFI_STATUS
+PlatformBootManagerShowProgress (
+  IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
+  IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
+  IN CHAR16*Title,
+  IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
+  IN UINTN Progress,
+  IN UINTN PreviousValue
+  )
+{
+  EFI_STATUS Status;
+  EFI_GRAPHICS_OUTPUT_PROTOCOL   *GraphicsOutput;
+  EFI_UGA_DRAW_PROTOCOL  *UgaDraw;
+  UINT32 SizeOfX;
+  UINT32 SizeOfY;
+  UINT32 ColorDepth;
+  UINT32 RefreshRate;
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL  Color;
+  UINTN  BlockHeight;
+  UINTN  BlockWidth;
+  UINTN  BlockNum;
+  UINTN  PosX;
+  UINTN  PosY;
+  UINTN  Index;
+
+  if (Progress > 100) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  UgaDraw = NULL;
+  Status = gBS->HandleProtocol (
+  gST->ConsoleOutHandle,
+  ,
+  (VOID **) 
+  );
+  if (EFI_ERROR (Status) && FeaturePcdGet (PcdUgaConsumeSupport)) {
+GraphicsOutput = NULL;
+
+Status = gBS->HandleProtocol (
+gST->ConsoleOutHandle,
+,
+(VOID **) 
+);
+  }
+  if (EFI_ERROR (Status)) {
+return EFI_UNSUPPORTED;
+  }
+
+  SizeOfX = 0;
+  SizeOfY = 0;
+  if (GraphicsOutput != NULL) {
+SizeOfX = GraphicsOutput->Mode->Info->HorizontalResolution;
+SizeOfY = GraphicsOutput->Mode->Info->VerticalResolution;
+  } else if (UgaDraw != NULL) {
+Status = UgaDraw->GetMode (
+UgaDraw,
+,
+,
+,
+
+);
+if (EFI_ERROR (Status)) {
+  return EFI_UNSUPPORTED;
+}
+  } else {
+return EFI_UNSUPPORTED;
+  }
+
+ 

[edk2-devel] [PATCH 09/15] [platforms/devel-riscv]: U500Pkg/Library: Initial version of PlatformBootManagerLib

[Mr. Gilbert Chen]

SiFive RISC-V U500 Platform Boot Manager library.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../Library/PlatformBootManagerLib/MemoryTest.c| 1110 
 .../PlatformBootManagerLib/PlatformBootManager.c   |  269 +
 .../PlatformBootManagerLib/PlatformBootManager.h   |  141 +++
 .../PlatformBootManagerLib.inf |   72 ++
 .../Library/PlatformBootManagerLib/PlatformData.c  |   54 +
 .../Library/PlatformBootManagerLib/Strings.uni |  Bin 0 -> 3922 bytes
 6 files changed, 1646 insertions(+)
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManager.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManager.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformData.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/Strings.uni

diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c 
b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
new file mode 100644
index 000..841e3d9
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
@@ -0,0 +1,1110 @@
+/** @file
+  Perform the RISC-V platform memory test
+
+Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD 
License
+which accompanies this distribution.  The full text of the license may be 
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformBootManager.h"
+
+EFI_HII_HANDLE gStringPackHandle = NULL;
+EFI_GUID   mPlatformBootManagerStringPackGuid = {
+  0x154dd51, 0x9079, 0x4a10, { 0x89, 0x5c, 0x9c, 0x7, 0x72, 0x81, 0x57, 0x88 }
+  };
+// extern UINT8  BdsDxeStrings[];
+
+//
+// BDS Platform Functions
+//
+/**
+
+  Show progress bar with title above it. It only works in Graphics mode.
+
+  @param TitleForeground Foreground color for Title.
+  @param TitleBackground Background color for Title.
+  @param Title   Title above progress bar.
+  @param ProgressColor   Progress bar color.
+  @param ProgressProgress (0-100)
+  @param PreviousValue   The previous value of the progress.
+
+  @retval  EFI_STATUS   Success update the progress bar
+
+**/
+EFI_STATUS
+PlatformBootManagerShowProgress (
+  IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
+  IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
+  IN CHAR16*Title,
+  IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
+  IN UINTN Progress,
+  IN UINTN PreviousValue
+  )
+{
+  EFI_STATUS Status;
+  EFI_GRAPHICS_OUTPUT_PROTOCOL   *GraphicsOutput;
+  EFI_UGA_DRAW_PROTOCOL  *UgaDraw;
+  UINT32 SizeOfX;
+  UINT32 SizeOfY;
+  UINT32 ColorDepth;
+  UINT32 RefreshRate;
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL  Color;
+  UINTN  BlockHeight;
+  UINTN  BlockWidth;
+  UINTN  BlockNum;
+  UINTN  PosX;
+  UINTN  PosY;
+  UINTN  Index;
+
+  if (Progress > 100) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  UgaDraw = NULL;
+  Status = gBS->HandleProtocol (
+  gST->ConsoleOutHandle,
+  ,
+  (VOID **) 
+  );
+  if (EFI_ERROR (Status) && FeaturePcdGet (PcdUgaConsumeSupport)) {
+GraphicsOutput = NULL;
+
+Status = gBS->HandleProtocol (
+gST->ConsoleOutHandle,
+,
+(VOID **) 
+);
+  }
+  if (EFI_ERROR (Status)) {
+return EFI_UNSUPPORTED;
+  }
+
+  SizeOfX = 0;
+  SizeOfY = 0;
+  if (GraphicsOutput != NULL) {
+SizeOfX = GraphicsOutput->Mode->Info->HorizontalResolution;
+SizeOfY = GraphicsOutput->Mode->Info->VerticalResolution;
+  } else if (UgaDraw != NULL) {
+Status = UgaDraw->GetMode (
+UgaDraw,
+,
+,
+,
+
+);
+if (EFI_ERROR (Status)) {
+  return EFI_UNSUPPORTED;
+}
+  } else {
+return EFI_UNSUPPORTED;
+  }
+
+  BlockWidth  = 

[edk2-devel] [PATCH 07/15] [platforms/devel-riscv]: RiscV/SiFive: Initial version of SiFive U500 platform package

[Mr. Gilbert Chen]

From: Gilbert Chen 

The initial version of SiFive U500 platform package.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Platform/RiscV/SiFive/U500Pkg/Readme.md|  30 ++
 Platform/RiscV/SiFive/U500Pkg/U500.dec |  40 ++
 Platform/RiscV/SiFive/U500Pkg/U500.dsc | 596 +
 Platform/RiscV/SiFive/U500Pkg/U500.fdf | 373 
 Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc |  58 +++
 Platform/RiscV/SiFive/U500Pkg/U500.uni | Bin 0 -> 1730 bytes
 Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni | Bin 0 -> 1396 bytes
 Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc |  85 
 8 files changed, 1182 insertions(+)
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Readme.md
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dec
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dsc
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.uni
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc

diff --git a/Platform/RiscV/SiFive/U500Pkg/Readme.md 
b/Platform/RiscV/SiFive/U500Pkg/Readme.md
new file mode 100644
index 000..3aaaf77
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Readme.md
@@ -0,0 +1,30 @@
+# Introduction
+
+## U500 Platform Package
+This is a sample RISC-V EDK2 platform package used agaist SiFive Freedom U500 
VC707 FPGA Dev Kit, please refer to "SiFive Freedom U500 VC707 FPGA Getting 
Started Guide" on https://www.sifive.com/documentation. This package is built 
with below common packages, 
+- **RiscVPlatformPkg**, edk2-platform/Platform/RiscV
+- **RiscVPkg**, edk2 master branch (Currently is in edk2-staging/RISC-V branch)
+
+This package provides librareis and modules which are SiFive U500 platform 
implementation-specific and incorporate with common RISC-V packages mentioned 
above.
+
+### OpneSbiPlatformLib
+In order to reduce the dependencies with RISC-V OpenSBI project 
(https://github.com/riscv/opensbi) and less burdens to EDK2 build process, the 
implementation of RISC-V EDK2 platform is leverage platform source code from 
OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib  is cloned from 
RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build 
environment.
+
+### PeiCoreInfoHobLib
+This is the library to create RISC-V core characteristics for building up 
RISC-V related SMBIOS records to support the unified boot loader and OS image. 
This library leverage the silicon libraries provided in Silicon/SiFive.
+
+### RiscVPlatformTimerLib
+This is U500 platform timer library which has the platform-specific timer 
implementation.
+
+### PlatformPei
+This is the platform-implementation specific library which is executed in 
early PEI phase for platform initialization.
+
+### TimerDxe
+This is U500 platform timer DXE driver whcih has the platform-specific timer 
implementation.
+
+## U500 Platform PCD settings
+
+| **PCD name** |**Usage**|
+||--|
+|PcdNumberofU5Cores| Number of U5 core enabled on U500 platform|
+|PcdE5MCSupported| Indicates whether or not the Monitor Core (E5) is supported 
on U500 platform|
diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.dec 
b/Platform/RiscV/SiFive/U500Pkg/U500.dec
new file mode 100644
index 000..9886328
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/U500.dec
@@ -0,0 +1,40 @@
+## @file  U500.dec
+# This Package provides SiFive U500 modules and libraries.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+#
+# This program and the accompanying materials are licensed and made available 
under
+# the terms and conditions of the BSD License which accompanies this 
distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  DEC_SPECIFICATION  = 0x00010005
+  PACKAGE_NAME   = U500
+  PACKAGE_UNI_FILE   = U500.uni
+  PACKAGE_GUID   = D11E9DB9-5940-4642-979D-2114342140D2
+  PACKAGE_VERSION= 1.0
+
+[Includes]
+  Include
+
+[LibraryClasses]
+
+
+[Guids]
+  gUefiRiscVPlatformU500PkgTokenSpaceGuid  = {0xDFD87009, 0x27A1, 0x41DD, { 
0x84, 0xB1, 0x35, 0xB4, 0xB9, 0x0D, 0x17, 0x63 }}
+
+[PcdsFixedAtBuild]
+  
gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores|0x8|UINT32|0x1000
+  
gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported|TRUE|BOOLEAN|0x1001
+
+[PcdsPatchableInModule]
+  
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  U500PkgExtra.uni
diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.dsc 
b/Platform/RiscV/SiFive/U500Pkg/U500.dsc
new file 

[edk2-devel] [PATCH 04/15] [platforms/devel-riscv]: RiscV/Include: Initial version of header files in RISC-V platform package

[Mr. Gilbert Chen]

From: Gilbert Chen 

FirmwareContextProcessorSpecificLib.h
- The difinitions of Firmware Context EDK2 implementaion based on RISC-V 
OpenSBI.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../Library/FirmwareContextProcessorSpecificLib.h  | 47 ++
 1 file changed, 47 insertions(+)
 create mode 100644 
Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h

diff --git 
a/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h 
b/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h
new file mode 100644
index 000..3bfd39f
--- /dev/null
+++ b/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h
@@ -0,0 +1,47 @@
+
+/** @file
+  Firmware Context Processor-specific common library
+   
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.  
+
+  This program and the accompanying materials are licensed and made available 
under 
+  the terms and conditions of the BSD License that accompanies this 
distribution.  
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.  

+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
 
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED. 
+
+**/
+#ifndef __FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H__
+#define __FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H__
+
+#include 
+
+/**
+  Build up common firmware context processor-specific information
+
+  @param  FirmwareContextHartSpecific  Pointer to 
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
+  @param  ParentProcessorGuid  Pointer to GUID of Processor which 
contains this core 
+  @param  ParentProcessorUid   Unique ID of pysical processor which 
owns this core.   
+  @param  CoreGuid Pointer to GUID of core
+  @param  HartId   Hart ID of this core.
+  @param  IsBootHart   This is boot hart or not 
+  @param  ProcessorSpecDataHob Pointer to 
RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+
+  @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CommonFirmwareContextHartSpecificInfo (
+  EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
+  EFI_GUID  *ParentProcessorGuid,
+  UINTN ParentProcessorUid,
+  EFI_GUID  *CoreGuid,
+  UINTN HartId,
+  BOOLEAN   IsBootHart,
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecDataHob
+  );
+
+#endif
-- 
2.7.4


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[edk2-devel] [PATCH 06/15] [platforms/devel-riscv]: RiscV/Universal: Initial version of common RISC-V SEC module

[Mr. Gilbert Chen]

Common RISC-V SEC module for RISC-V platforms.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s | 439 
 Platform/RiscV/Universal/Sec/SecMain.c  | 529 
 Platform/RiscV/Universal/Sec/SecMain.h  |  56 +++
 Platform/RiscV/Universal/Sec/SecMain.inf|  81 
 4 files changed, 1105 insertions(+)
 create mode 100644 Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s
 create mode 100644 Platform/RiscV/Universal/Sec/SecMain.c
 create mode 100644 Platform/RiscV/Universal/Sec/SecMain.h
 create mode 100644 Platform/RiscV/Universal/Sec/SecMain.inf

diff --git a/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s 
b/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s
new file mode 100644
index 000..a5ca481
--- /dev/null
+++ b/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s
@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2019 , Hewlett Packard Enterprise Development LP. All rights 
reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+.text
+.align 3
+.global ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+  /*
+   * Jump to warm-boot if this is not the selected core booting,
+   */
+  csrr a6, CSR_MHARTID
+  li a5, FixedPcdGet32 (PcdBootHartId)
+  bne a6, a5, _wait_for_boot_hart
+
+  // light LED on
+  li a5, 0x54002000
+  li a4, 0xff
+  sw a4, 0x08(a5)
+  li a4, 0x11
+  sw a4, 0x0c(a5)
+
+  lira, 0
+  call_reset_regs
+
+  /* Preload HART details
+   * s7 -> HART Count
+   * s8 -> HART Stack Size
+   */
+  li s7, FixedPcdGet32 (PcdHartCount)
+  li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
+
+  /* Setup scratch space for all the HARTs*/
+  li  tp, FixedPcdGet32 (PcdScratchRamBase)
+  mula5, s7, s8
+  addtp, tp, a5
+  /* Keep a copy of tp */
+  addt3, tp, zero
+  /* Counter */
+  lit2, 1
+  /* hartid 0 is mandated by ISA */
+  lit1, 0
+_scratch_init:
+  addtp, t3, zero
+  mula5, s8, t1
+  subtp, tp, a5
+  lia5, SBI_SCRATCH_SIZE
+  subtp, tp, a5
+
+  /* Initialize scratch space */
+  li  a4, FixedPcdGet32 (PcdFwStartAddress)
+  li  a5, FixedPcdGet32 (PcdFwEndAddress)
+  suba5, a5, a4
+  sda4, SBI_SCRATCH_FW_START_OFFSET(tp)
+  sda5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
+  /* Note: fw_next_arg1() uses a0, a1, and ra */
+  callfw_next_arg1
+  sda0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp)
+  /* Note: fw_next_addr() uses a0, a1, and ra */
+  callfw_next_addr
+  sda0, SBI_SCRATCH_NEXT_ADDR_OFFSET(tp)
+  lia4, PRV_S
+  sda4, SBI_SCRATCH_NEXT_MODE_OFFSET(tp)
+  laa4, _start_warm
+  sda4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp)
+  laa4, platform
+  sda4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp)
+  laa4, _hartid_to_scratch
+  sda4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp)
+  sdzero, SBI_SCRATCH_TMP0_OFFSET(tp)
+#ifdef FW_OPTIONS
+  lia4, FW_OPTIONS
+  sda4, SBI_SCRATCH_OPTIONS_OFFSET(tp)
+#else
+  sdzero, SBI_SCRATCH_OPTIONS_OFFSET(tp)
+#endif
+  addt1, t1, t2
+  bltt1, s7, _scratch_init
+
+  /* Fill-out temporary memory with 55aa*/
+  lia4, FixedPcdGet32 (PcdTemporaryRamBase)
+  lia5, FixedPcdGet32 (PcdTemporaryRamSize)
+  add a5, a4, a5
+1:
+  li a3, 0x5AA55AA55AA55AA5
+  sda3, (a4)
+  adda4, a4, __SIZEOF_POINTER__
+  blta4, a5, 1b
+
+  /* Update boot hart flag */
+  laa4, _boot_hart_done
+  lia5, 1
+  sda5, (a4)
+
+  /* Wait for boot hart */
+_wait_for_boot_hart:
+  laa4, _boot_hart_done
+  lda5, (a4)
+  /* Reduce the bus traffic so that boot hart may proceed faster */
+  nop
+  nop
+  nop
+  beqza5, _wait_for_boot_hart
+
+_start_warm:
+  lira, 0
+  call_reset_regs
+
+  /* Disable and clear all interrupts */
+  csrwCSR_MIE, zero
+  csrwCSR_MIP, zero
+
+  li s7, FixedPcdGet32 (PcdHartCount)
+  li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
+
+  /* HART ID should be within expected limit */
+  csrrs6, CSR_MHARTID
+  bges6, s7, _start_hang
+
+  /* find the scratch space for this hart */
+  litp, FixedPcdGet32 (PcdScratchRamBase)
+  mula5, s7, s8
+  addtp, tp, a5
+  mula5, s8, s6
+  subtp, tp, a5
+  lia5, SBI_SCRATCH_SIZE
+  subtp, tp, a5
+
+  /* update the mscratch */
+  csrwCSR_MSCRATCH, tp
+
+  /*make room for Hart specific Firmware Context*/
+  lia5, FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE
+  subtp, tp, a5
+
+  /* Setup stack */
+  add sp, tp, zero
+
+  /* Setup stack for the Hart executing EFI to top of temporary ram*/
+  csrr a6, CSR_MHARTID
+  li a5, FixedPcdGet32 (PcdBootHartId)
+  bne a6, a5, 1f
+
+  li a4, FixedPcdGet32(PcdTemporaryRamBase)
+  li a5, FixedPcdGet32(PcdTemporaryRamSize)
+  addsp, a4, a5
+  1:
+
+  /* Setup trap handler */
+  laa4, _trap_handler
+  csrwCSR_MTVEC, a4
+  /* Make sure that mtvec is updated */
+  1:
+  csrra5, CSR_MTVEC
+  bnea4, a5, 1b
+
+  /* Call library constructors before jup to SEC core */
+  call ProcessLibraryConstructorList
+
+  /* jump to SEC 

[edk2-devel] [PATCH 08/15] [platforms/devel-riscv]: U500Pkg/Include: Header files of SiFive U500 platform

[Mr. Gilbert Chen]

The initial header file commit for SiFive U5-MC Coreplex and U500 Core Local 
interrupt definitions.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h| 57 ++
 Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h  | 24 +
 2 files changed, 81 insertions(+)
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h

diff --git a/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h 
b/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h
new file mode 100644
index 000..c0323a5
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h
@@ -0,0 +1,57 @@
+/** @file
+  SiFive U54 Coreplex library definitions.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License that accompanies this 
distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __SIFIVE_U5MC_COREPLEX_H__
+#define __SIFIVE_U5MC_COREPLEX_H__
+
+#include 
+
+#include 
+#include 
+
+#define SIFIVE_U5MC_COREPLEX_MC_HART_ID 0
+
+/**
+  Build up U5MC coreplex processor core-specific information.
+
+  @param  UniqueId  U5MC unique ID.
+
+  @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCCoreplexProcessorSpecificDataHob (
+  IN UINTN UniqueId
+  );
+
+/**
+  Function to build processor related SMBIOS information. RISC-V SMBIOS DXE 
driver collect
+  this information and build SMBIOS Type4 and Type7 record.
+
+  @param  ProcessorUidUnique ID of pysical processor which owns this 
core.
+  @param  SmbiosDataHobPtrPointer to receive 
RISC_V_PROCESSOR_SMBIOS_DATA_HOB. The pointers
+  maintained in this structure is only valid 
before memory is discovered.
+  Access to those pointers after memory is 
installed will cause unexpected issues.
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCProcessorSmbiosDataHob (
+  IN UINTN ProcessorUid,
+  OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosDataHobPtr
+  );
+#endif
diff --git a/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h 
b/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h
new file mode 100644
index 000..426bf43
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h
@@ -0,0 +1,24 @@
+/** @file
+  RISC-V Timer Architectural definition for U500 platform.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution. The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#ifndef _U500_H_
+#define _U500_H_
+
+#define CLINT_REG_MTIME 0x0200BFF8
+#define CLINT_REG_MTIMECMP0 0x02004000
+#define CLINT_REG_MTIMECMP1 0x02004008
+#define CLINT_REG_MTIMECMP2 0x02004010
+#define CLINT_REG_MTIMECMP3 0x02004018
+#define CLINT_REG_MTIMECMP4 0x02004020
+
+#endif
\ No newline at end of file
--
2.7.4


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[edk2-devel] [PATCH 13/15] [platforms/devel-riscv]: U500Pkg/TimerDxe: Platform Timer DXE driver

[Mr. Gilbert Chen]

Timer DXE driver for U500 platform based U500 platform implementation specifc 
timer registers.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c  | 317 +
 .../SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h  | 179 
 .../U500Pkg/Universal/Dxe/TimerDxe/Timer.uni   | Bin 0 -> 1678 bytes
 .../U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf|  54 
 .../U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni  | Bin 0 -> 1374 bytes
 5 files changed, 550 insertions(+)
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.uni
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni

diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
new file mode 100644
index 000..8f8eeb6
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
@@ -0,0 +1,317 @@
+/** @file
+  RISC-V Timer Architectural Protocol for U500 platform.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution. The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include "Timer.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CLINT_REG_MTIME 0x0200BFF8
+#define CLINT_REG_MTIMECMP0 0x02004000
+#define CLINT_REG_MTIMECMP1 0x02004008
+#define CLINT_REG_MTIMECMP2 0x02004010
+#define CLINT_REG_MTIMECMP3 0x02004018
+#define CLINT_REG_MTIMECMP4 0x02004020
+
+static volatile void * const p_mtime = (void *)CLINT_REG_MTIME;
+#define MTIME  (*p_mtime)
+#define MTIMECMP(i)(p_mtimecmp[i])
+
+//
+// The handle onto which the Timer Architectural Protocol will be installed
+//
+EFI_HANDLEmTimerHandle = NULL;
+
+//
+// The Timer Architectural Protocol that this driver produces
+//
+EFI_TIMER_ARCH_PROTOCOL   mTimer = {
+  TimerDriverRegisterHandler,
+  TimerDriverSetTimerPeriod,
+  TimerDriverGetTimerPeriod,
+  TimerDriverGenerateSoftInterrupt
+};
+
+//
+// Pointer to the CPU Architectural Protocol instance
+//
+EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+//
+// The notification function to call on every timer interrupt.
+// A bug in the compiler prevents us from initializing this here.
+//
+EFI_TIMER_NOTIFY mTimerNotifyFunction;
+
+//
+// The current period of the timer interrupt
+//
+volatile UINT64 mTimerPeriod = 0;
+
+
+/**
+  8254 Timer #0 Interrupt Handler.
+
+  @param InterruptTypeThe type of interrupt that occured
+  @param SystemContextA pointer to the system context when the interrupt 
occured
+**/
+
+VOID
+EFIAPI
+TimerInterruptHandler (
+  IN EFI_EXCEPTION_TYPE   InterruptType,
+  IN EFI_SYSTEM_CONTEXT   SystemContext
+  )
+{
+  EFI_TPL OriginalTPL;
+  UINT64 RiscvTimer;
+
+  csr_clear(CSR_SIE, MIP_STIP); // enable timer int
+  OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+  if (mTimerPeriod == 0) {
+gBS->RestoreTPL (OriginalTPL);
+mCpu->DisableInterrupt(mCpu);
+return;
+  }
+  if (mTimerNotifyFunction != NULL) {
+mTimerNotifyFunction (mTimerPeriod);
+  }
+  gBS->RestoreTPL (OriginalTPL);
+
+
+  RiscvTimer = readq_relaxed(p_mtime);
+  sbi_set_timer(RiscvTimer += mTimerPeriod);
+  csr_set(CSR_SIE, MIP_STIP); // enable timer int
+
+}
+
+/**
+
+  This function registers the handler NotifyFunction so it is called every time
+  the timer interrupt fires.  It also passes the amount of time since the last
+  handler call to the NotifyFunction.  If NotifyFunction is NULL, then the
+  handler is unregistered.  If the handler is registered, then EFI_SUCCESS is
+  returned.  If the CPU does not support registering a timer interrupt handler,
+  then EFI_UNSUPPORTED is returned.  If an attempt is made to register a 
handler
+  when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+  If an attempt is made to unregister a handler when a handler is not 
registered,
+  then EFI_INVALID_PARAMETER is returned.  If an error occurs attempting to
+  register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+  is returned.
+
+  @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+  @param NotifyFunction   The function to call when a timer interrupt fires.  
This
+  function executes at TPL_HIGH_LEVEL.  The 

[edk2-devel] [PATCH 10/15] [platforms/devel-riscv]: U500Pkg/Library: Library instances of U500 platform library.

[Mr. Gilbert Chen]

OpneSbiPlatformLib
- In order to reduce the dependencies with RISC-V OpenSBI project 
(https://github.com/riscv/opensbi) and less burdens to EDK2 build process, the 
implementation of RISC-V EDK2 platform is leverage platform source code from 
OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib is cloned from 
RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build 
environment.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../OpenSbiPlatformLib/OpenSbiPlatformLib.inf  |  53 +
 .../U500Pkg/Library/OpenSbiPlatformLib/platform.c  | 214 +
 2 files changed, 267 insertions(+)
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c

diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
 
b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
new file mode 100644
index 000..1823e48
--- /dev/null
+++ 
b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
@@ -0,0 +1,53 @@
+## @file
+#  RISC-V OpenSbi Platform Library
+#  This is the the required library which provides platform
+#  level opensbi functions follow RISC-V opensbi implementation.
+#
+#  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution. The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = OpenSbiPlatformLib
+  FILE_GUID  = 9424ED54-EBDA-4FB5-8FF6-8291B07BB151
+  MODULE_TYPE= SEC
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = OpenSbiPlatformLib
+
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+#  VALID_ARCHITECTURES   = RISCV64 EBC
+#
+
+[Sources]
+  platform.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  RiscVPkg/RiscVPkg.dec
+  Platform/RiscV/RiscVPlatformPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  BaseMemoryLib
+  PcdLib
+  DebugAgentLib
+  RiscVCpuLib
+  PrintLib
+
+[FixedPcd]
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c 
b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
new file mode 100644
index 000..887a279
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
@@ -0,0 +1,214 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Atish Patra 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+#define U500_HART_COUNTFixedPcdGet32(PcdHartCount)
+#define U500_HART_STACK_SIZEFixedPcdGet32(PcdOpenSbiStackSize)
+#define U500_BOOT_HART_ID   FixedPcdGet32(PcdBootHartId)
+
+#define U500_SYS_CLK1
+
+#define U500_CLINT_ADDR0x200
+
+#define U500_PLIC_ADDR0xc00
+#define U500_PLIC_NUM_SOURCES0x35
+#define U500_PLIC_NUM_PRIORITIES7
+
+#define U500_UART_ADDR0x5400
+
+#define U500_UART_BAUDRATE115200
+
+/**
+ * The U500 SoC has 8 HARTs but HART ID 0 doesn't have S mode.
+ * HARTs 1 is selected as boot HART
+ */
+#ifndef U500_ENABLED_HART_MASK
+#define U500_ENABLED_HART_MASK(1 << U500_BOOT_HART_ID)
+#endif
+
+#define U500_HARTID_DISABLED~(U500_ENABLED_HART_MASK)
+
+/* PRCI clock related macros */
+//TODO: Do we need a separate driver for this ?
+#define U500_PRCI_BASE_ADDR0x1000
+#define U500_PRCI_CLKMUXSTATUSREG0x002C
+#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL(0x1 << 1)
+
+static void U500_modify_dt(void *fdt)
+{
+u32 i, size;
+int chosen_offset, err;
+int cpu_offset;
+char cpu_node[32] = "";
+const char *mmu_type;
+
+for (i = 0; i < U500_HART_COUNT; i++) {
+sbi_sprintf(cpu_node, "/cpus/cpu@%d", i);
+cpu_offset = fdt_path_offset(fdt, cpu_node);
+mmu_type = fdt_getprop(fdt, cpu_offset, "mmu-type", NULL);
+if (mmu_type && (!strcmp(mmu_type, "riscv,sv39") ||
+!strcmp(mmu_type,"riscv,sv48")))
+continue;
+else
+fdt_setprop_string(fdt, cpu_offset, "status", "masked");
+memset(cpu_node, 0, sizeof(cpu_node));
+}
+size = 

[edk2-devel] [PATCH 05/15] [platforms/devel-riscv]: RiscV/Library: Initial version of libraries introduced in RISC-V platform package

[Mr. Gilbert Chen]

FirmwareContextProcessorSpecificLib
- Common library to consume EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC and build 
up processor specific data HOB.

RealTimClockLibNull
- NULL instance of Real Time Clock library.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../FirmwareContextProcessorSpecificLib.c  |  88 +
 .../FirmwareContextProcessorSpecificLib.inf|  39 
 .../RealTimeClockLibNull/RealTimeClockLibNull.c| 212 +
 .../RealTimeClockLibNull/RealTimeClockLibNull.inf  |  36 
 4 files changed, 375 insertions(+)
 create mode 100644 
Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
 create mode 100644 
Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
 create mode 100644 
Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
 create mode 100644 
Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf

diff --git 
a/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
 
b/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
new file mode 100644
index 000..0ce2570
--- /dev/null
+++ 
b/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
@@ -0,0 +1,88 @@
+/**@file
+  Common library to build upfirmware context processor-specific information
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Build up common firmware context processor-specific information
+
+  @param  FirmwareContextHartSpecific  Pointer to 
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
+  @param  ParentProcessorGuid  Pointer to GUID of Processor which 
contains this core
+  @param  ParentProcessorUid   Unique ID of pysical processor which 
owns this core.
+  @param  CoreGuid Pointer to GUID of core
+  @param  HartId   Hart ID of this core.
+  @param  IsBootHart   This is boot hart or not
+  @param  ProcessorSpecDataHob Pointer to 
RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+
+  @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CommonFirmwareContextHartSpecificInfo (
+  EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
+  EFI_GUID  *ParentProcessorGuid,
+  UINTN ParentProcessorUid,
+  EFI_GUID  *CoreGuid,
+  UINTN HartId,
+  BOOLEAN   IsBootHart,
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecDataHob
+  )
+{
+  //
+  // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+  //
+  CopyGuid (>ParentPrcessorGuid, ParentProcessorGuid);
+  ProcessorSpecDataHob->ParentProcessorUid = ParentProcessorUid;
+  CopyGuid (>CoreGuid, CoreGuid);
+  ProcessorSpecDataHob->Context = NULL;
+  ProcessorSpecDataHob->ProcessorSpecificData.Revision = 
SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION;
+  ProcessorSpecDataHob->ProcessorSpecificData.Length   = sizeof 
(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+  ProcessorSpecDataHob->ProcessorSpecificData.HartId.Value64_L = 
(UINT64)HartId;
+  ProcessorSpecDataHob->ProcessorSpecificData.HartId.Value64_H = 0;
+  ProcessorSpecDataHob->ProcessorSpecificData.BootHartId   = 
(UINT8)IsBootHart;
+  ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported = 
FirmwareContextHartSpecific->IsaExtensionSupported;
+  ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported   = 
SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED;
+  if ((ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported & 
RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED) != 0) {
+ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported |= 
SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED;
+  }
+  if ((ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported & 
RISC_V_ISA_USER_MODE_IMPLEMENTED) != 0) {
+ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported |= 
SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED;
+  }
+  ProcessorSpecDataHob->ProcessorSpecificData.MachineVendorId.Value64_L = 
FirmwareContextHartSpecific->MachineVendorId.Value64_L;
+  ProcessorSpecDataHob->ProcessorSpecificData.MachineVendorId.Value64_H = 
FirmwareContextHartSpecific->MachineVendorId.Value64_H;
+  

[edk2-devel] [PATCH 12/15] [platforms/devel-riscv]: U500Pkg/RamFvbServiceruntimeDxe: FVB driver for EFI variable.

[Mr. Gilbert Chen]

From: Gilbert Chen 

Firmware Volume Block driver instance for ram based EFI variable on U500 
platform.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c |  133 +++
 .../FvbServicesRuntimeDxe.inf  |   88 ++
 .../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c  | 1129 
 .../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h  |  193 
 .../RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c   |  156 +++
 .../Dxe/RamFvbServicesRuntimeDxe/RamFlash.c|  151 +++
 .../Dxe/RamFvbServicesRuntimeDxe/RamFlash.h|   92 ++
 .../Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c |   26 +
 8 files changed, 1968 insertions(+)
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c

diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
new file mode 100644
index 000..bfed741
--- /dev/null
+++ 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
@@ -0,0 +1,133 @@
+/**@file
+ 
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2006, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Module Name:
+
+FvbInfo.c
+
+  Abstract:
+
+Defines data structure that is the volume header found.These data is intent
+to decouple FVB driver with FV header.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The protocols, PPI and GUID defintions for this module
+//
+#include 
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+
+typedef struct {
+  UINT64  FvLength;
+  EFI_FIRMWARE_VOLUME_HEADER  FvbInfo;
+  //
+  // EFI_FV_BLOCK_MAP_ENTRYExtraBlockMap[n];//n=0
+  //
+  EFI_FV_BLOCK_MAP_ENTRY  End[1];
+} EFI_FVB_MEDIA_INFO;
+
+EFI_FVB_MEDIA_INFO  mPlatformFvbMediaInfo[] = {
+  //
+  // Systen NvStorage FVB
+  //
+  {
+FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+{
+  {
+0,
+  },  // ZeroVector[16]
+  EFI_SYSTEM_NV_DATA_FV_GUID,
+  FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+  FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+  FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+  EFI_FVH_SIGNATURE,
+  EFI_FVB2_MEMORY_MAPPED |
+EFI_FVB2_READ_ENABLED_CAP |
+EFI_FVB2_READ_STATUS |
+EFI_FVB2_WRITE_ENABLED_CAP |
+EFI_FVB2_WRITE_STATUS |
+EFI_FVB2_ERASE_POLARITY |
+EFI_FVB2_ALIGNMENT_16,
+  sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
+  0,  // CheckSum
+  0,  // ExtHeaderOffset
+  {
+0,
+  },  // Reserved[1]
+  2,  // Revision
+  {
+{
+  (FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+   FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+   FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)) /
+  FixedPcdGet32 (PcdVariableFdBlockSize),
+  FixedPcdGet32 (PcdVariableFdBlockSize),
+}
+  } // BlockMap[1]
+},
+{
+  {
+0,
+0
+  }
+}  // End[1]
+  }
+};
+
+EFI_STATUS
+GetFvbInfo (
+  IN  UINT64FvLength,
+  OUT EFI_FIRMWARE_VOLUME_HEADER**FvbInfo
+  )
+{
+  STATIC BOOLEAN Checksummed = FALSE;
+  UINTN Index;
+
+  if (!Checksummed) {
+for (Index = 0;
+ Index < sizeof (mPlatformFvbMediaInfo) / sizeof (EFI_FVB_MEDIA_INFO);
+ Index += 1) {
+  UINT16 Checksum;
+  mPlatformFvbMediaInfo[Index].FvbInfo.Checksum = 0;
+  

[edk2-devel] [PATCH 14/15] [platforms/devel-riscv]: U500Pkg/PlatformPei: Platform initialization PEIM

[Mr. Gilbert Chen]

From: Gilbert Chen 

This is the platform-implementation specific library which is executed in early 
PEI phase for platform initialization.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c  |  55 
 .../U500Pkg/Universal/Pei/PlatformPei/MemDetect.c  |  80 ++
 .../U500Pkg/Universal/Pei/PlatformPei/Platform.c   | 319 +
 .../U500Pkg/Universal/Pei/PlatformPei/Platform.h   |  97 +++
 .../Universal/Pei/PlatformPei/PlatformPei.inf  |  82 ++
 5 files changed, 633 insertions(+)
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.inf

diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
new file mode 100644
index 000..04ac7ac
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
@@ -0,0 +1,55 @@
+/** @file
+  Build FV related hobs for platform.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PiPei.h"
+#include "Platform.h"
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
+  and DXE know about them.
+
+  @retval EFI_SUCCESS   Platform PEI FVs were initialized successfully.
+
+**/
+EFI_STATUS
+PeiFvInitialization (
+  VOID
+  )
+{
+  DEBUG ((EFI_D_INFO, "Platform PEI Firmware Volume Initialization\n"));
+  //
+  // Let DXE know about the DXE FV
+  //
+  BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize));
+  DEBUG ((EFI_D_INFO, "Platform builds DXE FV at %x, size %x.\n", PcdGet32 
(PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize)));
+
+  //
+  // Let PEI know about the DXE FV so it can find the DXE Core
+  //
+  PeiServicesInstallFvInfoPpi (
+NULL,
+(VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase),
+PcdGet32 (PcdRiscVDxeFvSize),
+NULL,
+NULL
+);
+
+  return EFI_SUCCESS;
+}
diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
new file mode 100644
index 000..3c047f1
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
@@ -0,0 +1,80 @@
+/**@file
+  Memory Detection for Virtual Machines.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  MemDetect.c
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "Platform.h"
+
+
+/**
+  Publish PEI core memory
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+PublishPeiMemory (
+  VOID
+  )
+{
+  EFI_STATUS  Status;
+  EFI_PHYSICAL_ADDRESSMemoryBase;
+  UINT64  MemorySize;
+
+  MemoryBase = 0x8000UL + 0x100UL;
+  MemorySize = 0x4000UL - 0x100UL; //1GB - 16MB 
+
+  DEBUG((EFI_D_INFO, "%a: MemoryBase:0x%x MemorySize:%d\n", __FUNCTION__, 
MemoryBase, MemorySize));
+
+  //
+  // Publish this memory to the PEI Core
+  //
+  Status = PublishSystemMemory(MemoryBase, MemorySize);
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
+/**
+  Publish system RAM and reserve memory regions
+
+**/
+VOID
+InitializeRamRegions (
+  VOID
+  )
+{
+  AddMemoryRangeHob(0x8100UL, 0x8100UL + 0x3F00UL);
+
+}
diff --git 

[edk2-devel] [PATCH 04/15] [platforms/devel-riscv]: RiscV/Include: Initial version of header files in RISC-V platform package

[Chen, Gilbert]

FirmwareContextProcessorSpecificLib.h
- The difinitions of Firmware Context EDK2 implementaion based on RISC-V 
OpenSBI.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../Library/FirmwareContextProcessorSpecificLib.h  | 47 ++
 1 file changed, 47 insertions(+)
 create mode 100644 
Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h

diff --git 
a/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h 
b/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h
new file mode 100644
index 000..3bfd39f
--- /dev/null
+++ b/Platform/RiscV/Include/Library/FirmwareContextProcessorSpecificLib.h
@@ -0,0 +1,47 @@
+
+/** @file
+  Firmware Context Processor-specific common library
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License that accompanies this 
distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H__
+#define __FIRMWARE_CONTEXT_PROCESSOR_SPECIFIC_LIB_H__
+
+#include 
+
+/**
+  Build up common firmware context processor-specific information
+
+  @param  FirmwareContextHartSpecific  Pointer to 
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
+  @param  ParentProcessorGuid  Pointer to GUID of Processor which 
contains this core
+  @param  ParentProcessorUid   Unique ID of pysical processor which 
owns this core.
+  @param  CoreGuid Pointer to GUID of core
+  @param  HartId   Hart ID of this core.
+  @param  IsBootHart   This is boot hart or not
+  @param  ProcessorSpecDataHob Pointer to 
RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+
+  @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CommonFirmwareContextHartSpecificInfo (
+  EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
+  EFI_GUID  *ParentProcessorGuid,
+  UINTN ParentProcessorUid,
+  EFI_GUID  *CoreGuid,
+  UINTN HartId,
+  BOOLEAN   IsBootHart,
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecDataHob
+  );
+
+#endif
--
2.7.4


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Re: [edk2-devel] [POC Seabios PATCH] seabios: use isolated SMM address space for relocation

[Boris Ostrovsky]

On 8/26/19 9:57 AM, Igor Mammedov wrote:
>
>> I most likely don't understand how this is supposed to work but aren't
>> we here successfully reading SMRAM from non-SMM context, something we
>> are not supposed to be able to do?
> We are aren't reading SMRAM at 0x3 base directly,
> "RAM" marked log lines are non-SMM context reads using as base
>   BUILD_SMM_INIT_ADDR   0x3
> and as you see, it isn't showing anything from SMRAM
>
> For mgmt/demo purposes SMRAM (which is at 0x3 in SMM address space)
> is also aliased at
>   BUILD_SMM_ADDR0xa
> into non-SMM address space to allow us to initialize SMM entry point
> (log entries are marked as "SMRAM").



OK, I then misunderstood the purpose of this demo. I thought you were
not supposed to be able to read it from either location in non-SMM mode.

Thanks for the explanation.

-boris

>
> Aliased SMRAM also allows us to check that relocation worked
> (i.e. smm_base was relocated from default "handle_smi cmd=0 smbase=0x0003"
> to a new one "smm_relocate: SMRAM  cpu.i64.smm_base  a").
>
>
> It's similar to what we do with TSEG where QEMU steals RAM from
> normal address space and puts MMIO region 'tseg_blackhole' over it
> so non-SMM context reads 0xFF from TSEG window, while SMM context
> accesses RAM hidden below tseg_blackhole.
>
> These patches show that we can have normal usable RAM at 0x3
> which doesn't overlap with SMRAM at the same address and each can
> be made accessible only from its own mode (no-SMM and SMM).
> Preventing non-SMM mode from injecting attack on SMRAM via CPU
> that hasn't been initialized yet once firmware locked down SMRAM.
>
>
>>
>> -boris
>>


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[edk2-devel] [PATCH 13/15] [platforms/devel-riscv]: U500Pkg/TimerDxe: Platform Timer DXE driver

[Chen, Gilbert]

Timer DXE driver for U500 platform based U500 platform implementation specifc 
timer registers.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c  | 317 +
 .../SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h  | 179 
 .../U500Pkg/Universal/Dxe/TimerDxe/Timer.uni   | Bin 0 -> 1678 bytes
 .../U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf|  54 
 .../U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni  | Bin 0 -> 1374 bytes
 5 files changed, 550 insertions(+)
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.uni
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerDxe.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/TimerExtra.uni

diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
new file mode 100644
index 000..8f8eeb6
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/TimerDxe/Timer.c
@@ -0,0 +1,317 @@
+/** @file
+  RISC-V Timer Architectural Protocol for U500 platform.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution. The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+
+#include "Timer.h"
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define CLINT_REG_MTIME 0x0200BFF8
+#define CLINT_REG_MTIMECMP0 0x02004000
+#define CLINT_REG_MTIMECMP1 0x02004008
+#define CLINT_REG_MTIMECMP2 0x02004010
+#define CLINT_REG_MTIMECMP3 0x02004018
+#define CLINT_REG_MTIMECMP4 0x02004020
+
+static volatile void * const p_mtime = (void *)CLINT_REG_MTIME;
+#define MTIME  (*p_mtime)
+#define MTIMECMP(i)(p_mtimecmp[i])
+
+//
+// The handle onto which the Timer Architectural Protocol will be installed
+//
+EFI_HANDLEmTimerHandle = NULL;
+
+//
+// The Timer Architectural Protocol that this driver produces
+//
+EFI_TIMER_ARCH_PROTOCOL   mTimer = {
+  TimerDriverRegisterHandler,
+  TimerDriverSetTimerPeriod,
+  TimerDriverGetTimerPeriod,
+  TimerDriverGenerateSoftInterrupt
+};
+
+//
+// Pointer to the CPU Architectural Protocol instance
+//
+EFI_CPU_ARCH_PROTOCOL *mCpu;
+
+//
+// The notification function to call on every timer interrupt.
+// A bug in the compiler prevents us from initializing this here.
+//
+EFI_TIMER_NOTIFY mTimerNotifyFunction;
+
+//
+// The current period of the timer interrupt
+//
+volatile UINT64 mTimerPeriod = 0;
+
+
+/**
+  8254 Timer #0 Interrupt Handler.
+
+  @param InterruptTypeThe type of interrupt that occured
+  @param SystemContextA pointer to the system context when the interrupt 
occured
+**/
+
+VOID
+EFIAPI
+TimerInterruptHandler (
+  IN EFI_EXCEPTION_TYPE   InterruptType,
+  IN EFI_SYSTEM_CONTEXT   SystemContext
+  )
+{
+  EFI_TPL OriginalTPL;
+  UINT64 RiscvTimer;
+
+  csr_clear(CSR_SIE, MIP_STIP); // enable timer int
+  OriginalTPL = gBS->RaiseTPL (TPL_HIGH_LEVEL);
+  if (mTimerPeriod == 0) {
+gBS->RestoreTPL (OriginalTPL);
+mCpu->DisableInterrupt(mCpu);
+return;
+  }
+  if (mTimerNotifyFunction != NULL) {
+mTimerNotifyFunction (mTimerPeriod);
+  }
+  gBS->RestoreTPL (OriginalTPL);
+
+
+  RiscvTimer = readq_relaxed(p_mtime);
+  sbi_set_timer(RiscvTimer += mTimerPeriod);
+  csr_set(CSR_SIE, MIP_STIP); // enable timer int
+
+}
+
+/**
+
+  This function registers the handler NotifyFunction so it is called every time
+  the timer interrupt fires.  It also passes the amount of time since the last
+  handler call to the NotifyFunction.  If NotifyFunction is NULL, then the
+  handler is unregistered.  If the handler is registered, then EFI_SUCCESS is
+  returned.  If the CPU does not support registering a timer interrupt handler,
+  then EFI_UNSUPPORTED is returned.  If an attempt is made to register a 
handler
+  when a handler is already registered, then EFI_ALREADY_STARTED is returned.
+  If an attempt is made to unregister a handler when a handler is not 
registered,
+  then EFI_INVALID_PARAMETER is returned.  If an error occurs attempting to
+  register the NotifyFunction with the timer interrupt, then EFI_DEVICE_ERROR
+  is returned.
+
+  @param This The EFI_TIMER_ARCH_PROTOCOL instance.
+  @param NotifyFunction   The function to call when a timer interrupt fires.  
This
+  function executes at TPL_HIGH_LEVEL.  The 

[edk2-devel] [PATCH 09/15] [platforms/devel-riscv]: U500Pkg/Library: Initial version of PlatformBootManagerLib

[Chen, Gilbert]

SiFive RISC-V U500 Platform Boot Manager library.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../Library/PlatformBootManagerLib/MemoryTest.c| 1110 
 .../PlatformBootManagerLib/PlatformBootManager.c   |  269 +
 .../PlatformBootManagerLib/PlatformBootManager.h   |  141 +++
 .../PlatformBootManagerLib.inf |   72 ++
 .../Library/PlatformBootManagerLib/PlatformData.c  |   54 +
 .../Library/PlatformBootManagerLib/Strings.uni |  Bin 0 -> 3922 bytes
 6 files changed, 1646 insertions(+)
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManager.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManager.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/PlatformData.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/Strings.uni

diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c 
b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
new file mode 100644
index 000..841e3d9
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Library/PlatformBootManagerLib/MemoryTest.c
@@ -0,0 +1,1110 @@
+/** @file
+  Perform the RISC-V platform memory test
+
+Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+Copyright (c) 2004 - 2015, Intel Corporation. All rights reserved.
+
+This program and the accompanying materials
+are licensed and made available under the terms and conditions of the BSD 
License
+which accompanies this distribution.  The full text of the license may be 
found at
+http://opensource.org/licenses/bsd-license.php
+
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PlatformBootManager.h"
+
+EFI_HII_HANDLE gStringPackHandle = NULL;
+EFI_GUID   mPlatformBootManagerStringPackGuid = {
+  0x154dd51, 0x9079, 0x4a10, { 0x89, 0x5c, 0x9c, 0x7, 0x72, 0x81, 0x57, 0x88 }
+  };
+// extern UINT8  BdsDxeStrings[];
+
+//
+// BDS Platform Functions
+//
+/**
+
+  Show progress bar with title above it. It only works in Graphics mode.
+
+  @param TitleForeground Foreground color for Title.
+  @param TitleBackground Background color for Title.
+  @param Title   Title above progress bar.
+  @param ProgressColor   Progress bar color.
+  @param ProgressProgress (0-100)
+  @param PreviousValue   The previous value of the progress.
+
+  @retval  EFI_STATUS   Success update the progress bar
+
+**/
+EFI_STATUS
+PlatformBootManagerShowProgress (
+  IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,
+  IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,
+  IN CHAR16*Title,
+  IN EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,
+  IN UINTN Progress,
+  IN UINTN PreviousValue
+  )
+{
+  EFI_STATUS Status;
+  EFI_GRAPHICS_OUTPUT_PROTOCOL   *GraphicsOutput;
+  EFI_UGA_DRAW_PROTOCOL  *UgaDraw;
+  UINT32 SizeOfX;
+  UINT32 SizeOfY;
+  UINT32 ColorDepth;
+  UINT32 RefreshRate;
+  EFI_GRAPHICS_OUTPUT_BLT_PIXEL  Color;
+  UINTN  BlockHeight;
+  UINTN  BlockWidth;
+  UINTN  BlockNum;
+  UINTN  PosX;
+  UINTN  PosY;
+  UINTN  Index;
+
+  if (Progress > 100) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  UgaDraw = NULL;
+  Status = gBS->HandleProtocol (
+  gST->ConsoleOutHandle,
+  ,
+  (VOID **) 
+  );
+  if (EFI_ERROR (Status) && FeaturePcdGet (PcdUgaConsumeSupport)) {
+GraphicsOutput = NULL;
+
+Status = gBS->HandleProtocol (
+gST->ConsoleOutHandle,
+,
+(VOID **) 
+);
+  }
+  if (EFI_ERROR (Status)) {
+return EFI_UNSUPPORTED;
+  }
+
+  SizeOfX = 0;
+  SizeOfY = 0;
+  if (GraphicsOutput != NULL) {
+SizeOfX = GraphicsOutput->Mode->Info->HorizontalResolution;
+SizeOfY = GraphicsOutput->Mode->Info->VerticalResolution;
+  } else if (UgaDraw != NULL) {
+Status = UgaDraw->GetMode (
+UgaDraw,
+,
+,
+,
+
+);
+if (EFI_ERROR (Status)) {
+  return EFI_UNSUPPORTED;
+}
+  } else {
+return EFI_UNSUPPORTED;
+  }
+
+  BlockWidth  = 

[edk2-devel] [PATCH 01/15] [platforms/devel-riscv]: Silicon/SiFive: Initial version of SiFive silicon package

[Mr. Gilbert Chen]

Add SiFive silicon EDK2 metafile and header files of SiFive RISC-V cores.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Silicon/SiFive/Include/Library/SiFiveE51.h | 66 ++
 Silicon/SiFive/Include/Library/SiFiveU54.h | 66 ++
 .../SiFive/Include/Library/SiFiveU54MCCoreplex.h   | 61 
 Silicon/SiFive/SiFive.dec  | 45 +++
 4 files changed, 238 insertions(+)
 create mode 100644 Silicon/SiFive/Include/Library/SiFiveE51.h
 create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54.h
 create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h
 create mode 100644 Silicon/SiFive/SiFive.dec

diff --git a/Silicon/SiFive/Include/Library/SiFiveE51.h 
b/Silicon/SiFive/Include/Library/SiFiveE51.h
new file mode 100644
index 000..96b1082
--- /dev/null
+++ b/Silicon/SiFive/Include/Library/SiFiveE51.h
@@ -0,0 +1,66 @@
+/** @file
+  SiFive E51 Core library definitions.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License that accompanies this 
distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __SIFIVE_E51_CORE_H__
+#define __SIFIVE_E51_CORE_H__
+
+#include 
+
+#include 
+#include 
+
+/**
+  Function to build core specific information HOB.
+
+  @param  ParentProcessorGuidParent processor od this core. 
ParentProcessorGuid
+ could be the same as CoreGuid if one 
processor has
+ only one core.
+  @param  ParentProcessorUid Unique ID of pysical processor which owns 
this core.
+  @param  HartId Hart ID of this core.
+  @param  IsBootHart TRUE means this is the boot HART.
+  @param  GuidHobDataPointer to receive 
RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51CoreProcessorSpecificDataHob (
+  IN EFI_GUID  *ParentProcessorGuid,
+  IN UINTN ParentProcessorUid,
+  IN UINTN HartId,
+  IN BOOLEAN   IsBootHart,
+  OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobData
+  );
+
+/**
+  Function to build processor related SMBIOS information. RISC-V SMBIOS DXE 
driver collect
+  this information and build SMBIOS Type4 and Type7 record.
+
+  @param  ProcessorUidUnique ID of pysical processor which owns this core.
+  @param  SmbiosHobPtrPointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_HOB. 
The pointers
+  maintained in this structure is only valid before 
memory is discovered.
+  Access to those pointers after memory is installed 
will cause unexpected issues.
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51ProcessorSmbiosDataHob (
+  IN UINTN ProcessorUid,
+  OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr
+  );
+
+#endif
diff --git a/Silicon/SiFive/Include/Library/SiFiveU54.h 
b/Silicon/SiFive/Include/Library/SiFiveU54.h
new file mode 100644
index 000..216b584
--- /dev/null
+++ b/Silicon/SiFive/Include/Library/SiFiveU54.h
@@ -0,0 +1,66 @@
+/** @file
+  SiFive U54 Core library definitions.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License that accompanies this 
distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __SIFIVE_U54_CORE_H__
+#define __SIFIVE_U54_CORE_H__
+
+#include 
+
+#include 
+#include 
+
+/**
+  Function to build core specific information HOB.
+
+  @param  ParentProcessorGuidParent processor od this core. 
ParentProcessorGuid
+ could be the same as CoreGuid if one 
processor has
+ only one core.
+  @param  ParentProcessorUid Unique ID of pysical processor which owns 
this core.
+  @param  HartId Hart ID of this core.
+  @param  IsBootHart TRUE means this is the boot HART.
+  @param  GuidHobdataPointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU54CoreProcessorSpecificDataHob (
+  IN EFI_GUID  *ParentProcessorGuid,
+  IN UINTN 

[edk2-devel] [PATCH 08/15] [platforms/devel-riscv]: U500Pkg/Include: Header files of SiFive U500 platform

[Chen, Gilbert]

The initial header file commit for SiFive U5-MC Coreplex and U500 Core Local 
interrupt definitions.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h| 57 ++
 Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h  | 24 +
 2 files changed, 81 insertions(+)
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h

diff --git a/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h 
b/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h
new file mode 100644
index 000..c0323a5
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Include/SiFiveU5MCCoreplex.h
@@ -0,0 +1,57 @@
+/** @file
+  SiFive U54 Coreplex library definitions.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License that accompanies this 
distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __SIFIVE_U5MC_COREPLEX_H__
+#define __SIFIVE_U5MC_COREPLEX_H__
+
+#include 
+
+#include 
+#include 
+
+#define SIFIVE_U5MC_COREPLEX_MC_HART_ID 0
+
+/**
+  Build up U5MC coreplex processor core-specific information.
+
+  @param  UniqueId  U5MC unique ID.
+
+  @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCCoreplexProcessorSpecificDataHob (
+  IN UINTN UniqueId
+  );
+
+/**
+  Function to build processor related SMBIOS information. RISC-V SMBIOS DXE 
driver collect
+  this information and build SMBIOS Type4 and Type7 record.
+
+  @param  ProcessorUidUnique ID of pysical processor which owns this 
core.
+  @param  SmbiosDataHobPtrPointer to receive 
RISC_V_PROCESSOR_SMBIOS_DATA_HOB. The pointers
+  maintained in this structure is only valid 
before memory is discovered.
+  Access to those pointers after memory is 
installed will cause unexpected issues.
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCProcessorSmbiosDataHob (
+  IN UINTN ProcessorUid,
+  OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosDataHobPtr
+  );
+#endif
diff --git a/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h 
b/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h
new file mode 100644
index 000..426bf43
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Include/U500Clint.h
@@ -0,0 +1,24 @@
+/** @file
+  RISC-V Timer Architectural definition for U500 platform.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution. The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+**/
+#ifndef _U500_H_
+#define _U500_H_
+
+#define CLINT_REG_MTIME 0x0200BFF8
+#define CLINT_REG_MTIMECMP0 0x02004000
+#define CLINT_REG_MTIMECMP1 0x02004008
+#define CLINT_REG_MTIMECMP2 0x02004010
+#define CLINT_REG_MTIMECMP3 0x02004018
+#define CLINT_REG_MTIMECMP4 0x02004020
+
+#endif
\ No newline at end of file
--
2.7.4


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[edk2-devel] [PATCH 01/15] [platforms/devel-riscv]: Silicon/SiFive: Initial version of SiFive silicon package

[Chen, Gilbert]

Add SiFive silicon EDK2 metafile and header files of SiFive RISC-V cores.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Silicon/SiFive/Include/Library/SiFiveE51.h | 66 ++
 Silicon/SiFive/Include/Library/SiFiveU54.h | 66 ++
 .../SiFive/Include/Library/SiFiveU54MCCoreplex.h   | 61 
 Silicon/SiFive/SiFive.dec  | 45 +++
 4 files changed, 238 insertions(+)
 create mode 100644 Silicon/SiFive/Include/Library/SiFiveE51.h
 create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54.h
 create mode 100644 Silicon/SiFive/Include/Library/SiFiveU54MCCoreplex.h
 create mode 100644 Silicon/SiFive/SiFive.dec

diff --git a/Silicon/SiFive/Include/Library/SiFiveE51.h 
b/Silicon/SiFive/Include/Library/SiFiveE51.h
new file mode 100644
index 000..96b1082
--- /dev/null
+++ b/Silicon/SiFive/Include/Library/SiFiveE51.h
@@ -0,0 +1,66 @@
+/** @file
+  SiFive E51 Core library definitions.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License that accompanies this 
distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __SIFIVE_E51_CORE_H__
+#define __SIFIVE_E51_CORE_H__
+
+#include 
+
+#include 
+#include 
+
+/**
+  Function to build core specific information HOB.
+
+  @param  ParentProcessorGuidParent processor od this core. 
ParentProcessorGuid
+ could be the same as CoreGuid if one 
processor has
+ only one core.
+  @param  ParentProcessorUid Unique ID of pysical processor which owns 
this core.
+  @param  HartId Hart ID of this core.
+  @param  IsBootHart TRUE means this is the boot HART.
+  @param  GuidHobDataPointer to receive 
RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51CoreProcessorSpecificDataHob (
+  IN EFI_GUID  *ParentProcessorGuid,
+  IN UINTN ParentProcessorUid,
+  IN UINTN HartId,
+  IN BOOLEAN   IsBootHart,
+  OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobData
+  );
+
+/**
+  Function to build processor related SMBIOS information. RISC-V SMBIOS DXE 
driver collect
+  this information and build SMBIOS Type4 and Type7 record.
+
+  @param  ProcessorUidUnique ID of pysical processor which owns this core.
+  @param  SmbiosHobPtrPointer to receive RISC_V_PROCESSOR_SMBIOS_DATA_HOB. 
The pointers
+  maintained in this structure is only valid before 
memory is discovered.
+  Access to those pointers after memory is installed 
will cause unexpected issues.
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51ProcessorSmbiosDataHob (
+  IN UINTN ProcessorUid,
+  OUT RISC_V_PROCESSOR_SMBIOS_DATA_HOB **SmbiosHobPtr
+  );
+
+#endif
diff --git a/Silicon/SiFive/Include/Library/SiFiveU54.h 
b/Silicon/SiFive/Include/Library/SiFiveU54.h
new file mode 100644
index 000..216b584
--- /dev/null
+++ b/Silicon/SiFive/Include/Library/SiFiveU54.h
@@ -0,0 +1,66 @@
+/** @file
+  SiFive U54 Core library definitions.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials are licensed and made available 
under
+  the terms and conditions of the BSD License that accompanies this 
distribution.
+  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php.
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#ifndef __SIFIVE_U54_CORE_H__
+#define __SIFIVE_U54_CORE_H__
+
+#include 
+
+#include 
+#include 
+
+/**
+  Function to build core specific information HOB.
+
+  @param  ParentProcessorGuidParent processor od this core. 
ParentProcessorGuid
+ could be the same as CoreGuid if one 
processor has
+ only one core.
+  @param  ParentProcessorUid Unique ID of pysical processor which owns 
this core.
+  @param  HartId Hart ID of this core.
+  @param  IsBootHart TRUE means this is the boot HART.
+  @param  GuidHobdataPointer to RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU54CoreProcessorSpecificDataHob (
+  IN EFI_GUID  *ParentProcessorGuid,
+  IN UINTN 

[edk2-devel] [PATCH 14/15] [platforms/devel-riscv]: U500Pkg/PlatformPei: Platform initialization PEIM

[Chen, Gilbert]

This is the platform-implementation specific library which is executed in early 
PEI phase for platform initialization.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c  |  55 
 .../U500Pkg/Universal/Pei/PlatformPei/MemDetect.c  |  80 ++
 .../U500Pkg/Universal/Pei/PlatformPei/Platform.c   | 319 +
 .../U500Pkg/Universal/Pei/PlatformPei/Platform.h   |  97 +++
 .../Universal/Pei/PlatformPei/PlatformPei.inf  |  82 ++
 5 files changed, 633 insertions(+)
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/PlatformPei.inf

diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
new file mode 100644
index 000..04ac7ac
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Fv.c
@@ -0,0 +1,55 @@
+/** @file
+  Build FV related hobs for platform.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include "PiPei.h"
+#include "Platform.h"
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Publish PEI & DXE (Decompressed) Memory based FVs to let PEI
+  and DXE know about them.
+
+  @retval EFI_SUCCESS   Platform PEI FVs were initialized successfully.
+
+**/
+EFI_STATUS
+PeiFvInitialization (
+  VOID
+  )
+{
+  DEBUG ((EFI_D_INFO, "Platform PEI Firmware Volume Initialization\n"));
+  //
+  // Let DXE know about the DXE FV
+  //
+  BuildFvHob (PcdGet32 (PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize));
+  DEBUG ((EFI_D_INFO, "Platform builds DXE FV at %x, size %x.\n", PcdGet32 
(PcdRiscVDxeFvBase), PcdGet32 (PcdRiscVDxeFvSize)));
+
+  //
+  // Let PEI know about the DXE FV so it can find the DXE Core
+  //
+  PeiServicesInstallFvInfoPpi (
+NULL,
+(VOID *)(UINTN) PcdGet32 (PcdRiscVDxeFvBase),
+PcdGet32 (PcdRiscVDxeFvSize),
+NULL,
+NULL
+);
+
+  return EFI_SUCCESS;
+}
diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
new file mode 100644
index 000..3c047f1
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/MemDetect.c
@@ -0,0 +1,80 @@
+/**@file
+  Memory Detection for Virtual Machines.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+Module Name:
+
+  MemDetect.c
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include "Platform.h"
+
+
+/**
+  Publish PEI core memory
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+PublishPeiMemory (
+  VOID
+  )
+{
+  EFI_STATUS  Status;
+  EFI_PHYSICAL_ADDRESSMemoryBase;
+  UINT64  MemorySize;
+
+  MemoryBase = 0x8000UL + 0x100UL;
+  MemorySize = 0x4000UL - 0x100UL; //1GB - 16MB
+
+  DEBUG((EFI_D_INFO, "%a: MemoryBase:0x%x MemorySize:%d\n", __FUNCTION__, 
MemoryBase, MemorySize));
+
+  //
+  // Publish this memory to the PEI Core
+  //
+  Status = PublishSystemMemory(MemoryBase, MemorySize);
+  ASSERT_EFI_ERROR (Status);
+
+  return Status;
+}
+
+/**
+  Publish system RAM and reserve memory regions
+
+**/
+VOID
+InitializeRamRegions (
+  VOID
+  )
+{
+  AddMemoryRangeHob(0x8100UL, 0x8100UL + 0x3F00UL);
+
+}
diff --git a/Platform/RiscV/SiFive/U500Pkg/Universal/Pei/PlatformPei/Platform.c 

[edk2-devel] [PATCH 02/15] [platforms/devel-riscv]: Silicon/SiFive: Add library module of SiFive RISC-V cores

[Mr. Gilbert Chen]

Initial version of SiFive RISC-V core libraries. Library of each core creates 
processor core SMBIOS data hob for building SMBIOS records in DXE phase.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c| 248 +
 .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf|  57 
 .../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c| 300 +
 .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf|  57 
 .../Library/PeiCoreInfoHobLib/CoreInfoHob.c| 191 +
 .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf|  56 
 6 files changed, 909 insertions(+)
 create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
 create mode 100644 
Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
 create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
 create mode 100644 
Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
 create mode 100644 
Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
 create mode 100644 
Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf

diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c 
b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 000..1009b1e
--- /dev/null
+++ b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,248 @@
+/**@file
+  Build up platform processor information.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Function to build core specific information HOB. RISC-V SMBIOS DXE driver 
collect
+  this information and build SMBIOS Type44.
+
+  @param  ParentProcessorGuidParent processor od this core. 
ParentProcessorGuid
+ could be the same as CoreGuid if one 
processor has
+ only one core.
+  @param  ParentProcessorUid Unique ID of pysical processor which owns 
this core.
+  @param  HartId Hart ID of this core.
+  @param  IsBootHart TRUE means this is the boot HART.
+  @param  GuidHobDataPointer to receive   EFI_HOB_GUID_TYPE.
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51CoreProcessorSpecificDataHob (
+  IN EFI_GUID  *ParentProcessorGuid,
+  IN UINTN ParentProcessorUid,
+  IN UINTN HartId,
+  IN BOOLEAN   IsBootHart,
+  OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobData
+  )
+{
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *CoreGuidHob;
+  EFI_GUID *ProcessorSpecDataHobGuid;
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB ProcessorSpecDataHob;
+  struct sbi_scratch *ThisHartSbiScratch;
+  struct sbi_platform *ThisHartSbiPlatform;
+  EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+  EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific;
+
+  DEBUG ((EFI_D_INFO, "%a: Entry.\n", __FUNCTION__));
+
+  if (GuidHobData == NULL) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  ThisHartSbiScratch = sbi_hart_id_to_scratch (sbi_scratch_thishart_ptr(), 
(UINT32)HartId);
+  DEBUG ((EFI_D_INFO, "SBI Scratch is at 0x%x.\n", ThisHartSbiScratch));
+  ThisHartSbiPlatform = (struct sbi_platform 
*)sbi_platform_ptr(ThisHartSbiScratch);
+  DEBUG ((EFI_D_INFO, "SBI platform is at 0x%x.\n", ThisHartSbiPlatform));
+  FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT 
*)ThisHartSbiPlatform->firmware_context;
+  DEBUG ((EFI_D_INFO, "Firmware Context is at 0x%x.\n", FirmwareContext));
+  FirmwareContextHartSpecific = FirmwareContext->HartSpecific[HartId];
+  DEBUG ((EFI_D_INFO, "Firmware Context Hart specific is at 0x%x.\n", 
FirmwareContextHartSpecific));
+
+  //
+  // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+  //
+  CommonFirmwareContextHartSpecificInfo (
+  FirmwareContextHartSpecific,
+  ParentProcessorGuid,
+  ParentProcessorUid,
+  (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid),
+  HartId,
+  IsBootHart,
+  
+  );
+  ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L
 = TO_BE_FILLED;
+  

[edk2-devel] [PATCH 05/15] [platforms/devel-riscv]: RiscV/Library: Initial version of libraries introduced in RISC-V platform package

[Chen, Gilbert]

FirmwareContextProcessorSpecificLib
- Common library to consume EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC and build 
up processor specific data HOB.

RealTimClockLibNull
- NULL instance of Real Time Clock library.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../FirmwareContextProcessorSpecificLib.c  |  88 +
 .../FirmwareContextProcessorSpecificLib.inf|  39 
 .../RealTimeClockLibNull/RealTimeClockLibNull.c| 212 +
 .../RealTimeClockLibNull/RealTimeClockLibNull.inf  |  36 
 4 files changed, 375 insertions(+)
 create mode 100644 
Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
 create mode 100644 
Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf
 create mode 100644 
Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.c
 create mode 100644 
Platform/RiscV/Library/RealTimeClockLibNull/RealTimeClockLibNull.inf

diff --git 
a/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
 
b/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
new file mode 100644
index 000..0ce2570
--- /dev/null
+++ 
b/Platform/RiscV/Library/FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.c
@@ -0,0 +1,88 @@
+/**@file
+  Common library to build upfirmware context processor-specific information
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Build up common firmware context processor-specific information
+
+  @param  FirmwareContextHartSpecific  Pointer to 
EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC
+  @param  ParentProcessorGuid  Pointer to GUID of Processor which 
contains this core
+  @param  ParentProcessorUid   Unique ID of pysical processor which 
owns this core.
+  @param  CoreGuid Pointer to GUID of core
+  @param  HartId   Hart ID of this core.
+  @param  IsBootHart   This is boot hart or not
+  @param  ProcessorSpecDataHob Pointer to 
RISC_V_PROCESSOR_SPECIFIC_DATA_HOB
+
+  @return EFI_STATUS
+
+**/
+EFI_STATUS
+EFIAPI
+CommonFirmwareContextHartSpecificInfo (
+  EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific,
+  EFI_GUID  *ParentProcessorGuid,
+  UINTN ParentProcessorUid,
+  EFI_GUID  *CoreGuid,
+  UINTN HartId,
+  BOOLEAN   IsBootHart,
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *ProcessorSpecDataHob
+  )
+{
+  //
+  // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+  //
+  CopyGuid (>ParentPrcessorGuid, ParentProcessorGuid);
+  ProcessorSpecDataHob->ParentProcessorUid = ParentProcessorUid;
+  CopyGuid (>CoreGuid, CoreGuid);
+  ProcessorSpecDataHob->Context = NULL;
+  ProcessorSpecDataHob->ProcessorSpecificData.Revision = 
SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA_REVISION;
+  ProcessorSpecDataHob->ProcessorSpecificData.Length   = sizeof 
(SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA);
+  ProcessorSpecDataHob->ProcessorSpecificData.HartId.Value64_L = 
(UINT64)HartId;
+  ProcessorSpecDataHob->ProcessorSpecificData.HartId.Value64_H = 0;
+  ProcessorSpecDataHob->ProcessorSpecificData.BootHartId   = 
(UINT8)IsBootHart;
+  ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported = 
FirmwareContextHartSpecific->IsaExtensionSupported;
+  ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported   = 
SMBIOS_RISC_V_PSD_MACHINE_MODE_SUPPORTED;
+  if ((ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported & 
RISC_V_ISA_SUPERVISOR_MODE_IMPLEMENTED) != 0) {
+ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported |= 
SMBIOS_RISC_V_PSD_SUPERVISOR_MODE_SUPPORTED;
+  }
+  if ((ProcessorSpecDataHob->ProcessorSpecificData.InstSetSupported & 
RISC_V_ISA_USER_MODE_IMPLEMENTED) != 0) {
+ProcessorSpecDataHob->ProcessorSpecificData.PrivilegeModeSupported |= 
SMBIOS_RISC_V_PSD_USER_MODE_SUPPORTED;
+  }
+  ProcessorSpecDataHob->ProcessorSpecificData.MachineVendorId.Value64_L = 
FirmwareContextHartSpecific->MachineVendorId.Value64_L;
+  ProcessorSpecDataHob->ProcessorSpecificData.MachineVendorId.Value64_H = 
FirmwareContextHartSpecific->MachineVendorId.Value64_H;
+  

[edk2-devel] [PATCH 07/15] [platforms/devel-riscv]: RiscV/SiFive: Initial version of SiFive U500 platform package

[Chen, Gilbert]

The initial version of SiFive U500 platform package.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Platform/RiscV/SiFive/U500Pkg/Readme.md|  30 ++
 Platform/RiscV/SiFive/U500Pkg/U500.dec |  40 ++
 Platform/RiscV/SiFive/U500Pkg/U500.dsc | 596 +
 Platform/RiscV/SiFive/U500Pkg/U500.fdf | 373 
 Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc |  58 +++
 Platform/RiscV/SiFive/U500Pkg/U500.uni | Bin 0 -> 1730 bytes
 Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni | Bin 0 -> 1396 bytes
 Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc |  85 
 8 files changed, 1182 insertions(+)
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/Readme.md
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dec
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.dsc
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.fdf.inc
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500.uni
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/U500PkgExtra.uni
 create mode 100644 Platform/RiscV/SiFive/U500Pkg/VarStore.fdf.inc

diff --git a/Platform/RiscV/SiFive/U500Pkg/Readme.md 
b/Platform/RiscV/SiFive/U500Pkg/Readme.md
new file mode 100644
index 000..3aaaf77
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Readme.md
@@ -0,0 +1,30 @@
+# Introduction
+
+## U500 Platform Package
+This is a sample RISC-V EDK2 platform package used agaist SiFive Freedom U500 
VC707 FPGA Dev Kit, please refer to "SiFive Freedom U500 VC707 FPGA Getting 
Started Guide" on https://www.sifive.com/documentation. This package is built 
with below common packages, 
+- **RiscVPlatformPkg**, edk2-platform/Platform/RiscV
+- **RiscVPkg**, edk2 master branch (Currently is in edk2-staging/RISC-V branch)
+
+This package provides librareis and modules which are SiFive U500 platform 
implementation-specific and incorporate with common RISC-V packages mentioned 
above.
+
+### OpneSbiPlatformLib
+In order to reduce the dependencies with RISC-V OpenSBI project 
(https://github.com/riscv/opensbi) and less burdens to EDK2 build process, the 
implementation of RISC-V EDK2 platform is leverage platform source code from 
OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib  is cloned from 
RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build 
environment.
+
+### PeiCoreInfoHobLib
+This is the library to create RISC-V core characteristics for building up 
RISC-V related SMBIOS records to support the unified boot loader and OS image. 
This library leverage the silicon libraries provided in Silicon/SiFive.
+
+### RiscVPlatformTimerLib
+This is U500 platform timer library which has the platform-specific timer 
implementation.
+
+### PlatformPei
+This is the platform-implementation specific library which is executed in 
early PEI phase for platform initialization.
+
+### TimerDxe
+This is U500 platform timer DXE driver whcih has the platform-specific timer 
implementation.
+
+## U500 Platform PCD settings
+
+| **PCD name** |**Usage**|
+||--|
+|PcdNumberofU5Cores| Number of U5 core enabled on U500 platform|
+|PcdE5MCSupported| Indicates whether or not the Monitor Core (E5) is supported 
on U500 platform|
diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.dec 
b/Platform/RiscV/SiFive/U500Pkg/U500.dec
new file mode 100644
index 000..9886328
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/U500.dec
@@ -0,0 +1,40 @@
+## @file  U500.dec
+# This Package provides SiFive U500 modules and libraries.
+#
+# Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+#
+# This program and the accompanying materials are licensed and made available 
under
+# the terms and conditions of the BSD License which accompanies this 
distribution.
+# The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  DEC_SPECIFICATION  = 0x00010005
+  PACKAGE_NAME   = U500
+  PACKAGE_UNI_FILE   = U500.uni
+  PACKAGE_GUID   = D11E9DB9-5940-4642-979D-2114342140D2
+  PACKAGE_VERSION= 1.0
+
+[Includes]
+  Include
+
+[LibraryClasses]
+
+
+[Guids]
+  gUefiRiscVPlatformU500PkgTokenSpaceGuid  = {0xDFD87009, 0x27A1, 0x41DD, { 
0x84, 0xB1, 0x35, 0xB4, 0xB9, 0x0D, 0x17, 0x63 }}
+
+[PcdsFixedAtBuild]
+  
gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdNumberofU5Cores|0x8|UINT32|0x1000
+  
gUefiRiscVPlatformU500PkgTokenSpaceGuid.PcdE5MCSupported|TRUE|BOOLEAN|0x1001
+
+[PcdsPatchableInModule]
+
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  U500PkgExtra.uni
diff --git a/Platform/RiscV/SiFive/U500Pkg/U500.dsc 
b/Platform/RiscV/SiFive/U500Pkg/U500.dsc
new file mode 100644
index 

[edk2-devel] [PATCH 12/15] [platforms/devel-riscv]: U500Pkg/RamFvbServiceruntimeDxe: FVB driver for EFI variable.

[Chen, Gilbert]

Firmware Volume Block driver instance for ram based EFI variable on U500 
platform.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c |  133 +++
 .../FvbServicesRuntimeDxe.inf  |   88 ++
 .../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c  | 1129 
 .../Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h  |  193 
 .../RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c   |  156 +++
 .../Dxe/RamFvbServicesRuntimeDxe/RamFlash.c|  151 +++
 .../Dxe/RamFvbServicesRuntimeDxe/RamFlash.h|   92 ++
 .../Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c |   26 +
 8 files changed, 1968 insertions(+)
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbServicesRuntimeDxe.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockService.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FwBlockServiceDxe.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlash.h
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/RamFlashDxe.c

diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
new file mode 100644
index 000..bfed741
--- /dev/null
+++ 
b/Platform/RiscV/SiFive/U500Pkg/Universal/Dxe/RamFvbServicesRuntimeDxe/FvbInfo.c
@@ -0,0 +1,133 @@
+/**@file
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+  Copyright (c) 2006, Intel Corporation. All rights reserved.
+
+  This program and the accompanying materials are licensed and made available
+  under the terms and conditions of the BSD License which accompanies this
+  distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Module Name:
+
+FvbInfo.c
+
+  Abstract:
+
+Defines data structure that is the volume header found.These data is intent
+to decouple FVB driver with FV header.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The protocols, PPI and GUID defintions for this module
+//
+#include 
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+
+typedef struct {
+  UINT64  FvLength;
+  EFI_FIRMWARE_VOLUME_HEADER  FvbInfo;
+  //
+  // EFI_FV_BLOCK_MAP_ENTRYExtraBlockMap[n];//n=0
+  //
+  EFI_FV_BLOCK_MAP_ENTRY  End[1];
+} EFI_FVB_MEDIA_INFO;
+
+EFI_FVB_MEDIA_INFO  mPlatformFvbMediaInfo[] = {
+  //
+  // Systen NvStorage FVB
+  //
+  {
+FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+{
+  {
+0,
+  },  // ZeroVector[16]
+  EFI_SYSTEM_NV_DATA_FV_GUID,
+  FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+  FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+  FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize),
+  EFI_FVH_SIGNATURE,
+  EFI_FVB2_MEMORY_MAPPED |
+EFI_FVB2_READ_ENABLED_CAP |
+EFI_FVB2_READ_STATUS |
+EFI_FVB2_WRITE_ENABLED_CAP |
+EFI_FVB2_WRITE_STATUS |
+EFI_FVB2_ERASE_POLARITY |
+EFI_FVB2_ALIGNMENT_16,
+  sizeof (EFI_FIRMWARE_VOLUME_HEADER) + sizeof (EFI_FV_BLOCK_MAP_ENTRY),
+  0,  // CheckSum
+  0,  // ExtHeaderOffset
+  {
+0,
+  },  // Reserved[1]
+  2,  // Revision
+  {
+{
+  (FixedPcdGet32 (PcdFlashNvStorageVariableSize) +
+   FixedPcdGet32 (PcdFlashNvStorageFtwWorkingSize) +
+   FixedPcdGet32 (PcdFlashNvStorageFtwSpareSize)) /
+  FixedPcdGet32 (PcdVariableFdBlockSize),
+  FixedPcdGet32 (PcdVariableFdBlockSize),
+}
+  } // BlockMap[1]
+},
+{
+  {
+0,
+0
+  }
+}  // End[1]
+  }
+};
+
+EFI_STATUS
+GetFvbInfo (
+  IN  UINT64FvLength,
+  OUT EFI_FIRMWARE_VOLUME_HEADER**FvbInfo
+  )
+{
+  STATIC BOOLEAN Checksummed = FALSE;
+  UINTN Index;
+
+  if (!Checksummed) {
+for (Index = 0;
+ Index < sizeof (mPlatformFvbMediaInfo) / sizeof (EFI_FVB_MEDIA_INFO);
+ Index += 1) {
+  UINT16 Checksum;
+  mPlatformFvbMediaInfo[Index].FvbInfo.Checksum = 0;
+  Checksum = 

[edk2-devel] [PATCH 03/15] [platforms/devel-riscv]: platforms/RiscV: Initial version of RISC-V platform package

[Mr. Gilbert Chen]

Initial version of RISC-V platform package which provides the common libraries, 
drivers, PCD and etc. for RISC-V platform development.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Platform/RiscV/Readme.md |  88 +++
 Platform/RiscV/RiscVPlatformPkg.dec  |  75 ++
 Platform/RiscV/RiscVPlatformPkg.uni  | Bin 0 -> 1754 bytes
 Platform/RiscV/RiscVPlatformPkgExtra.uni | Bin 0 -> 1392 bytes
 4 files changed, 163 insertions(+)
 create mode 100644 Platform/RiscV/Readme.md
 create mode 100644 Platform/RiscV/RiscVPlatformPkg.dec
 create mode 100644 Platform/RiscV/RiscVPlatformPkg.uni
 create mode 100644 Platform/RiscV/RiscVPlatformPkgExtra.uni

diff --git a/Platform/RiscV/Readme.md b/Platform/RiscV/Readme.md
new file mode 100644
index 000..dd817eb
--- /dev/null
+++ b/Platform/RiscV/Readme.md
@@ -0,0 +1,88 @@
+# Introduction
+
+## EDK2 RISC-V Platform Package
+RISC-V platform package provides the generic and common modules for RISC-V 
platforms. RISC-V platform package could include RiscPlatformPkg.dec to use the 
common drivers, libraries, definitions, PCDs and etc. for the platform 
development.
+
+## EDK2 RISC-V Platforms
+RISC-V platform is created and maintained by RISC-V platform vendors. The 
directory of RISC-V platform should be created under Platform/RiscV. Vendor 
should create the folder under Platform/RiscV and name it using vendor name, 
under the vendor folder is the platform folder named by platform model name, 
code name or etc. (e.g. Platform/RiscV/SiFive/U500Pkg)
+
+## Build EDK2 RISC-V Platforms
+RISC-V platform package should provide EDK2 metafiles under RISC-V platform 
package folder (Platform/RiscV/{Vendor}/{Platform}). Build RISC-V platform 
package against edk2 and follow the build guidence mentioned in Readme.md under 
below link.
+https://github.com/tianocore/edk2-platforms
+
+### Download the sources ###
+```
+git clone https://github.com/tianocore/edk2-staging.git
+# Checkout RISC-V branch
+git clone https://github.com/tianocore/edk2-platforms.git
+# Checkout devel-riscv branch
+git clone https://github.com/tianocore/edk2-non-osi.git
+```
+
+### Requirements
+Build EDK2 RISC-V platform requires GCC RISC-V toolchain. Refer to 
https://github.com/riscv/riscv-gnu-toolchain for the details.
+
+### EDK2 project
+Currently, the EDK2 RISC-V platform can only build with edk2 project in 
**edk2-staging/RISC-V** branch. The build architecture whcih is supported and 
verified so far is "RISCV64". The verified RISC-V toolchain is GCC 7.1.1, 
toolchain tag is "GCC711RISCV" declared in tools_def.txt
+
+### Linux Build Instructions
+You can build the RISC-V platform using below script, 
+`build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t 
GCC711RISCV`
+
+Or modify target.txt to set up your build parameters.
+
+## RISC-V Platform PCD settings
+### EDK2 Firmware Volume Settings
+EDK2 Firmware volume related PCDs which declared in platform FDF file.
+
+| **PCD name** |**Usage**|
+||--|
+|PcdRiscVSecFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVSecFvSize| The size of SEC Firmware Volume|
+|PcdRiscVPeiFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVPeiFvSize| The size of SEC Firmware Volume|
+|PcdRiscVDxeFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVDxeFvSize| The size of SEC Firmware Volume|
+
+### EDK2 EFI Variable Region Settings
+The PCD settings regard to EFI Variable
+
+| **PCD name** |**Usage**|
+||--|
+|PcdVariableFdBaseAddress| The EFI variable firmware device base address|
+|PcdVariableFdSize| The EFI variable firmware device size|
+|PcdVariableFdBlockSize| The block size of EFI variable firmware device|
+|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within 
firmware device|
+|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable 
fault tolerance worksapce (FTW) within firmware device|
+|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable spare 
FTW within firmware device|
+
+### RISC-V Physical Memory Protection (PMP) Region Settings
+Below PCDs could be set in platform FDF file.
+
+| **PCD name** |**Usage**|
+||--|
+|PcdFwStartAddress| The starting address of firmware region to protected by 
PMP|
+|PcdFwEndAddress| The ending address of firmware region to protected by PMP|
+
+### RISC-V Processor HART Settings
+
+| **PCD name** |**Usage**|
+||--|
+|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation 
specific|
+|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot 
system to OS|
+
+### RISC-V OpenSBI Settings
+
+| **PCD name** |**Usage**|
+||--|
+|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RISC-V 
HARTs|
+|PcdScratchRamSize| The total size of OpenSBI scratch buffer for 

[edk2-devel] [PATCH 15/15] [platforms/devel-riscv]: Platforms: Readme file updates

[Mr. Gilbert Chen]

Update Readme.md and Maintainers.txt for RISV-V platforms.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Maintainers.txt | 9 +
 Readme.md   | 5 +
 2 files changed, 14 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index 876ae56..c494c9d 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -108,6 +108,11 @@ R: Marcin Wojtas 
 Platform/SolidRun/Armada80x0McBin
 R: Marcin Wojtas 

+Platform/RiscV
+Platform/RiscV/SiFive/U500Pkg
+R: Abner Chang 
+R: Gilbert Chen 
+
 Silicon
 M: Ard Biesheuvel 
 M: Leif Lindholm 
@@ -151,3 +156,7 @@ M: Liming Gao 

 Silicon/Marvell
 R: Marcin Wojtas 
+
+Silicon/SiFive
+R: Abner Chang 
+R: Gilbert Chen 
diff --git a/Readme.md b/Readme.md
index 63e59f6..4572d19 100644
--- a/Readme.md
+++ b/Readme.md
@@ -52,6 +52,7 @@ ARM | arm-linux-gnueabihf-
 IA32| i?86-linux-gnu-* _or_ x86_64-linux-gnu-
 IPF | ia64-linux-gnu
 X64 | x86_64-linux-gnu-
+RISCV64 | riscv64-unknown-elf-

 \* i386, i486, i586 or i686

@@ -243,6 +244,10 @@ For more information, see the
 ## Raspberry Pi
 * [Pi 3](Platform/RaspberryPi/RPi3)

+## RISC-V
+### SiFive
+* [Freedom U500 VC707 FPGA](Platform/RiscV/SiFive/U500Pkg)
+
 ## Socionext
 * [SynQuacer](Platform/Socionext/DeveloperBox)

--
2.7.4


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[edk2-devel] [PATCH 02/15] [platforms/devel-riscv]: Silicon/SiFive: Add library module of SiFive RISC-V cores

[Chen, Gilbert]

Initial version of SiFive RISC-V core libraries. Library of each core creates 
processor core SMBIOS data hob for building SMBIOS records in DXE phase.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c| 248 +
 .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf|  57 
 .../U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c| 300 +
 .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf|  57 
 .../Library/PeiCoreInfoHobLib/CoreInfoHob.c| 191 +
 .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf|  56 
 6 files changed, 909 insertions(+)
 create mode 100644 Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
 create mode 100644 
Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
 create mode 100644 Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/CoreInfoHob.c
 create mode 100644 
Silicon/SiFive/U54/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
 create mode 100644 
Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/CoreInfoHob.c
 create mode 100644 
Silicon/SiFive/U54MCCoreplex/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf

diff --git a/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c 
b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 000..1009b1e
--- /dev/null
+++ b/Silicon/SiFive/E51/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,248 @@
+/**@file
+  Build up platform processor information.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Function to build core specific information HOB. RISC-V SMBIOS DXE driver 
collect
+  this information and build SMBIOS Type44.
+
+  @param  ParentProcessorGuidParent processor od this core. 
ParentProcessorGuid
+ could be the same as CoreGuid if one 
processor has
+ only one core.
+  @param  ParentProcessorUid Unique ID of pysical processor which owns 
this core.
+  @param  HartId Hart ID of this core.
+  @param  IsBootHart TRUE means this is the boot HART.
+  @param  GuidHobDataPointer to receive   EFI_HOB_GUID_TYPE.
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateE51CoreProcessorSpecificDataHob (
+  IN EFI_GUID  *ParentProcessorGuid,
+  IN UINTN ParentProcessorUid,
+  IN UINTN HartId,
+  IN BOOLEAN   IsBootHart,
+  OUT RISC_V_PROCESSOR_SPECIFIC_DATA_HOB **GuidHobData
+  )
+{
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *CoreGuidHob;
+  EFI_GUID *ProcessorSpecDataHobGuid;
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB ProcessorSpecDataHob;
+  struct sbi_scratch *ThisHartSbiScratch;
+  struct sbi_platform *ThisHartSbiPlatform;
+  EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;
+  EFI_RISCV_FIRMWARE_CONTEXT_HART_SPECIFIC *FirmwareContextHartSpecific;
+
+  DEBUG ((EFI_D_INFO, "%a: Entry.\n", __FUNCTION__));
+
+  if (GuidHobData == NULL) {
+return EFI_INVALID_PARAMETER;
+  }
+
+  ThisHartSbiScratch = sbi_hart_id_to_scratch (sbi_scratch_thishart_ptr(), 
(UINT32)HartId);
+  DEBUG ((EFI_D_INFO, "SBI Scratch is at 0x%x.\n", ThisHartSbiScratch));
+  ThisHartSbiPlatform = (struct sbi_platform 
*)sbi_platform_ptr(ThisHartSbiScratch);
+  DEBUG ((EFI_D_INFO, "SBI platform is at 0x%x.\n", ThisHartSbiPlatform));
+  FirmwareContext = (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT 
*)ThisHartSbiPlatform->firmware_context;
+  DEBUG ((EFI_D_INFO, "Firmware Context is at 0x%x.\n", FirmwareContext));
+  FirmwareContextHartSpecific = FirmwareContext->HartSpecific[HartId];
+  DEBUG ((EFI_D_INFO, "Firmware Context Hart specific is at 0x%x.\n", 
FirmwareContextHartSpecific));
+
+  //
+  // Build up RISC_V_PROCESSOR_SPECIFIC_DATA_HOB.
+  //
+  CommonFirmwareContextHartSpecificInfo (
+  FirmwareContextHartSpecific,
+  ParentProcessorGuid,
+  ParentProcessorUid,
+  (EFI_GUID *)PcdGetPtr (PcdSiFiveE51CoreGuid),
+  HartId,
+  IsBootHart,
+  
+  );
+  ProcessorSpecDataHob.ProcessorSpecificData.MModeExcepDelegation.Value64_L
 = TO_BE_FILLED;
+  

[edk2-devel] [PATCH 06/15] [platforms/devel-riscv]: RiscV/Universal: Initial version of common RISC-V SEC module

[Chen, Gilbert]

Common RISC-V SEC module for RISC-V platforms.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s | 439 
 Platform/RiscV/Universal/Sec/SecMain.c  | 529 
 Platform/RiscV/Universal/Sec/SecMain.h  |  56 +++
 Platform/RiscV/Universal/Sec/SecMain.inf|  81 
 4 files changed, 1105 insertions(+)
 create mode 100644 Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s
 create mode 100644 Platform/RiscV/Universal/Sec/SecMain.c
 create mode 100644 Platform/RiscV/Universal/Sec/SecMain.h
 create mode 100644 Platform/RiscV/Universal/Sec/SecMain.inf

diff --git a/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s 
b/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s
new file mode 100644
index 000..a5ca481
--- /dev/null
+++ b/Platform/RiscV/Universal/Sec/Riscv64/SecEntry.s
@@ -0,0 +1,439 @@
+/*
+ * Copyright (c) 2019 , Hewlett Packard Enterprise Development LP. All rights 
reserved.
+ *
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Anup Patel 
+ *
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+.text
+.align 3
+.global ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+  /*
+   * Jump to warm-boot if this is not the selected core booting,
+   */
+  csrr a6, CSR_MHARTID
+  li a5, FixedPcdGet32 (PcdBootHartId)
+  bne a6, a5, _wait_for_boot_hart
+
+  // light LED on
+  li a5, 0x54002000
+  li a4, 0xff
+  sw a4, 0x08(a5)
+  li a4, 0x11
+  sw a4, 0x0c(a5)
+
+  lira, 0
+  call_reset_regs
+
+  /* Preload HART details
+   * s7 -> HART Count
+   * s8 -> HART Stack Size
+   */
+  li s7, FixedPcdGet32 (PcdHartCount)
+  li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
+
+  /* Setup scratch space for all the HARTs*/
+  li  tp, FixedPcdGet32 (PcdScratchRamBase)
+  mula5, s7, s8
+  addtp, tp, a5
+  /* Keep a copy of tp */
+  addt3, tp, zero
+  /* Counter */
+  lit2, 1
+  /* hartid 0 is mandated by ISA */
+  lit1, 0
+_scratch_init:
+  addtp, t3, zero
+  mula5, s8, t1
+  subtp, tp, a5
+  lia5, SBI_SCRATCH_SIZE
+  subtp, tp, a5
+
+  /* Initialize scratch space */
+  li  a4, FixedPcdGet32 (PcdFwStartAddress)
+  li  a5, FixedPcdGet32 (PcdFwEndAddress)
+  suba5, a5, a4
+  sda4, SBI_SCRATCH_FW_START_OFFSET(tp)
+  sda5, SBI_SCRATCH_FW_SIZE_OFFSET(tp)
+  /* Note: fw_next_arg1() uses a0, a1, and ra */
+  callfw_next_arg1
+  sda0, SBI_SCRATCH_NEXT_ARG1_OFFSET(tp)
+  /* Note: fw_next_addr() uses a0, a1, and ra */
+  callfw_next_addr
+  sda0, SBI_SCRATCH_NEXT_ADDR_OFFSET(tp)
+  lia4, PRV_S
+  sda4, SBI_SCRATCH_NEXT_MODE_OFFSET(tp)
+  laa4, _start_warm
+  sda4, SBI_SCRATCH_WARMBOOT_ADDR_OFFSET(tp)
+  laa4, platform
+  sda4, SBI_SCRATCH_PLATFORM_ADDR_OFFSET(tp)
+  laa4, _hartid_to_scratch
+  sda4, SBI_SCRATCH_HARTID_TO_SCRATCH_OFFSET(tp)
+  sdzero, SBI_SCRATCH_TMP0_OFFSET(tp)
+#ifdef FW_OPTIONS
+  lia4, FW_OPTIONS
+  sda4, SBI_SCRATCH_OPTIONS_OFFSET(tp)
+#else
+  sdzero, SBI_SCRATCH_OPTIONS_OFFSET(tp)
+#endif
+  addt1, t1, t2
+  bltt1, s7, _scratch_init
+
+  /* Fill-out temporary memory with 55aa*/
+  lia4, FixedPcdGet32 (PcdTemporaryRamBase)
+  lia5, FixedPcdGet32 (PcdTemporaryRamSize)
+  add a5, a4, a5
+1:
+  li a3, 0x5AA55AA55AA55AA5
+  sda3, (a4)
+  adda4, a4, __SIZEOF_POINTER__
+  blta4, a5, 1b
+
+  /* Update boot hart flag */
+  laa4, _boot_hart_done
+  lia5, 1
+  sda5, (a4)
+
+  /* Wait for boot hart */
+_wait_for_boot_hart:
+  laa4, _boot_hart_done
+  lda5, (a4)
+  /* Reduce the bus traffic so that boot hart may proceed faster */
+  nop
+  nop
+  nop
+  beqza5, _wait_for_boot_hart
+
+_start_warm:
+  lira, 0
+  call_reset_regs
+
+  /* Disable and clear all interrupts */
+  csrwCSR_MIE, zero
+  csrwCSR_MIP, zero
+
+  li s7, FixedPcdGet32 (PcdHartCount)
+  li s8, FixedPcdGet32 (PcdOpenSbiStackSize)
+
+  /* HART ID should be within expected limit */
+  csrrs6, CSR_MHARTID
+  bges6, s7, _start_hang
+
+  /* find the scratch space for this hart */
+  litp, FixedPcdGet32 (PcdScratchRamBase)
+  mula5, s7, s8
+  addtp, tp, a5
+  mula5, s8, s6
+  subtp, tp, a5
+  lia5, SBI_SCRATCH_SIZE
+  subtp, tp, a5
+
+  /* update the mscratch */
+  csrwCSR_MSCRATCH, tp
+
+  /*make room for Hart specific Firmware Context*/
+  lia5, FIRMWARE_CONTEXT_HART_SPECIFIC_SIZE
+  subtp, tp, a5
+
+  /* Setup stack */
+  add sp, tp, zero
+
+  /* Setup stack for the Hart executing EFI to top of temporary ram*/
+  csrr a6, CSR_MHARTID
+  li a5, FixedPcdGet32 (PcdBootHartId)
+  bne a6, a5, 1f
+
+  li a4, FixedPcdGet32(PcdTemporaryRamBase)
+  li a5, FixedPcdGet32(PcdTemporaryRamSize)
+  addsp, a4, a5
+  1:
+
+  /* Setup trap handler */
+  laa4, _trap_handler
+  csrwCSR_MTVEC, a4
+  /* Make sure that mtvec is updated */
+  1:
+  csrra5, CSR_MTVEC
+  bnea4, a5, 1b
+
+  /* Call library constructors before jup to SEC core */
+  call ProcessLibraryConstructorList
+
+  /* jump to SEC 

[edk2-devel] [PATCH 11/15] [platforms/devel-riscv]: U500Pkg/Library: Library instances of U500 platform library.

[Chen, Gilbert]

PeiCoreInfoHobLib
- This is the library to create RISC-V core characteristics for building up 
RISC-V related SMBIOS records to support the unified boot loader and OS image.

- RiscVPlatformTimerLib
This is U500 platform timer library which has the platform-specific timer 
implementation.

- SerialPortLib
U500 serial port platform library

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../Library/PeiCoreInfoHobLib/CoreInfoHob.c| 201 +
 .../PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf|  64 ++
 .../RiscVPlatformTimerLib.inf  |  46 
 .../RiscVPlatformTimerLib/RiscVPlatformTimerLib.s  |  54 +
 .../U500Pkg/Library/SerialIoLib/SerialIoLib.inf|  37 +++
 .../U500Pkg/Library/SerialIoLib/SerialPortLib.c| 247 +
 .../Library/SerialIoLib/U500SerialPortLib.uni  |  22 ++
 7 files changed, 671 insertions(+)
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/PeiCoreInfoHobLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/RiscVPlatformTimerLib/RiscVPlatformTimerLib.s
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialIoLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/SerialPortLib.c
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/SerialIoLib/U500SerialPortLib.uni

diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c 
b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
new file mode 100644
index 000..2db4fdc
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Library/PeiCoreInfoHobLib/CoreInfoHob.c
@@ -0,0 +1,201 @@
+/**@file
+  Build up platform processor information.
+
+  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD 
License
+  which accompanies this distribution.  The full text of the license may be 
found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+//
+// The package level header files this module uses
+//
+#include 
+
+//
+// The Library classes this module consumes
+//
+#include 
+#include 
+#include 
+
+#include 
+#include 
+#include 
+#include 
+#include 
+
+/**
+  Build up processor-specific HOB for U5MC Coreplex
+
+  @param  UniqueId  Unique ID of this U5MC Coreplex processor
+
+  @return EFI_SUCCESS The PEIM initialized successfully.
+
+**/
+EFI_STATUS
+EFIAPI
+CreateU5MCCoreplexProcessorSpecificDataHob (
+  IN UINTN UniqueId
+  )
+{
+  EFI_STATUS Status;
+  UINT32 HartIdNumber;
+  RISC_V_PROCESSOR_SPECIFIC_DATA_HOB *GuidHobData;
+  EFI_GUID *ParentCoreGuid;
+  BOOLEAN MCSupport;
+
+  DEBUG ((EFI_D_INFO, "Building U5 Coreplex processor information HOB\n"));
+
+  HartIdNumber = 0;
+  ParentCoreGuid = PcdGetPtr(PcdSiFiveU5MCCoreplexGuid);
+  MCSupport = PcdGetBool (PcdE5MCSupported);
+  if (MCSupport == TRUE) {
+Status = CreateE51CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, 
HartIdNumber, FALSE, );
+if (EFI_ERROR (Status)) {
+  DEBUG ((EFI_D_ERROR, "Faile to build U5MC processor informatino HOB\n"));
+  ASSERT (FALSE);
+}
+HartIdNumber ++;
+DEBUG ((EFI_D_INFO, "Support E5 Monitor core on U500 platform, HOB at 
address 0x%x\n", GuidHobData));
+  }
+  for (; HartIdNumber < (FixedPcdGet32 (PcdNumberofU5Cores) + 
(UINT32)MCSupport); HartIdNumber ++) {
+Status = CreateU54CoreProcessorSpecificDataHob (ParentCoreGuid, UniqueId, 
HartIdNumber, (HartIdNumber == FixedPcdGet32 (PcdBootHartId))? TRUE: FALSE, 
);
+if (EFI_ERROR (Status)) {
+  DEBUG ((EFI_D_ERROR, "Faile to build U5MC processor informatino HOB\n"));
+  ASSERT (FALSE);
+}
+DEBUG ((EFI_D_INFO, "Support U5 application core on U500 platform, HOB 
Data at address 0x%x\n", GuidHobData));
+  }
+  DEBUG ((EFI_D_INFO, "Support %d U5 application cores on U500 platform\n", 
HartIdNumber - (UINT32)MCSupport));
+
+  if (HartIdNumber != FixedPcdGet32 (PcdHartCount)) {
+DEBUG ((EFI_D_ERROR, "Improper core settings...\n"));
+DEBUG ((EFI_D_ERROR, "PcdHartCount\n"));
+DEBUG ((EFI_D_ERROR, "PcdNumberofU5Cores\n"));
+DEBUG ((EFI_D_ERROR, "PcdE5MCSupported\n\n"));
+ASSERT (FALSE);
+  }
+  return Status;
+}
+
+/**
+  Function to build processor related SMBIOS information. RISC-V SMBIOS DXE 
driver collect
+  this information and build SMBIOS Type4 and Type7 record.
+
+  @param  ProcessorUidUnique ID of pysical processor which owns this core.
+  @param  

[edk2-devel] [PATCH 10/15] [platforms/devel-riscv]: U500Pkg/Library: Library instances of U500 platform library.

[Chen, Gilbert]

OpneSbiPlatformLib
- In order to reduce the dependencies with RISC-V OpenSBI project 
(https://github.com/riscv/opensbi) and less burdens to EDK2 build process, the 
implementation of RISC-V EDK2 platform is leverage platform source code from 
OpenSBI code tree. The "platform.c" under OpenSbiPlatformLib is cloned from 
RISC-V OpenSBI code tree (in EDK2 RiscVPkg) and built based on EDK2 build 
environment.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 .../OpenSbiPlatformLib/OpenSbiPlatformLib.inf  |  53 +
 .../U500Pkg/Library/OpenSbiPlatformLib/platform.c  | 214 +
 2 files changed, 267 insertions(+)
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
 create mode 100644 
Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c

diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
 
b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
new file mode 100644
index 000..1823e48
--- /dev/null
+++ 
b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/OpenSbiPlatformLib.inf
@@ -0,0 +1,53 @@
+## @file
+#  RISC-V OpenSbi Platform Library
+#  This is the the required library which provides platform
+#  level opensbi functions follow RISC-V opensbi implementation.
+#
+#  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD 
License
+#  which accompanies this distribution. The full text of the license may be 
found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR 
IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION= 0x00010005
+  BASE_NAME  = OpenSbiPlatformLib
+  FILE_GUID  = 9424ED54-EBDA-4FB5-8FF6-8291B07BB151
+  MODULE_TYPE= SEC
+  VERSION_STRING = 1.0
+  LIBRARY_CLASS  = OpenSbiPlatformLib
+
+#
+# The following information is for reference only and not required by the 
build tools.
+#
+#  VALID_ARCHITECTURES   = RISCV64 EBC
+#
+
+[Sources]
+  platform.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  RiscVPkg/RiscVPkg.dec
+  Platform/RiscV/RiscVPlatformPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  BaseMemoryLib
+  PcdLib
+  DebugAgentLib
+  RiscVCpuLib
+  PrintLib
+
+[FixedPcd]
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdHartCount
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdOpenSbiStackSize
+  gUefiRiscVPlatformPkgTokenSpaceGuid.PcdBootHartId
diff --git 
a/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c 
b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
new file mode 100644
index 000..887a279
--- /dev/null
+++ b/Platform/RiscV/SiFive/U500Pkg/Library/OpenSbiPlatformLib/platform.c
@@ -0,0 +1,214 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights 
reserved.
+ * Copyright (c) 2019 Western Digital Corporation or its affiliates.
+ *
+ * Authors:
+ *   Atish Patra 
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+
+#define U500_HART_COUNTFixedPcdGet32(PcdHartCount)
+#define U500_HART_STACK_SIZEFixedPcdGet32(PcdOpenSbiStackSize)
+#define U500_BOOT_HART_ID   FixedPcdGet32(PcdBootHartId)
+
+#define U500_SYS_CLK1
+
+#define U500_CLINT_ADDR0x200
+
+#define U500_PLIC_ADDR0xc00
+#define U500_PLIC_NUM_SOURCES0x35
+#define U500_PLIC_NUM_PRIORITIES7
+
+#define U500_UART_ADDR0x5400
+
+#define U500_UART_BAUDRATE115200
+
+/**
+ * The U500 SoC has 8 HARTs but HART ID 0 doesn't have S mode.
+ * HARTs 1 is selected as boot HART
+ */
+#ifndef U500_ENABLED_HART_MASK
+#define U500_ENABLED_HART_MASK(1 << U500_BOOT_HART_ID)
+#endif
+
+#define U500_HARTID_DISABLED~(U500_ENABLED_HART_MASK)
+
+/* PRCI clock related macros */
+//TODO: Do we need a separate driver for this ?
+#define U500_PRCI_BASE_ADDR0x1000
+#define U500_PRCI_CLKMUXSTATUSREG0x002C
+#define U500_PRCI_CLKMUX_STATUS_TLCLKSEL(0x1 << 1)
+
+static void U500_modify_dt(void *fdt)
+{
+u32 i, size;
+int chosen_offset, err;
+int cpu_offset;
+char cpu_node[32] = "";
+const char *mmu_type;
+
+for (i = 0; i < U500_HART_COUNT; i++) {
+sbi_sprintf(cpu_node, "/cpus/cpu@%d", i);
+cpu_offset = fdt_path_offset(fdt, cpu_node);
+mmu_type = fdt_getprop(fdt, cpu_offset, "mmu-type", NULL);
+if (mmu_type && (!strcmp(mmu_type, "riscv,sv39") ||
+!strcmp(mmu_type,"riscv,sv48")))
+continue;
+else
+fdt_setprop_string(fdt, cpu_offset, "status", "masked");
+memset(cpu_node, 0, sizeof(cpu_node));
+}
+size = 

[edk2-devel] [PATCH 15/15] [platforms/devel-riscv]: Platforms: Readme file updates

[Chen, Gilbert]

Update Readme.md and Maintainers.txt for RISV-V platforms.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Maintainers.txt | 9 +
 Readme.md   | 5 +
 2 files changed, 14 insertions(+)

diff --git a/Maintainers.txt b/Maintainers.txt
index 876ae56..c494c9d 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -108,6 +108,11 @@ R: Marcin Wojtas 
 Platform/SolidRun/Armada80x0McBin
 R: Marcin Wojtas 

+Platform/RiscV
+Platform/RiscV/SiFive/U500Pkg
+R: Abner Chang 
+R: Gilbert Chen 
+
 Silicon
 M: Ard Biesheuvel 
 M: Leif Lindholm 
@@ -151,3 +156,7 @@ M: Liming Gao 

 Silicon/Marvell
 R: Marcin Wojtas 
+
+Silicon/SiFive
+R: Abner Chang 
+R: Gilbert Chen 
diff --git a/Readme.md b/Readme.md
index 63e59f6..4572d19 100644
--- a/Readme.md
+++ b/Readme.md
@@ -52,6 +52,7 @@ ARM | arm-linux-gnueabihf-
 IA32| i?86-linux-gnu-* _or_ x86_64-linux-gnu-
 IPF | ia64-linux-gnu
 X64 | x86_64-linux-gnu-
+RISCV64 | riscv64-unknown-elf-

 \* i386, i486, i586 or i686

@@ -243,6 +244,10 @@ For more information, see the
 ## Raspberry Pi
 * [Pi 3](Platform/RaspberryPi/RPi3)

+## RISC-V
+### SiFive
+* [Freedom U500 VC707 FPGA](Platform/RiscV/SiFive/U500Pkg)
+
 ## Socionext
 * [SynQuacer](Platform/Socionext/DeveloperBox)

--
2.7.4


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[edk2-devel] [PATCH 03/15] [platforms/devel-riscv]: platforms/RiscV: Initial version of RISC-V platform package

[Chen, Gilbert]

Initial version of RISC-V platform package which provides the common libraries, 
drivers, PCD and etc. for RISC-V platform development.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Gilbert Chen 
---
 Platform/RiscV/Readme.md |  88 +++
 Platform/RiscV/RiscVPlatformPkg.dec  |  75 ++
 Platform/RiscV/RiscVPlatformPkg.uni  | Bin 0 -> 1754 bytes
 Platform/RiscV/RiscVPlatformPkgExtra.uni | Bin 0 -> 1392 bytes
 4 files changed, 163 insertions(+)
 create mode 100644 Platform/RiscV/Readme.md
 create mode 100644 Platform/RiscV/RiscVPlatformPkg.dec
 create mode 100644 Platform/RiscV/RiscVPlatformPkg.uni
 create mode 100644 Platform/RiscV/RiscVPlatformPkgExtra.uni

diff --git a/Platform/RiscV/Readme.md b/Platform/RiscV/Readme.md
new file mode 100644
index 000..dd817eb
--- /dev/null
+++ b/Platform/RiscV/Readme.md
@@ -0,0 +1,88 @@
+# Introduction
+
+## EDK2 RISC-V Platform Package
+RISC-V platform package provides the generic and common modules for RISC-V 
platforms. RISC-V platform package could include RiscPlatformPkg.dec to use the 
common drivers, libraries, definitions, PCDs and etc. for the platform 
development.
+
+## EDK2 RISC-V Platforms
+RISC-V platform is created and maintained by RISC-V platform vendors. The 
directory of RISC-V platform should be created under Platform/RiscV. Vendor 
should create the folder under Platform/RiscV and name it using vendor name, 
under the vendor folder is the platform folder named by platform model name, 
code name or etc. (e.g. Platform/RiscV/SiFive/U500Pkg)
+
+## Build EDK2 RISC-V Platforms
+RISC-V platform package should provide EDK2 metafiles under RISC-V platform 
package folder (Platform/RiscV/{Vendor}/{Platform}). Build RISC-V platform 
package against edk2 and follow the build guidence mentioned in Readme.md under 
below link.
+https://github.com/tianocore/edk2-platforms
+
+### Download the sources ###
+```
+git clone https://github.com/tianocore/edk2-staging.git
+# Checkout RISC-V branch
+git clone https://github.com/tianocore/edk2-platforms.git
+# Checkout devel-riscv branch
+git clone https://github.com/tianocore/edk2-non-osi.git
+```
+
+### Requirements
+Build EDK2 RISC-V platform requires GCC RISC-V toolchain. Refer to 
https://github.com/riscv/riscv-gnu-toolchain for the details.
+
+### EDK2 project
+Currently, the EDK2 RISC-V platform can only build with edk2 project in 
**edk2-staging/RISC-V** branch. The build architecture whcih is supported and 
verified so far is "RISCV64". The verified RISC-V toolchain is GCC 7.1.1, 
toolchain tag is "GCC711RISCV" declared in tools_def.txt
+
+### Linux Build Instructions
+You can build the RISC-V platform using below script, 
+`build -a RISCV64 -p Platform/{Vendor}/{Platform}/{Platform}.dsc -t 
GCC711RISCV`
+
+Or modify target.txt to set up your build parameters.
+
+## RISC-V Platform PCD settings
+### EDK2 Firmware Volume Settings
+EDK2 Firmware volume related PCDs which declared in platform FDF file.
+
+| **PCD name** |**Usage**|
+||--|
+|PcdRiscVSecFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVSecFvSize| The size of SEC Firmware Volume|
+|PcdRiscVPeiFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVPeiFvSize| The size of SEC Firmware Volume|
+|PcdRiscVDxeFvBase| The base address of SEC Firmware Volume|
+|PcdRiscVDxeFvSize| The size of SEC Firmware Volume|
+
+### EDK2 EFI Variable Region Settings
+The PCD settings regard to EFI Variable
+
+| **PCD name** |**Usage**|
+||--|
+|PcdVariableFdBaseAddress| The EFI variable firmware device base address|
+|PcdVariableFdSize| The EFI variable firmware device size|
+|PcdVariableFdBlockSize| The block size of EFI variable firmware device|
+|PcdPlatformFlashNvStorageVariableBase| EFI variable base address within 
firmware device|
+|PcdPlatformFlashNvStorageFtwWorkingBase| The base address of EFI variable 
fault tolerance worksapce (FTW) within firmware device|
+|PcdPlatformFlashNvStorageFtwSpareBase| The base address of EFI variable spare 
FTW within firmware device|
+
+### RISC-V Physical Memory Protection (PMP) Region Settings
+Below PCDs could be set in platform FDF file.
+
+| **PCD name** |**Usage**|
+||--|
+|PcdFwStartAddress| The starting address of firmware region to protected by 
PMP|
+|PcdFwEndAddress| The ending address of firmware region to protected by PMP|
+
+### RISC-V Processor HART Settings
+
+| **PCD name** |**Usage**|
+||--|
+|PcdHartCount| Number of RISC-V HARTs, the value is processor-implementation 
specific|
+|PcdBootHartId| The ID of RISC-V HART to execute main fimrware code and boot 
system to OS|
+
+### RISC-V OpenSBI Settings
+
+| **PCD name** |**Usage**|
+||--|
+|PcdScratchRamBase| The base address of OpenSBI scratch buffer for all RISC-V 
HARTs|
+|PcdScratchRamSize| The total size of OpenSBI scratch buffer for 

[edk2-devel] [edk2-platforms:PATCH v5] IntelSiliconPkg/Feature Implement SmmAccess

[Marc W Chen]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2121

Implement SmmAccess for PEI and DXE phase in IntelSiliconPkg

Signed-off-by: Marc Chen 
Cc: Ray Ni 
Cc: Rangasai V Chaganty 
---
 .../Library/PeiSmmAccessLib/PeiSmmAccessLib.c  | 339 +
 .../Library/PeiSmmAccessLib/PeiSmmAccessLib.inf|  41 +++
 .../Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf   |  46 +++
 .../SmmAccess/SmmAccessDxe/SmmAccessDriver.c   | 267 
 .../SmmAccess/SmmAccessDxe/SmmAccessDriver.h   | 160 ++
 .../IntelSiliconPkg/Include/Library/SmmAccessLib.h |  28 ++
 6 files changed, 881 insertions(+)
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccessDriver.c
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccessDriver.h
 create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/SmmAccessLib.h

diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
 
b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
new file mode 100644
index 00..da141cfa0e
--- /dev/null
+++ 
b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
@@ -0,0 +1,339 @@
+/** @file
+  This is to publish the SMM Access Ppi instance.
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#define SMM_ACCESS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('4', '5', 's', 'a')
+
+///
+/// Private data
+///
+typedef struct {
+  UINTN Signature;
+  EFI_HANDLEHandle;
+  EFI_PEI_MM_ACCESS_PPI SmmAccess;
+  //
+  // Local Data for SMM Access interface goes here
+  //
+  UINTN NumberRegions;
+  EFI_SMRAM_DESCRIPTOR  *SmramDesc;
+} SMM_ACCESS_PRIVATE_DATA;
+
+#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \
+CR (a, \
+  SMM_ACCESS_PRIVATE_DATA, \
+  SmmAccess, \
+  SMM_ACCESS_PRIVATE_DATA_SIGNATURE \
+  )
+
+/**
+  This routine accepts a request to "open" a region of SMRAM.  The
+  region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
+  The use of "open" means that the memory is visible from all PEIM
+  and SMM agents.
+
+  @param[in] This -  Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex  -  Region of SMRAM to Open.
+  @param[in] PeiServices  -  General purpose services available to every 
PEIM.
+
+  @retval EFI_SUCCESS-  The region was successfully opened.
+  @retval EFI_DEVICE_ERROR   -  The region could not be opened because 
locked by
+chipset.
+  @retval EFI_INVALID_PARAMETER  -  The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Open (
+  IN EFI_PEI_SERVICES   **PeiServices,
+  IN EFI_PEI_MM_ACCESS_PPI  *This,
+  IN UINTN  DescriptorIndex
+  )
+{
+  SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+
+  SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+  if (DescriptorIndex >= SmmAccess->NumberRegions) {
+DEBUG ((DEBUG_WARN, "SMRAM region out of range\n"));
+
+return EFI_INVALID_PARAMETER;
+  } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & 
EFI_SMRAM_LOCKED) {
+//
+// Cannot open a "locked" region
+//
+DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n"));
+
+return EFI_DEVICE_ERROR;
+  }
+
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState &= (UINT64) 
~(EFI_SMRAM_CLOSED | EFI_ALLOCATED);
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINT64) EFI_SMRAM_OPEN;
+  SmmAccess->SmmAccess.OpenState = TRUE;
+  return EFI_SUCCESS;
+}
+
+/**
+  This routine accepts a request to "close" a region of SMRAM.  This is valid 
for
+  compatible SMRAM region.
+
+  @param[in] PeiServices  -  General purpose services available to every 
PEIM.
+  @param[in] This -  Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex  -  Region of SMRAM to Close.
+
+  @retval EFI_SUCCESS-  The region was successfully closed.
+  @retval EFI_DEVICE_ERROR   -  The region could not be closed because 
locked by
+chipset.
+  @retval EFI_INVALID_PARAMETER  -  The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Close (
+  IN EFI_PEI_SERVICES**PeiServices,
+  IN EFI_PEI_MM_ACCESS_PPI   *This,
+  IN UINTN   DescriptorIndex
+  )
+{
+  SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+  BOOLEAN

[edk2-devel] [edk2-platforms:PATCH v4] IntelSiliconPkg/Feature Implement SmmAccess

[Marc W Chen]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2121

Implement SmmAccess for PEI and DXE phase in IntelSiliconPkg

Signed-off-by: Marc Chen 
Cc: Ray Ni 
Cc: Rangasai V Chaganty 
---
 .../Library/PeiSmmAccessLib/PeiSmmAccessLib.c  | 339 +
 .../Library/PeiSmmAccessLib/PeiSmmAccessLib.inf|  41 +++
 .../Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf   |  46 +++
 .../SmmAccess/SmmAccessDxe/SmmAccessDriver.c   | 267 
 .../SmmAccess/SmmAccessDxe/SmmAccessDriver.h   | 160 ++
 .../IntelSiliconPkg/Include/Library/SmmAccessLib.h |  28 ++
 6 files changed, 881 insertions(+)
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccessDriver.c
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccessDriver.h
 create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/SmmAccessLib.h

diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
 
b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
new file mode 100644
index 00..da141cfa0e
--- /dev/null
+++ 
b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
@@ -0,0 +1,339 @@
+/** @file
+  This is to publish the SMM Access Ppi instance.
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#define SMM_ACCESS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('4', '5', 's', 'a')
+
+///
+/// Private data
+///
+typedef struct {
+  UINTN Signature;
+  EFI_HANDLEHandle;
+  EFI_PEI_MM_ACCESS_PPI SmmAccess;
+  //
+  // Local Data for SMM Access interface goes here
+  //
+  UINTN NumberRegions;
+  EFI_SMRAM_DESCRIPTOR  *SmramDesc;
+} SMM_ACCESS_PRIVATE_DATA;
+
+#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \
+CR (a, \
+  SMM_ACCESS_PRIVATE_DATA, \
+  SmmAccess, \
+  SMM_ACCESS_PRIVATE_DATA_SIGNATURE \
+  )
+
+/**
+  This routine accepts a request to "open" a region of SMRAM.  The
+  region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
+  The use of "open" means that the memory is visible from all PEIM
+  and SMM agents.
+
+  @param[in] This -  Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex  -  Region of SMRAM to Open.
+  @param[in] PeiServices  -  General purpose services available to every 
PEIM.
+
+  @retval EFI_SUCCESS-  The region was successfully opened.
+  @retval EFI_DEVICE_ERROR   -  The region could not be opened because 
locked by
+chipset.
+  @retval EFI_INVALID_PARAMETER  -  The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Open (
+  IN EFI_PEI_SERVICES   **PeiServices,
+  IN EFI_PEI_MM_ACCESS_PPI  *This,
+  IN UINTN  DescriptorIndex
+  )
+{
+  SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+
+  SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+  if (DescriptorIndex >= SmmAccess->NumberRegions) {
+DEBUG ((DEBUG_WARN, "SMRAM region out of range\n"));
+
+return EFI_INVALID_PARAMETER;
+  } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & 
EFI_SMRAM_LOCKED) {
+//
+// Cannot open a "locked" region
+//
+DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n"));
+
+return EFI_DEVICE_ERROR;
+  }
+
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState &= (UINT64) 
~(EFI_SMRAM_CLOSED | EFI_ALLOCATED);
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINT64) EFI_SMRAM_OPEN;
+  SmmAccess->SmmAccess.OpenState = TRUE;
+  return EFI_SUCCESS;
+}
+
+/**
+  This routine accepts a request to "close" a region of SMRAM.  This is valid 
for
+  compatible SMRAM region.
+
+  @param[in] PeiServices  -  General purpose services available to every 
PEIM.
+  @param[in] This -  Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex  -  Region of SMRAM to Close.
+
+  @retval EFI_SUCCESS-  The region was successfully closed.
+  @retval EFI_DEVICE_ERROR   -  The region could not be closed because 
locked by
+chipset.
+  @retval EFI_INVALID_PARAMETER  -  The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Close (
+  IN EFI_PEI_SERVICES**PeiServices,
+  IN EFI_PEI_MM_ACCESS_PPI   *This,
+  IN UINTN   DescriptorIndex
+  )
+{
+  SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+  BOOLEAN

[edk2-devel] [edk2-platforms:PATCH v3] IntelSiliconPkg/Feature Implement SmmAccess

[Marc W Chen]

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2121

Implement SmmAccess for PEI and DXE phase in IntelSiliconPkg

Signed-off-by: Marc Chen 
Cc: Ray Ni 
Cc: Rangasai V Chaganty 
---
 .../Library/PeiSmmAccessLib/PeiSmmAccessLib.c  | 343 +
 .../Library/PeiSmmAccessLib/PeiSmmAccessLib.inf|  41 +++
 .../Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf   |  46 +++
 .../SmmAccess/SmmAccessDxe/SmmAccessDriver.c   | 267 
 .../SmmAccess/SmmAccessDxe/SmmAccessDriver.h   | 160 ++
 .../IntelSiliconPkg/Include/Library/SmmAccessLib.h |  32 ++
 6 files changed, 889 insertions(+)
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.inf
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccessDriver.c
 create mode 100644 
Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccessDriver.h
 create mode 100644 Silicon/Intel/IntelSiliconPkg/Include/Library/SmmAccessLib.h

diff --git 
a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
 
b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
new file mode 100644
index 00..cc5bf745d2
--- /dev/null
+++ 
b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/PeiSmmAccessLib.c
@@ -0,0 +1,343 @@
+/** @file
+  This is to publish the SMM Access Ppi instance.
+
+  Copyright (c) 2019, Intel Corporation. All rights reserved.
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#include 
+#include 
+
+#define SMM_ACCESS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('4', '5', 's', 'a')
+
+///
+/// Private data
+///
+typedef struct {
+  UINTN Signature;
+  EFI_HANDLEHandle;
+  EFI_PEI_MM_ACCESS_PPI SmmAccess;
+  //
+  // Local Data for SMM Access interface goes here
+  //
+  UINTN NumberRegions;
+  EFI_SMRAM_DESCRIPTOR  *SmramDesc;
+} SMM_ACCESS_PRIVATE_DATA;
+
+#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \
+CR (a, \
+  SMM_ACCESS_PRIVATE_DATA, \
+  SmmAccess, \
+  SMM_ACCESS_PRIVATE_DATA_SIGNATURE \
+  )
+
+/**
+  This routine accepts a request to "open" a region of SMRAM.  The
+  region could be legacy ABSEG, HSEG, or TSEG near top of physical memory.
+  The use of "open" means that the memory is visible from all PEIM
+  and SMM agents.
+
+  @param[in] This -  Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex  -  Region of SMRAM to Open.
+  @param[in] PeiServices  -  General purpose services available to every 
PEIM.
+
+  @retval EFI_SUCCESS-  The region was successfully opened.
+  @retval EFI_DEVICE_ERROR   -  The region could not be opened because 
locked by
+chipset.
+  @retval EFI_INVALID_PARAMETER  -  The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Open (
+  IN EFI_PEI_SERVICES   **PeiServices,
+  IN EFI_PEI_MM_ACCESS_PPI  *This,
+  IN UINTN  DescriptorIndex
+  )
+{
+  SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+
+  SmmAccess = SMM_ACCESS_PRIVATE_DATA_FROM_THIS (This);
+  if (DescriptorIndex >= SmmAccess->NumberRegions) {
+DEBUG ((DEBUG_WARN, "SMRAM region out of range\n"));
+
+return EFI_INVALID_PARAMETER;
+  } else if (SmmAccess->SmramDesc[DescriptorIndex].RegionState & 
EFI_SMRAM_LOCKED) {
+//
+// Cannot open a "locked" region
+//
+DEBUG ((DEBUG_WARN, "Cannot open a locked SMRAM region\n"));
+
+return EFI_DEVICE_ERROR;
+  }
+
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState &= (UINT64) 
~(EFI_SMRAM_CLOSED | EFI_ALLOCATED);
+  SmmAccess->SmramDesc[DescriptorIndex].RegionState |= (UINT64) EFI_SMRAM_OPEN;
+  SmmAccess->SmmAccess.OpenState = TRUE;
+  return EFI_SUCCESS;
+}
+
+/**
+  This routine accepts a request to "close" a region of SMRAM.  This is valid 
for
+  compatible SMRAM region.
+
+  @param[in] PeiServices  -  General purpose services available to every 
PEIM.
+  @param[in] This -  Pointer to the SMM Access Interface.
+  @param[in] DescriptorIndex  -  Region of SMRAM to Close.
+
+  @retval EFI_SUCCESS-  The region was successfully closed.
+  @retval EFI_DEVICE_ERROR   -  The region could not be closed because 
locked by
+chipset.
+  @retval EFI_INVALID_PARAMETER  -  The descriptor index was out of bounds.
+**/
+EFI_STATUS
+EFIAPI
+Close (
+  IN EFI_PEI_SERVICES**PeiServices,
+  IN EFI_PEI_MM_ACCESS_PPI   *This,
+  IN UINTN   DescriptorIndex
+  )
+{
+  SMM_ACCESS_PRIVATE_DATA *SmmAccess;
+  BOOLEAN

Re: [edk2-devel] [PATCH v2] IntelSiliconPkg/Feature Implement SmmAccess

[Marc W Chen]

Thanks Star for reviewing, it is a typo, let me update it in next patch.

Thanks,
Marc

> -Original Message-
> From: Zeng, Star
> Sent: Tuesday, August 27, 2019 2:22 PM
> To: devel@edk2.groups.io; Chen, Marc W 
> Cc: Ni, Ray ; Chaganty, Rangasai V
> ; Zeng, Star 
> Subject: RE: [edk2-devel] [PATCH v2] IntelSiliconPkg/Feature Implement
> SmmAccess
> 
> Include new library and driver to IntelSiliconPkg.dsc for building coverage?
> In SmmAccessLib.h, it still refers the _PEI_SMM_ACCESS_PPI definition from
> MdeModulePkg? And need have _EFI prefix for
> _PEI_MASTER_BOOT_MODE_PEIM_PPI and
> _PEI_PERMANENT_MEMORY_INSTALLED_PPI?
> In PeiSmmAccessLib.inf, the word 'module' in description " Library
> description file for the SmmAccess module " need to be updated?
> 
> 
> 
> Thanks,
> Star
> 
> > -Original Message-
> > From: devel@edk2.groups.io [mailto:devel@edk2.groups.io] On Behalf Of
> > Marc W Chen
> > Sent: Monday, August 26, 2019 2:14 PM
> > To: devel@edk2.groups.io
> > Cc: Chen, Marc W ; Ni, Ray ;
> > Chaganty, Rangasai V 
> > Subject: [edk2-devel] [PATCH v2] IntelSiliconPkg/Feature Implement
> > SmmAccess
> >
> > REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2121
> >
> > Implement SmmAccess for PEI and DXE phase in IntelSiliconPkg
> >
> > Signed-off-by: Marc Chen 
> > Cc: Ray Ni 
> > Cc: Rangasai V Chaganty 
> > ---
> >  .../Library/PeiSmmAccessLib/PeiSmmAccessLib.c  | 343
> > +
> >  .../Library/PeiSmmAccessLib/PeiSmmAccessLib.inf|  41 +++
> >  .../Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf   |  46 +++
> >  .../SmmAccess/SmmAccessDxe/SmmAccessDriver.c   | 267
> > 
> >  .../SmmAccess/SmmAccessDxe/SmmAccessDriver.h   | 160 ++
> >  .../IntelSiliconPkg/Include/Library/SmmAccessLib.h |  32 ++
> >  6 files changed, 889 insertions(+)
> >  create mode 100644
> >
> Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/
> > PeiSmmAccessLib.c
> >  create mode 100644
> >
> Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/
> > PeiSmmAccessLib.inf
> >  create mode 100644
> > Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAcce
> > ss.inf
> >  create mode 100644
> > Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAcce
> > ssDriver.c
> >  create mode 100644
> > Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAcce
> > ssDriver.h
> >  create mode 100644
> > Silicon/Intel/IntelSiliconPkg/Include/Library/SmmAccessLib.h
> >
> > diff --git
> > a/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLi
> > b/PeiSmmAccessLib.c
> >
> b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLi
> > b/PeiSmmAccessLib.c
> > new file mode 100644
> > index 00..cc5bf745d2
> > --- /dev/null
> > +++
> > b/Silicon/Intel/IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAcce
> > +++ ssLib/PeiSmmAccessLib.c
> > @@ -0,0 +1,343 @@
> > +/** @file
> > +  This is to publish the SMM Access Ppi instance.
> > +
> > +  Copyright (c) 2019, Intel Corporation. All rights reserved.
> > +  SPDX-License-Identifier: BSD-2-Clause-Patent
> > +
> > +**/
> > +#include 
> > +#include 
> > +#include  #include
> > + #include  #include
> > + #include  #include
> > +
> > +
> > +#include 
> > +#include 
> > +
> > +#define SMM_ACCESS_PRIVATE_DATA_SIGNATURE SIGNATURE_32 ('4', '5',
> > 's',
> > +'a')
> > +
> > +///
> > +/// Private data
> > +///
> > +typedef struct {
> > +  UINTN Signature;
> > +  EFI_HANDLEHandle;
> > +  EFI_PEI_MM_ACCESS_PPI SmmAccess;
> > +  //
> > +  // Local Data for SMM Access interface goes here
> > +  //
> > +  UINTN NumberRegions;
> > +  EFI_SMRAM_DESCRIPTOR  *SmramDesc;
> > +} SMM_ACCESS_PRIVATE_DATA;
> > +
> > +#define SMM_ACCESS_PRIVATE_DATA_FROM_THIS(a) \
> > +CR (a, \
> > +  SMM_ACCESS_PRIVATE_DATA, \
> > +  SmmAccess, \
> > +  SMM_ACCESS_PRIVATE_DATA_SIGNATURE \
> > +  )
> > +
> > +/**
> > +  This routine accepts a request to "open" a region of SMRAM.  The
> > +  region could be legacy ABSEG, HSEG, or TSEG near top of physical
> memory.
> > +  The use of "open" means that the memory is visible from all PEIM
> > +  and SMM agents.
> > +
> > +  @param[in] This -  Pointer to the SMM Access Interface.
> > +  @param[in] DescriptorIndex  -  Region of SMRAM to Open.
> > +  @param[in] PeiServices  -  General purpose services available to 
> > every
> > PEIM.
> > +
> > +  @retval EFI_SUCCESS-  The region was successfully opened.
> > +  @retval EFI_DEVICE_ERROR   -  The region could not be opened
> because
> > locked by
> > +chipset.
> > +  @retval EFI_INVALID_PARAMETER  -  The descriptor index was out of
> > bounds.
> > +**/
> > +EFI_STATUS
> > +EFIAPI
> > +Open (
> > +  IN EFI_PEI_SERVICES   **PeiServices,
> > +  IN EFI_PEI_MM_ACCESS_PPI  *This,
> > +  IN UINTN