: Re: [Discuss-gnuradio] Costas loop and MM algorithm on FPGA
At high SNR, a single bit is probably enough in the detector and 15 bits in
the phase accumulator is also likely more than enough. The error, in my
opinion, is elsewhere.
Tell us about your work here please:
https://www.cgran.org
; usrp-us...@lists.ettus.com
*Subject:* Re: [Discuss-gnuradio] Costas loop and MM algorithm on FPGA***
*
** **
At high SNR, a single bit is probably enough in the detector and 15 bits
in the phase accumulator is also likely more than enough. The error, in my
opinion, is elsewhere
Hello Phone
Do you have a git repo that one might throw in ones two coppers?
Best
Paul
2011/12/15 Phone Naing MYINT phonenaing.my...@sg.panasonic.com
Hi,
Anyone here implemented freq/phase correction and symbol timing correction
in USRP's FPGA?
Recently I implemented Costas loop and
To: GNURadio Discussion List
Subject: Re: [Discuss-gnuradio] Costas loop and MM algorithm on FPGA
Hello Phone
Do you have a git repo that one might throw in ones two coppers?
Best
Paul
2011/12/15 Phone Naing MYINT
phonenaing.my...@sg.panasonic.commailto:phonenaing.my...@sg.panasonic.com
Hi,
Anyone here
M. Bendixen
*Sent:* Thursday, December 15, 2011 4:48 PM
*To:* GNURadio Discussion List
*Subject:* Re: [Discuss-gnuradio] Costas loop and MM algorithm on FPGA
Hello Phone
Do you have a git repo that one might throw in ones two coppers?
Best
Paul
2011/12/15 Phone Naing MYINT
At high SNR, a single bit is probably enough in the detector and 15 bits
in the phase accumulator is also likely more than enough. The error, in my
opinion, is elsewhere.
Tell us about your work here please:
https://www.cgran.org/
after you have set up your git repository here:
] Costas loop and MM algorithm on FPGA
At high SNR, a single bit is probably enough in the detector and 15 bits in
the phase accumulator is also likely more than enough. The error, in my
opinion, is elsewhere.
Tell us about your work here please:
https://www.cgran.org/
after you have set up your
Hi,
Anyone here implemented freq/phase correction and symbol timing correction in
USRP's FPGA?
Recently I implemented Costas loop and Muller Mueller algorithm in RTL by
referring the gnuradio code. Now I'm testing it on FPGA. I can get correct
demodulated data(DQPSK) at initial few thousand