On Tue, 24 Dec 2019 15:38:51 +0100, Miquel Raynal wrote:
> PX30 SoCs use a single PHY shared by two display pipelines: MIPI DSI
> and LVDS. In the case of the LVDS IP, document the possibility to fill
> a PHY handle.
>
> Signed-off-by: Miquel Raynal
> ---
>
On Mon, Dec 23, 2019 at 04:16:40PM +0100, Yuti Amonkar wrote:
> Document the bindings used for the Cadence MHDP DPI/DP bridge in
> yaml format.
>
> Signed-off-by: Yuti Amonkar
> ---
> .../bindings/display/bridge/cdns,mhdp.yaml | 109
> +
> 1 file changed, 109
Hi Harigovindan.
Thanks for re-submitting this driver.
There is several more or less trivial comments below.
Please fix and send a v3.
Thanks,
Sam
On Fri, Nov 29, 2019 at 12:25:45PM +0530, Harigovindan P wrote:
> Add support for Visionox panel driver.
>
> Changes in v1:
> -Split
Hi Paul.
Good looking driver. Well structured in a number of relevant files.
A few comments in the following.
Some parts I fail to follow - due to my lack of DRM knowledge.
So all in all - only trivial comments.
With these fixed you can add:
Acked-by: Sam Ravnborg
Sam
On Tue, Dec 03,
Hi Linus.
Driver looks good.
Rahter complicated - but that what the controller/panel requires.
Lot's of good code comments - very nice.
A few comments in the following.
Sam
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e6db3889cb19..1372b4139ebd 100644
> --- a/MAINTAINERS
> +++
Hi Linus
On Sat, Jan 04, 2020 at 06:27:17PM +0100, Sam Ravnborg wrote:
> Hi Linus.
>
> On Wed, Dec 25, 2019 at 12:56:09PM +0100, Linus Walleij wrote:
> > This adds device tree bindings for the Novatek NT35510-based
> > family of panels. Since several such panels are in existence
> > we define
Hi Linus.
On Wed, Dec 25, 2019 at 12:56:09PM +0100, Linus Walleij wrote:
> This adds device tree bindings for the Novatek NT35510-based
> family of panels. Since several such panels are in existence
> we define bindings common for all, and define the compatible
> string for one certain panel
Hi Claudiu
On Thu, Jan 02, 2020 at 10:08:48AM +0100, Sam Ravnborg wrote:
> On Wed, Dec 18, 2019 at 02:28:28PM +0200, Claudiu Beznea wrote:
> > From: Peter Rosin
> >
> > The intention was to only select a higher pixel-clock rate than the
> > requested, if a slight overclocking would result in a
On Tue, Dec 24, 2019 at 12:26:41PM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner
>
> The LTK500HD1829 is 5.5" DSI display.
>
> changes in v4:
> - drop error message if backlight not found, no other panel
> does that and if needed it should live in drm_panel_of_backlight
> changes in v3:
On Tue, Dec 24, 2019 at 12:26:40PM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner
>
> The LTK500HD1829 is a 5.0" 720x1280 DSI display.
>
> changes in v2:
> - fix id (Maxime)
> - drop port (Maxime)
>
> Signed-off-by: Heiko Stuebner
> Acked-by: Maxime Ripard
Applied to drm-misc-next.
On Tue, Dec 24, 2019 at 12:26:39PM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner
>
> Shenzhen Leadtek Technology Co., Ltd. produces for example display
> and touch panels.
>
> Signed-off-by: Heiko Stuebner
Applied to drm-misc-next.
Sam
Hi Heiko.
Thanks for your work on this.
On Tue, Dec 24, 2019 at 12:29:05PM +0100, Heiko Stuebner wrote:
> From: Heiko Stuebner
>
> Shenzhen Xinpeng Technology Co., Ltd produces for example display panels.
>
> Signed-off-by: Heiko Stuebner
> Acked-by: Sam Ravnborg
> Acked-by: Rob Herring
Fix up inconsistent usage of upper and lowercase letters in "Exynos"
name.
"EXYNOS" is not an abbreviation but a regular trademarked name.
Therefore it should be written with lowercase letters starting with
capital letter.
The lowercase "Exynos" name is promoted by its manufacturer Samsung
Fix up inconsistent usage of upper and lowercase letters in "Exynos"
name.
"EXYNOS" is not an abbreviation but a regular trademarked name.
Therefore it should be written with lowercase letters starting with
capital letter.
The lowercase "Exynos" name is promoted by its manufacturer Samsung
Hi all,
Changes since v1:
=
1. Split bindings to separate patch (1/20). Bindings were previously in
media (7/20) and phy (10/20).
Description
===
The "Samsung" and "Exynos" names are written inconsistently in Linux
kernel sources. Sometimes all uppercase (as SAMSUNG),
Hi Miquel.
On Tue, Dec 24, 2019 at 03:19:05PM +0100, Miquel Raynal wrote:
> Add support for the Satoz SAT050AT40H12R2 RGB panel.
>
> Signed-off-by: Miquel Raynal
> ---
>
> Changes since v2:
> * Dropped two uneeded lines which would fail the build.
>
> Changes since v1:
> * Switched to
Hi Jagan.
On Wed, Jan 01, 2020 at 04:54:38PM +0530, Jagan Teki wrote:
> These panel bindings are owned by me, so updated all of them into
> YAML DT schema.
>
> Any inputs?
Thanks for doing the conversion.
dt_binding_check was not happy:
On Fri, Jan 03, 2020 at 02:25:41PM -0700, Rob Herring wrote:
> On Fri, Jan 3, 2020 at 10:11 AM Krzysztof Kozlowski wrote:
> >
> > Hi all,
> >
> > The "Samsung" and "Exynos" names are written inconsistently in Linux
> > kernel sources. Sometimes all uppercase (as SAMSUNG), sometimes
> > lowercase
Hi,
On Thu, Jan 02, 2020 at 10:04:40PM +0530, Jagan Teki wrote:
> On Thu, Jan 2, 2020 at 9:17 PM Maxime Ripard wrote:
> >
> > On Thu, Jan 02, 2020 at 09:10:31PM +0530, Jagan Teki wrote:
> > > On Thu, Jan 2, 2020 at 4:24 PM Maxime Ripard wrote:
> > > >
> > > > On Tue, Dec 31, 2019 at 06:35:21PM
Hi Linus.
On Sat, Jan 04, 2020 at 01:10:26AM +0100, Linus Walleij wrote:
> The Sony ACX424AKP is a command/videomode DSI panel for
> mobile devices. It is used on the ST-Ericsson HREF520
> reference design. We support video mode by default, but
> it is possible to switch the panel into command
Ma Feng (3):
drm/i915: use true,false for bool variable in i915_debugfs.c
drm/i915/dp: use true,false for bool variable in intel_dp.c
drm/i915: use true,false for bool variable in intel_crt.c
drivers/gpu/drm/i915/display/intel_crt.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dp.c |
чт, 2 янв. 2020 г., 09:42 Jernej Škrabec :
>
> Hi!
>
> Dne sreda, 01. januar 2020 ob 21:47:50 CET je
> roman.stratiie...@globallogic.com napisal(a):
> > From: Roman Stratiienko
> >
> > According to DRM documentation the only difference between PRIMARY
> > and OVERLAY plane is that each CRTC must
On Fri, Jan 03, 2020 at 11:30:12PM +0800, Chen-Yu Tsai wrote:
> On Fri, Jan 3, 2020 at 11:28 PM Maxime Ripard wrote:
> >
> > The MIPI PLL is used for LVDS. Make sure it's exported in the dt bindings
> > headers.
> >
> > Signed-off-by: Maxime Ripard
>
> Acked-by: Chen-Yu Tsai
Applied, thanks!
This series are based on 5.5-rc1 and provid 17 patch
to support mediatek SOC MT8183
Change since v5
- fix reviewed issue in v5
base https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219
Change since v4
- fix reviewed issue in v4
Change since v3
- fix reviewed issue in v3
- fix
* Matthijs van Duin [200104 04:53]:
> On Fri, Dec 20, 2019 at 04:57:11PM -0800, Tony Lindgren wrote:
> > On my droid4 I noticed bad constant tearing on the LCD with stellarium in
> > landscape mode with xorg-video-omap rotated with xrandr --rotate right.
> > Every second or so update gets
On Fri, Jan 03, 2020 at 11:30:35PM +0800, Chen-Yu Tsai wrote:
> On Fri, Jan 3, 2020 at 11:28 PM Maxime Ripard wrote:
> >
> > The MIPI PLL is used for LVDS. Make sure it's exported in the dt bindings
> > headers.
> >
> > Signed-off-by: Maxime Ripard
>
> Acked-by: Chen-Yu Tsai
Applied, thanks!
On Thu, Jan 02, 2020 at 10:12:10AM -0700, Rob Herring wrote:
> On Thu, Jan 2, 2020 at 8:26 AM Maxime Ripard wrote:
> >
> > The Allwinner SoCs have a display engine composed of several controllers
> > assembled differently depending on the SoC, the number and type of output
> > they have, and the
this patch add add connection from OVL_2L0 to RDMA0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
This patch move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel
rdma only has single output, but no multi output,
all these rdma->dsi/dpi usecase should move to mtk_ddp_sout_sel
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 90
This patch add connection from OVL_2L1 to RDMA1
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index
чт, 2 янв. 2020 г., 12:08 Maxime Ripard :
>
> Hi,
>
> On Wed, Jan 01, 2020 at 10:47:50PM +0200, roman.stratiie...@globallogic.com
> wrote:
> > From: Roman Stratiienko
> >
> > According to DRM documentation the only difference between PRIMARY
> > and OVERLAY plane is that each CRTC must have
because the hardware limitation,The initial color depth must set to 32bpp
and must set the FB Offset of the display hardware to 128Byte alignment,
which is used to solve the display problem at 800x600 and 1440x900
resolution under 16bpp.
Signed-off-by: Tian Tao
Signed-off-by: Gong junjie
---
This patch add connection from DITHER0 to DSI0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index
The Allwinner SoCs have a display engine composed of several controllers
assembled differently depending on the SoC, the number and type of output
they have, and the additional features they provide. A number of those are
supported in Linux, with the matching bindings.
Now that we have the DT
The maximum resolution supported by hibmc is 1920 * 1200 instead of
1920 * 1440, this patch fixed this problem
Signed-off-by: Tian Tao
Signed-off-by: Gong junjie
---
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
This patch add support for mediatek SOC MT8183
1.ovl_2l share driver with ovl
2.rdma1 share drive with rdma0, but fifo size is different
3.add mt8183 mutex private data, and mmsys private data
4.add mt8183 main and external path module for crtc create
Signed-off-by: Yongqiang Niu
---
Fix indentation in the Makefile by replacing spaces with tabs.
Signed-off-by: Fabien Parent
---
drivers/gpu/drm/mediatek/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/Makefile
b/drivers/gpu/drm/mediatek/Makefile
index
This patch add connection from OVL0 to OVL_2L0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index
list_for_each() can be replaced by the more concise
list_for_each_entry() here for iteration over the lists.
This change was reported by coccinelle.
Signed-off-by: Wambui Karuga
---
.../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 19 ---
1 file changed, 4 insertions(+), 15
there will be more sout case in the future,
make the sout function format same mtk_ddp_sel_in
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git
The MIPI PLL is used for LVDS. Make sure it's exported in the dt bindings
headers.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi-ng/ccu-sun8i-a23-a33.h | 4 +++-
include/dt-bindings/clock/sun8i-a23-a33-ccu.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git
The Allwinner SoCs have a display engine composed of several controllers
assembled differently depending on the SoC, the number and type of output
they have, and the additional features they provide. A number of those are
supported in Linux, with the matching bindings.
Now that we have the DT
Hi!
Dne četrtek, 02. januar 2020 ob 17:32:07 CET je Roman Stratiienko napisal(a):
> чт, 2 янв. 2020 г., 12:08 Maxime Ripard :
> > Hi,
> >
> > On Wed, Jan 01, 2020 at 10:47:50PM +0200,
roman.stratiie...@globallogic.com wrote:
> > > From: Roman Stratiienko
> > >
> > > According to DRM
Remove unnecessary variable comparisions to true/false in if statements
and check the value of the variable directly.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/radeon/cik_sdma.c | 2 +-
drivers/gpu/drm/radeon/r100.c | 2 +-
drivers/gpu/drm/radeon/r600.c
the register offset and value will be different in future SOC,
add private data for rdma1->dsi0 use case.
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
Some old SoCs, while supporting LVDS, don't list the LVDS clocks and reset
lines. Let's add them when relevant.
Signed-off-by: Maxime Ripard
---
arch/arm/boot/dts/sun6i-a31.dtsi | 23 +++
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 12
the register offset and value will be different in future SOC,
add private data for rdma1->dpi0 use case.
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git
The MIPI PLL is used for LVDS. Make sure it's exported in the dt bindings
headers.
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi-ng/ccu-sun6i-a31.h | 4 +++-
include/dt-bindings/clock/sun6i-a31-ccu.h | 2 ++
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git
Update device tree binding documention for rdma_fifo_size
Signed-off-by: Yongqiang Niu
---
.../devicetree/bindings/display/mediatek/mediatek,disp.txt | 13 +
1 file changed, 13 insertions(+)
diff --git
a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
move dsi/dpi select input into mtk_ddp_sel_in
DPI_SEL_IN_BLS is zero, it is same with hardware default setting,
DISP_REG_CONFIG_DPI_SEL no need set when bls connect with
dpi0
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 7 +++
1 file changed, 3 insertions(+), 4
the fifo size of rdma in mt8183 is different.
rdma0 fifo size is 5k
rdma1 fifo size is 2k
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
This patch add display nodes for mt8183
Signed-off-by: Yongqiang Niu
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 98
1 file changed, 98 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index
On Fri, Jan 03, 2020 at 11:31:05PM +0800, Chen-Yu Tsai wrote:
> On Fri, Jan 3, 2020 at 11:28 PM Maxime Ripard wrote:
> >
> > Some old SoCs, while supporting LVDS, don't list the LVDS clocks and reset
> > lines. Let's add them when relevant.
> >
> > Signed-off-by: Maxime Ripard
>
> Acked-by:
From: Roman Stratiienko
DE2.0 and DE3.0 UI layers supports plane-global alpha channel.
Add alpha property to the DRM plane and connect it to the
corresponding registers in mixer.
Signed-off-by: Roman Stratiienko
Reviewed-by: Jernej Skrabec
---
v2: Initial commit by mistake
v3:
- Picked
* Matthijs van Duin [200104 05:10]:
> On Sat, Dec 21, 2019 at 08:41:41AM -0800, Tony Lindgren wrote:
> > Also, I'm wondering if this change makes sense alone without the pinning
> > changes for a fix, or if also the pinning changes are needed.
>
> Both pinning and page-alignment are done just to
This patch add mmsys private data for ddp path config
all these register offset and value will be different in future SOC
add these define into mmsys private data
u32 ovl0_mout_en;
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 4
On Thu 02 Jan 00:55 PST 2020, Sam Ravnborg wrote:
> Hi Bjorn.
>
> On Sat, Dec 28, 2019 at 10:06:58PM -0800, Bjorn Andersson wrote:
> > The InfoVision Optoelectronics M133NWF4 R0 panel is a 13.3" 1920x1080
> > eDP panel, add support for it in panel-simple.
> >
> > Signed-off-by: Bjorn Andersson
Fixes coccicheck warning:
drivers/gpu/drm/i915/display/intel_crt.c:1066:1-28: WARNING: Assignment of 0/1
to bool variable
drivers/gpu/drm/i915/display/intel_crt.c:928:2-29: WARNING: Assignment of 0/1
to bool variable
drivers/gpu/drm/i915/display/intel_crt.c:443:2-29: WARNING: Assignment of 0/1
This patch add connection from RDMA1 to DSI0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index
This patch add connection from RDMA0 to COLOR0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index
Fixes coccicheck warning:
drivers/gpu/drm/i915/i915_debugfs.c:3078:4-36: WARNING: Assignment of 0/1 to
bool variable
drivers/gpu/drm/i915/i915_debugfs.c:3078:4-36: WARNING: Assignment of 0/1 to
bool variable
drivers/gpu/drm/i915/i915_debugfs.c:3080:4-36: WARNING: Assignment of 0/1 to
bool
Fixes coccicheck warning:
drivers/gpu/drm/i915/display/intel_dp.c:4950:1-33: WARNING: Assignment of 0/1
to bool variable
drivers/gpu/drm/i915/display/intel_dp.c:4906:1-33: WARNING: Assignment of 0/1
to bool variable
Reported-by: Hulk Robot
Signed-off-by: Ma Feng
---
Hi, I think there has a incorrect kfree in pcirom_init function. In
pcirom_init function priv porinter could be free only when priv != null
and priv->rom is null.
Signed-off-by: wuxu.wu
---
drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.c | 3 ++-
1 file changed, 2 insertions(+), 1
From: Roman Stratiienko
DE3.0 VI layers supports plane-global alpha channel.
DE2.0 FCC block have GLOBAL_ALPHA register that can be used as alpha source
for blender.
Add alpha property to the DRM plane and connect it to the
corresponding registers in the mixer.
Do not add alpha property for
On Sat, Dec 21, 2019 at 08:41:41AM -0800, Tony Lindgren wrote:
> Also, I'm wondering if this change makes sense alone without the pinning
> changes for a fix, or if also the pinning changes are needed.
Both pinning and page-alignment are done just to support the direct
userspace mapping. By
Hi Robin,
On Wed, Jan 1, 2020 at 1:55 PM Robin Murphy wrote:
>
> On 2019-12-31 4:47 pm, Martin Blumenstingl wrote:
> > Hi Robin,
> >
> > On Tue, Dec 31, 2019 at 5:40 PM Robin Murphy wrote:
> >>
> >> On 2019-12-31 2:17 pm, Martin Blumenstingl wrote:
> >>> Hi Robin,
> >>>
> >>> On Mon, Dec 30,
This patch add connection from RDMA0 to DSI0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index
On Fri, Dec 20, 2019 at 04:57:11PM -0800, Tony Lindgren wrote:
> On my droid4 I noticed bad constant tearing on the LCD with stellarium in
> landscape mode with xorg-video-omap rotated with xrandr --rotate right.
> Every second or so update gets squeezed down in size to only the top half
> of the
As single statement conditionals do not need to be wrapped around
braces, the unnecessary braces can be removed.
Signed-off-by: Wambui Karuga
---
drivers/gpu/drm/radeon/atombios_crtc.c | 3 +--
drivers/gpu/drm/radeon/atombios_dp.c | 3 +--
drivers/gpu/drm/radeon/atombios_encoders.c
Explicitly declare constants as unsigned long long to address the
following sparse warnings:
warning: constant is so big it is long
v2: convert to unsigned long long for compatibility with 32-bit
architectures.
Signed-off-by: Wambui Karuga
Suggested by: lia Mirkin
---
https://bugzilla.kernel.org/show_bug.cgi?id=204849
--- Comment #3 from Justin Clift (jus...@postgresql.org) ---
As an extra data point with this, the error in my case only happens when I have
an external monitor plugged in via the HDMI port.
This is on a laptop, with the error not showing up if
On Sat, 04 Jan 2020 00:01:14 +0100,
Lyude Paul wrote:
>
> Got shown this patch at work and realized it still needed review, so I went
> ahead and did that :)
>
> Reviewed-by: Lyude Paul
Thanks!
Let me know if the submission of the patch is needed.
Takashi
>
> On Mon, 2019-07-22 at 16:38
72 matches
Mail list logo
