Rework and simplify the locking with GuC subission. Drop
sched_state_no_lock and move all fields under the guc_state.sched_state
and protect all these fields with guc_state.lock . This requires
changing the locking hierarchy from guc_state.lock -> sched_engine.lock
to sched_engine.lock -> guc_state
s/static inline/static/g + fix function argument alignment to make
checkpatch happy.
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 116 +-
1 file changed, 57 insertions(+), 59 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submi
Drop pin count check trick between a sched_disable and re-pin, now rely
on the lock and counter of the number of committed requests to determine
if scheduling should be disabled on the context.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 2 +
.../gpu/drm/i91
Lock the xarray and take ref to the context if needed.
v2:
(Checkpatch)
- Add new line after declaration
(Daniel Vetter)
- Correct put / get accounting in xa_for_loops
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 103 +++---
1 file changed,
Now that we have locking hierarchy of sched_engine->lock ->
ce->guc_state everything from guc_active can be moved into guc_state and
protected the guc_state.lock.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c | 10 +--
drivers/gpu/drm/i915/gt/intel_context_types.
Add GuC kernel doc for all structures added thus far for GuC submission
and update the main GuC submission section with the new interface
details.
v2:
- Drop guc_active.lock DOC
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context_types.h | 44 ++---
drivers/gpu/drm/i915/
GuC submission has exposed an existing memory corruption in
live_lrc_isolation. We believe that some writes to the watchdog offsets
in the LRC (0x178 & 0x17c) can result in trashing of portions of the
address space. With GuC submission there are additional objects which
can move the context redzone
It isn't safe to scrub for missing G2H or continue with the reset until
all G2H processing is complete. Flush the G2H work queue during reset to
ensure it is done running.
Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementation for new GuC interface")
Signed-off-by: Matthew Brost
---
.../gpu/dr
Move GuC management fields in context under guc_active struct as this is
where the lock that protects theses fields lives. Also only set guc_prio
field once during context init.
Fixes: ee242ca704d3 ("drm/i915/guc: Implement GuC priority management")
Signed-off-by: Matthew Brost
Cc:
---
drivers/
Move guc_blocked fence to struct guc_state as the lock which protects
the fence lives there.
s/ce->guc_blocked/ce->guc_state.blocked_fence/g
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c| 5 +++--
drivers/gpu/drm/i915/gt/intel_context_types.h | 5 ++---
...
To make ownership of locking clear move fields (guc_id, guc_id_ref,
guc_id_link) to sub structure guc_id in intel_context.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/intel_context.c | 4 +-
drivers/gpu/drm/i915/gt/intel_context_types.h | 18 +--
drivers/gpu/drm/i915/gt/sel
Before we did some clever tricks to not use the a lock when touching
guc_state.sched_state in certain cases. Don't do that, enforce the use
of the lock.
Part of this is removing a dead code path from guc_lrc_desc_pin where a
context could be deregistered when the aforementioned function was
called
A subsequent patch will flip the locking hierarchy from
ce->guc_state.lock -> sched_engine->lock to sched_engine->lock ->
ce->guc_state.lock. As such we need to release the submit fence for a
request from an IRQ to break a lock inversion - i.e. the fence must be
release went holding ce->guc_state.l
Propagating errors to dependent fences is wrong, don't do it. A selftest
in the following exposed the propagating of an error to a dependent
fence after an engine reset.
This reverts commit 8e9f84cf5cac248a1c6a5daa4942879c8b765058.
v2:
(Daniel Vetter)
- Use revert
References: 3761baae908a (Re
Daniel Vetter pointed out that locking in the GuC submission code was
overly complicated, let's clean this up a bit before introducing more
features in the GuC submission backend.
Also fix some CI failures, port fixes from our internal tree, and add a
few more selftests for coverage.
Lastly, add
A context can get destroyed after cancelling a request so take a
reference to context when cancelling a request.
Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 5 -
1 file changed, 4 inse
If the context is reset as a result of the request cancelation the
context reset G2H is received after schedule disable done G2H which is
likely the wrong order. The schedule disable done G2H release the
waiting request cancelation code which resubmits the context. This races
with the context reset
Error captures can now be done in a work queue processing G2H messages.
These messages need to be completely done being processed in the reset
path, to avoid races in the missing G2H cleanup, which create a
dependency on memory allocations and dma fences (i915_requests).
Requests depend on resets,
Add a cancel request selftest that results in an engine reset to cancel
the request as it is non-preemptable. Also insert a NOP request after
the cancelled request and confirm that it completely successfully.
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/selftests/i915_request.c | 100 ++
When unblocking a context, do not enable scheduling if the context is
banned, guc_id invalid, or not registered.
Fixes: 62eaf0ae217d ("drm/i915/guc: Support request cancellation")
Signed-off-by: Matthew Brost
Cc:
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 3 +++
1 file changed, 3 i
Kick tasklet after queuing a request so it submitted in a timely manner.
Fixes: 3a4cdf1982f0 ("drm/i915/guc: Implement GuC context operations for new
inteface")
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 1 +
1 file changed, 1 insertion(+)
diff --git a
Reset LRC descriptor if a context register returns -ENODEV as this means
we are mid-reset.
Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementation for new GuC interface")
Signed-off-by: Matthew Brost
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 --
1 file changed, 4 insertions(
A small race that could result in incorrect accounting of the number
of outstanding G2H. Basically prior to this patch we did not increment
the number of outstanding G2H if we encoutered a GT reset while sending
a H2G. This was incorrect as the context state had already been updated
to anticipate a
While debugging an issue with full GT resets I went down a rabbit hole
thinking the scrubbing of lost G2H wasn't working correctly. This proved
to be incorrect as this was working just fine but this chase inspired me
to write a selftest to prove that this works. This simple selftest
injects errors
Rather than processing 1 G2H at a time and re-queuing the work queue if
more messages exist, process all the G2H in a single pass of the work
queue.
Signed-off-by: Matthew Brost
Cc: Daniel Vetter
Cc: Michal Wajdeczko
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ct.c | 6 +++---
1 file changed, 3 i
Prior to this patch the blocked context counter was cleared on
init_sched_state (used during registering a context & resets) which is
incorrect. This state needs to be persistent or the counter can read the
incorrect value resulting in scheduling never getting enabled again.
Fixes: 62eaf0ae217d ("
Don't drop ce->guc_active.lock when unwinding a context after reset.
At one point we had to drop this because of a lock inversion but that is
no longer the case. It is much safer to hold the lock so let's do that.
Fixes: eb5e7da736f3 ("drm/i915/guc: Reset implementation for new GuC interface")
Sig
When unwinding requests on a reset context, if other requests in the
context are in the priority list the requests could be resubmitted out
of seqno order. Traverse the list of active requests in reverse and
append to the head of the priority list to fix this.
Fixes: eb5e7da736f3 ("drm/i915/guc: R
On 18-08-21, 18:55, Dmitry Osipenko wrote:
> 18.08.2021 12:41, Ulf Hansson пишет:
>
> Either way gives the equal result. The new callback allows to remove the
> boilerplate dev_pm_opp_set_rate(clk_get_rate() code from the rpm-resume
> of consumer devices, that's it.
It may not be equal, as dev_pm
Enable DSI EOTP feature for fixing some panel screen constant shift issue.
Removing MIPI flag MIPI_DSI_MODE_NO_EOT_PACKET to enable DSI EOTP.
Reviewed-by: Robert Foss
Signed-off-by: Xin Ji
---
drivers/gpu/drm/bridge/analogix/anx7625.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/g
On 19/8/21 12:33 am, Daniel Vetter wrote:
On Wed, Aug 18, 2021 at 5:37 PM Desmond Cheong Zhi Xi
wrote:
On 18/8/21 6:11 pm, Daniel Vetter wrote:
On Wed, Aug 18, 2021 at 03:38:19PM +0800, Desmond Cheong Zhi Xi wrote:
There are three areas where we dereference struct drm_master without
checking
On 8/19/2021 5:29 AM, Kees Cook wrote:
On Wed, Aug 18, 2021 at 05:12:28PM +0530, Lazar, Lijo wrote:
On 8/18/2021 11:34 AM, Kees Cook wrote:
In preparation for FORTIFY_SOURCE performing compile-time and run-time
field bounds checking for memcpy(), memmove(), and memset(), avoid
intentionally
[AMD Official Use Only]
Hi Andrey and Daniel
We worked for a really long time on this new feature to AMD that finally can
pick up the bad job from all timedout ones, and the change in scheduler
(get/put fence in drm_sched_job_timedout, and remove the bad job delete and put
back) is the last pi
1. Add mt8195 SoC binding to AAL, CCORR, COLOR, DITHER, GAMMA, MERGE,
MUTEX, OVL and RDMA yaml schema.
2. Add MERGE additional property description for mt8195
- async clock
- fifo setting enable
- reset controller
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,aal.yaml
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
vi
1. Remove mediatek,dislpay.txt
2. Split each display function block to individual yaml file.
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,aal.yaml| 75 ++
.../display/mediatek/mediatek,ccorr.yaml | 69 ++
.../display/mediatek/mediatek,color.yaml | 84
Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 268
Adjust to the alphabetic order for the define, function, struct
and array in mediatek-drm driver
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 133 ++--
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 22 ++--
drivers/gpu/drm/mediatek/mtk_drm_drv.c
Add display node for vdosys0.
Signed-off-by: jason-jh.lin
---
This patch is based on [1][2][3]
[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
-
https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.w...@mediatek.com/
[2]arm64: dts:
Add DISP_REG prefix for the define of register offset to
make the difference from the define of register value.
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 57 +++--
1 file changed, 29 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/
Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: jason-jh.lin
---
This patch is base on [1][2]
[1] soc: mediatek: mmsys: add MT8365 support
-
https://patchwork.kernel.org/project/linux-mediatek/patch/20210519161847.3747352-3-fpar...@baylibre.
Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
Signed-off-by: jason-jh.lin
Reviewed-by: Chun-Kuang Hu
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 28
2 files changed, 34 insertions(+)
diff -
Change in v8:
- add DP_INTF0 mux into mmsys routing table
- add DP_INTF0 mutex mod and enum into add/remove comp funtion
- remove bypass DSC enum in mtk_ddp_comp_init
Change in v7:
- add dt=binding of mmsys and disp path into this series
- separate th modidfication of alphabetic order, remove unus
Remove the unsed define in mtk_drm_ddp_comp.c
Signed-off-by: jason-jh.lin
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 75bc00e17fc4..
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin
---
drivers/soc/mediatek/mtk-mutex.c | 98 +++-
1 file changed, 95 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576.
1. There are 2 mmsys, namely vdosys0 and vdosys1 in mt8195.
Each of them is bound to a display pipeline, so add their
definition in mtk-mmsys documentation with 2 compatibles.
2. Add description for power-domain property.
Signed-off-by: jason-jh.lin
---
this patch is base on [1][2]
[1] dt
1. Add mediatek,dsc.yaml to describe DSC module in details.
2. Add mt8195 SoC binding to mediatek,dsc.yaml.
Signed-off-by: jason-jh.lin
---
.../display/mediatek/mediatek,dsc.yaml| 69 +++
1 file changed, 69 insertions(+)
create mode 100644
Documentation/devicetree/bindi
Hi, Dave & Daniel:
This includes:
1. Fix AAL output size setting.
2. Delete component in remove function.
Regards,
Chun-Kuang.
The following changes since commit 1a64a7aff8da352c9419de3d5c34343682916411:
drm/mediatek: Fix cursor plane no update (2021-07-22 22:57:52 +0800)
are available in t
On Wed, Aug 18, 2021 at 05:12:28PM +0530, Lazar, Lijo wrote:
>
> On 8/18/2021 11:34 AM, Kees Cook wrote:
> > In preparation for FORTIFY_SOURCE performing compile-time and run-time
> > field bounds checking for memcpy(), memmove(), and memset(), avoid
> > intentionally writing across neighboring fi
On Wed, Aug 18, 2021 at 10:53:58PM +, Sean Christopherson wrote:
> On Wed, Aug 18, 2021, Kees Cook wrote:
> > On Wed, Aug 18, 2021 at 03:11:28PM +, Sean Christopherson wrote:
> > > From dbdca1f4cd01fee418c252e54c360d518b2b1ad6 Mon Sep 17 00:00:00 2001
> > > From: Sean Christopherson
> > >
Hi Dave, Daniel,
Fixes for 5.14.
The following changes since commit 7c60610d476766e128cc4284bb6349732cbd6606:
Linux 5.14-rc6 (2021-08-15 13:40:53 -1000)
are available in the Git repository at:
https://gitlab.freedesktop.org/agd5f/linux.git
tags/amd-drm-fixes-5.14-2021-08-18
for you to fe
On Tue, Aug 17, 2021 at 11:06 PM Kees Cook wrote:
>
> Use the newly introduced struct_group_typed() macro to clean up the
> declaration of struct cxl_regs.
>
> Cc: Alison Schofield
> Cc: Vishal Verma
> Cc: Ira Weiny
> Cc: Ben Widawsky
> Cc: linux-...@vger.kernel.org
> Suggested-by: Dan William
On Tue, Aug 17, 2021 at 11:06 PM Kees Cook wrote:
>
> Kernel code has a regular need to describe groups of members within a
> structure usually when they need to be copied or initialized separately
> from the rest of the surrounding structure. The generally accepted design
> pattern in C is to use
On Wed, Aug 18, 2021 at 08:42:18AM +0200, Christophe Leroy wrote:
>
>
> Le 18/08/2021 à 08:05, Kees Cook a écrit :
> > In preparation for FORTIFY_SOURCE performing compile-time and run-time
> > field bounds checking for memset(), avoid intentionally writing across
> > neighboring fields.
> >
> >
This looks great to me! Wasn't much to comment on here as most of this looks
fine to me. For the whole series:
Reviewed-by: Lyude Paul
This will be quite interesting to try getting working for nouveau
On Tue, 2021-08-17 at 23:51 +0200, Hans de Goede wrote:
> Hi all,
>
> Here is a rebased-resen
Applied. Let's see how long this one lasts :)
Alex
On Tue, Aug 17, 2021 at 4:23 AM Michel Dänzer wrote:
>
> From: Michel Dänzer
>
> schedule_delayed_work does not push back the work if it was already
> scheduled before, so amdgpu_device_delay_enable_gfx_off ran ~100 ms
> after the first time G
Applied. Thanks!
Alex
On Wed, Aug 18, 2021 at 8:41 AM Lukas Bulwahn wrote:
>
> Commit 04ed8459f334 ("drm/amdgpu: remove chash") removes the chash
> architecture and its corresponding config CHASH.
>
> There is still a reference to CHASH in the config DRM_AMDGPU in
> ./drivers/gpu/drm/Kconfig.
>
On Tue, 2021-08-17 at 23:51 +0200, Hans de Goede wrote:
> Give connector sysfs devices there own device_type, this allows us to
> check if a device passed to functions dealing with generic devices is
> a drm_connector or not.
>
> A check like this is necessary in the drm_connector_acpi_bus_match()
Hi Dave and Daniel,
Here goes drm-intel-fixes-2021-08-18:
- Expand a tweaked display workaround for all PCHs. (Anshuman)
- Fix eDP MSO pipe sanity checks for ADL-P. (Jani)
- Remove superfluous EXPORT_SYMBOL(). (Jani)
Thanks,
Rodrigo.
The following changes since commit 7c60610d476766e128cc4284bb
Quoting Krishna Manikandan (2021-08-18 03:27:01)
> MSM Mobile Display Subsystem (MDSS) encapsulates sub-blocks
> like DPU display controller, DSI, EDP etc. Add required DPU
> device tree bindings for SC7280.
>
> Signed-off-by: Krishna Manikandan
> ---
Please send a cover-letter next time.
Do you
Quoting Krishna Manikandan (2021-08-18 03:27:04)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index aadf55d..5be318e 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1412,7 +1412,7 @@
>
Quoting Krishna Manikandan (2021-08-18 03:27:03)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index fd7ff1c..aadf55d 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -1507,6 +1519,95 @@
>
Quoting Krishna Manikandan (2021-08-18 03:27:02)
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 53a21d0..fd7ff1c 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -5,6 +5,7 @@
> * Copyright
Quoting Krishna Manikandan (2021-08-18 03:27:01)
> diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
> b/Documentation/devicetree/bindings/display/msm/dpu-sc7280.yaml
> new file mode 100644
> index 000..3d256c0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/
On Wed, Aug 18, 2021 at 8:52 PM Jarkko Nikula wrote:
>
> Hi
>
> My old Thinkpad T410i won't resume properly anymore after suspend or
> hibernation after v5.12 including today's head 614cb2751d31 ("Merge tag
> 'trace-v5.14-rc6' of
> git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace"
Hi
Am 17.08.21 um 21:50 schrieb Daniel Vetter:
On Tue, Aug 17, 2021 at 8:16 PM Thomas Zimmermann wrote:
Initialize delta variable in PLL compute function for G200SE, rev 00 to
the maximum value. Fixes uninitialized usage.
smatch warnings:
drivers/gpu/drm/mgag200/mgag200_pll.c:142 mgag2
On 17/08/2021 20:48, abhin...@codeaurora.org wrote:
On 2021-06-28 12:19, Dmitry Baryshkov wrote:
Add support for alpha blending properties. Setup the plane blend state
according to those properties.
Signed-off-by: Dmitry Baryshkov
I think this has already been picked up by Rob but just had a
On 8/17/21 5:35 PM, Felix Kuehling wrote:
Am 2021-08-17 um 8:01 p.m. schrieb Ralph Campbell:
On 8/12/21 11:31 PM, Alex Sierra wrote:
From: Ralph Campbell
ZONE_DEVICE struct pages have an extra reference count that
complicates the
code for put_page() and several places in the kernel that need
Hi Dave and Daniel,
here's the drm-misc-fixes PR for this week. The vblank fix is a UAPI
change that unifies the behaviour of the regular and compat ioctl.
Best regards
Thomas
drm-misc-fixes-2021-08-18:
Short summary of fixes pull:
* UAPI: Return results for failed drm_wait_vblank_ioctl()
* t
On 18.08.2021 18:35, Daniel Vetter wrote:
> On Wed, Aug 18, 2021 at 5:11 PM Michal Wajdeczko
> wrote:
>>
>>
>>
>> On 18.08.2021 16:20, Daniel Vetter wrote:
>>> On Thu, Jul 01, 2021 at 05:55:11PM +0200, Michal Wajdeczko wrote:
Instead of plain error value (%d) print more user friendly error
Thanks Sam!
On Wed, 18 Aug 2021 at 19:40, Sam Ravnborg wrote:
>
> Hi Robert,
>
> On Wed, Aug 18, 2021 at 07:13:18PM +0200, Robert Foss wrote:
> > During the sp_tx_edid_read() call the return value of sp_tx_edid_read()
> > is ignored, which could cause potential errors to go unhandled.
> >
> > All
On Wed, 2021-08-11 at 09:49 +, Lin, Wayne wrote:
> [Public]
>
> > -Original Message-
> > From: Lyude Paul
> > Sent: Wednesday, August 11, 2021 4:45 AM
> > To: Lin, Wayne ; dri-devel@lists.freedesktop.org
> > Cc: Kazlauskas, Nicholas ; Wentland, Harry <
> > harry.wentl...@amd.com>; Zuo
Hi
My old Thinkpad T410i won't resume properly anymore after suspend or
hibernation after v5.12 including today's head 614cb2751d31 ("Merge tag
'trace-v5.14-rc6' of
git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace").
I bisected regression to commit 64f7c698bea9 ("drm/nouveau/fifo
Hi Nikola,
On Wed, Aug 18, 2021 at 04:46:48PM +0200, Nikola Pavlica wrote:
> Add vendor prefix for the Vivax brand by M SAN Grupa d.o.o.
>
> Source (in Croatian): https://www.vivax.com/hr/o-nama.aspx
>
> Signed-off-by: Nikola Pavlica
One other note, bindings patches should also be copied to th
Hi Nikola,
On Wed, Aug 18, 2021 at 04:46:47PM +0200, Nikola Pavlica wrote:
> This tablet display is unique and hence must be added to documentation.
> Unfortunately, it's real make and number is not known due to obscure and
> missing documentation and lack of writing on the display assembly
> itse
On Wed, Aug 18, 2021 at 04:46:48PM +0200, Nikola Pavlica wrote:
> Add vendor prefix for the Vivax brand by M SAN Grupa d.o.o.
>
> Source (in Croatian): https://www.vivax.com/hr/o-nama.aspx
>
> Signed-off-by: Nikola Pavlica
Reviewed-by: Sam Ravnborg
I like this as the first in the series, as we
Hi Nikola,
On Wed, Aug 18, 2021 at 04:46:46PM +0200, Nikola Pavlica wrote:
> The model and make of the LCD panel of the Vivax TPC-9150 is unknown,
> hence the panel settings that were retrieved with a FEX dump are named
> after the device NOT the actual panel.
>
> The LCD in question is a 50 pin
DP 2.0 brings some new DPCD addresses for PHY repeaters.
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
include/drm/drm_dp_helper.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
in
The DP 2.0 128b/132b channel coding uses TX FFE presets instead of
vswing and pre-emphasis.
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 14 ++
include/drm/drm_dp_helper.h | 2 ++
2 files changed, 16 insertions(+)
diff --g
Extend the use of extended receiver cap at 0x2200 to cover
MAIN_LINK_CHANNEL_CODING_CAP in 0x2206, in case an implementation hides
the DP 2.0 128b/132b channel encoding cap.
Cc: dri-devel@lists.freedesktop.org
Reviewed-by: Manasi Navare
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_help
The bw code equals link_rate / 0.27 Gbps only for 8b/10b link
rates. Handle DP 2.0 UHBR rates as special cases, though this is not
pretty.
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Jani Nikula
---
drivers/gpu/drm/drm_dp_helper.c | 26 ++
1 file changed, 22 insert
Using the generic extension support set in the previous patch, this
patch enables more than one in/out binary syncobj per job submission.
Arrays of syncobjs are set in a specific extension type (multisync)
that also cares of determining the stage for sync (bin/render)
through a flag - when this is
Add support to attach generic extensions on job submission.
This patch is a second prep work to enable multiple syncobjs on job
submission. With this work, when the job submission interface needs
to be extended to accomodate a new feature, we will use a generic
extension struct where an id determin
Prep work to enable a job to wait for more than one syncobj before
start. Also get rid of old checkpatch warnings in the v3d_gem file.
No functional changes.
Signed-off-by: Melissa Wen
---
drivers/gpu/drm/v3d/v3d_gem.c | 28 ++--
1 file changed, 18 insertions(+), 10 delet
Currently, v3d only supports single in/out syncobj per submission (in
v3d_submit_cl, there are two in_sync, one for bin and another for render
job); however, Vulkan queue submit operations expect multiples wait and
signal semaphores. This series extends v3d interface and job dependency
operations t
> From: Christian König
> Sent: Wednesday, August 18, 2021 2:10 PM
> To: Sa, Nuno ; linaro-mm-...@lists.linaro.org;
> dri-devel@lists.freedesktop.org; linux-me...@vger.kernel.org
> Cc: Rob Clark ; Sumit Semwal
>
> Subject: Re: [PATCH] dma-buf: return -EINVAL if dmabuf object is
> NULL
>
> [Exte
In line 317 (#1), drm_gem_prime_import() is called, it will call
drm_gem_prime_import_dev(). At the end of the function
drm_gem_prime_import_dev() (line 956, #2), "dma_buf_put(dma_buf);" puts
dma_buf->file and may cause it to be released. However, after
drm_gem_prime_import() returning, the dma_buf
> From: Christian König
> Sent: Wednesday, August 18, 2021 2:58 PM
> To: Daniel Vetter
> Cc: Sa, Nuno ; linaro-mm-...@lists.linaro.org;
> dri-devel@lists.freedesktop.org; linux-me...@vger.kernel.org; Rob
> Clark
> Subject: Re: [Linaro-mm-sig] [PATCH] dma-buf: return -EINVAL if
> dmabuf object is
On Wed, Aug 18, 2021 at 8:14 AM Kees Cook wrote:
>
> Since all compilers support __builtin_object_size(), and there is only
> one user of __compiletime_object_size, remove it to avoid the needless
> indirection. This lets Clang reason about check_copy_size() correctly.
Sounds good to me, the indi
On top of warning about a NULL object, we also want to return with a
proper error code (as done in 'dma_buf_begin_cpu_access()'). Otherwise,
we will get a NULL pointer dereference.
Fixes: fc13020e086b ("dma-buf: add support for kernel cpu access")
Signed-off-by: Nuno Sá
---
drivers/dma-buf/dma-b
Coverity warns of a possible NULL dereference:
Both dma_resv_lock_interruptible() and dma_resv_lock() can return -EDEADLK.
Protect
against a NULL dereference by checking for NULL before saving the object
pointer. This
is consistent with previous checks for ww==NULL.
Addresses-Coverity: ("Derefe
Hey,
Just a couple fixes for Ampere display issues, and a long-standing
race in MM paths.
Ben.
The following changes since commit 7c60610d476766e128cc4284bb6349732cbd6606:
Linux 5.14-rc6 (2021-08-15 13:40:53 -1000)
are available in the Git repository at:
git://github.com/skeggsb/linux lin
Hi Robert,
On Wed, Aug 18, 2021 at 07:13:18PM +0200, Robert Foss wrote:
> During the sp_tx_edid_read() call the return value of sp_tx_edid_read()
> is ignored, which could cause potential errors to go unhandled.
>
> All errors which are returned by sp_tx_edid_read() are handled in
> anx7625_get_e
Hi Robert,
On Wed, Aug 18, 2021 at 07:13:17PM +0200, Robert Foss wrote:
> The return value of sp_tx_rst_aux() is not propagated, which means
> both compiler warnings and potential errors not being handled.
>
> Fixes: 8bdfc5dae4e3 ("drm/bridge: anx7625: Add anx7625 MIPI DSI/DPI to DP")
>
> Report
18.08.2021 11:35, Ulf Hansson пишет:
> Thanks for clarifying! As I said, feel free to ignore my comments then.
>
> For this and the other patches in the series, I assume you only need
> to care about whether the driver is a cross SoC driver and used on
> other platforms than Tegra then.
Yes, and
18.08.2021 19:57, Dmitry Osipenko пишет:
Also, I don't think the tegra- prefix is necessary here. The parent node
is already identified as Tegra via the compatible string.
In the case of CAR, I'd imagine something like:
clocks {
sclk {
Users reported that after commit 2bbd6dba84d4 ("drm/i915: Try to use
fast+narrow link on eDP again and fall back to the old max strategy on
failure"), the screen starts to have wobbly effect.
Commit a5c936add6a2 ("drm/i915/dp: Use slow and wide link training for
everything") doesn't help either, t
During the sp_tx_edid_read() call the return value of sp_tx_edid_read()
is ignored, which could cause potential errors to go unhandled.
All errors which are returned by sp_tx_edid_read() are handled in
anx7625_get_edid().
Signed-off-by: Robert Foss
---
drivers/gpu/drm/bridge/analogix/anx7625.c
The return value of sp_tx_rst_aux() is not propagated, which means
both compiler warnings and potential errors not being handled.
Fixes: 8bdfc5dae4e3 ("drm/bridge: anx7625: Add anx7625 MIPI DSI/DPI to DP")
Reported-by: kernel test robot
Signed-off-by: Robert Foss
---
Changes since v1:
- Inste
If the ttm_bo_init_reserved() call fails ensure we also release the
region, otherwise we leak the reference, or worse hit some uaf, when we
start using the objects.list. Also remove the make_unshrinkable call
here, which doesn't do anything.
Signed-off-by: Matthew Auld
Cc: Thomas Hellström
---
1 - 100 of 233 matches
Mail list logo