Hi Kris,
On Wed, Jan 12, 2022 at 3:19 AM Kris Karas (Bug reporting)
wrote:
> Javier Martinez Canillas wrote:
> > Changes in v2:
> > - Make the change only for x86 (Geert Uytterhoeven)
> > - Only check the suppported video mode for x86 (Geert Uytterhoeven).
>
> I just updated Bug 215001 to
If nobody has any more objections/ideas I'm going to push this one here
to drm-misc-next in the afternoon.
Christian.
Am 11.01.22 um 21:14 schrieb Arunpravin:
Move the base i915 buddy allocator code into drm
- Move i915_buddy.h to include/drm
- Move i915_buddy.c to drm root folder
- Rename
Hi Neil,
On Mon, Sep 7, 2020 at 1:48 PM Neil Armstrong wrote:
>
> The Amlogic AXg SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a),
> with a custom
> glue managing the IP resets, clock and data input similar to the DW-HDMI Glue
> on other
> Amlogic SoCs.
>
> This adds support for the
On Tue, Jan 4, 2022 at 3:30 PM AngeloGioacchino Del Regno
wrote:
>
> DRM bridge drivers are now attaching their DSI device at probe time,
> which requires us to register our DSI host in order to let the bridge
> to probe: this recently started producing an endless -EPROBE_DEFER
> loop on some
Yeah, that should probably be the right one.
Christian.
Am 12.01.22 um 03:19 schrieb Chen, Guchun:
[Public]
Hi Christian,
My BAD, I checked that discussion history of this just now. So If I read it correctly,
the double check at a different place to skip evict is: " drm/ttm: Double check
Hi Andrey,
Please go ahead and push your change. I will prepare the RFC later.
On 2022/1/8 上午12:02, Andrey Grodzovsky wrote:
>
> On 2022-01-07 12:46 a.m., JingWen Chen wrote:
>> On 2022/1/7 上午11:57, JingWen Chen wrote:
>>> On 2022/1/7 上午3:13, Andrey Grodzovsky wrote:
On 2022-01-06 12:18
Sorry for being super delayed on response here. I'm buried in other
work. +Jerome for exclusive clk API.
Quoting Maxime Ripard (2021-09-14 02:35:13)
> It's not unusual to find clocks being shared across multiple devices
> that need to change the rate depending on what the device is doing at a
>
[Public]
Hi Christian,
My BAD, I checked that discussion history of this just now. So If I read it
correctly, the double check at a different place to skip evict is: " drm/ttm:
Double check mem_type of BO while eviction"? It is in 5.16 kernel.
Regards,
Guchun
-Original Message-
From:
https://bugzilla.kernel.org/show_bug.cgi?id=215001
--- Comment #13 from Kris Karas (bugs-...@moonlit-rail.com) ---
Hi Javier, et al,
I have just tested version two of the patch (from email, I don't see it listed
in the attachments), on the original two BIOS/VGAC servers, one new UEFI
server, and
Hi, Simon
On 2022/01/06 8:57, Simon Ser wrote:
Thanks for working on this! I've pushed a patch [1] to drm-misc-next which
touches the same function, can you rebase your patches on top of it?
[1]: https://patchwork.freedesktop.org/patch/467940/?series=98255=3
I understand. I will rebase the
On Fri, 07 Jan 2022 15:55:11 +0100, Neil Armstrong wrote:
> Add third port corresponding to the ENCL DPI encoder used to connect
> to DSI or LVDS transceivers.
>
> Signed-off-by: Neil Armstrong
> ---
> .../devicetree/bindings/display/amlogic,meson-vpu.yaml | 5 +
> 1 file changed, 5
On Fri, Jan 07, 2022 at 03:55:10PM +0100, Neil Armstrong wrote:
> The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver
> (ver 1.21a),
> with a custom glue managing the IP resets, clock and data input similar to
> the DW-HDMI Glue
> on the same Amlogic SoCs.
>
>
On Fri, 07 Jan 2022 20:22:08 +0800, xiazhengqiao wrote:
> Add dt-bindings for 10.1" TFT LCD module called STARRY 2081101
> QFH032011-53G.
>
> Signed-off-by: xiazhengqiao
> ---
> .../display/panel/innolux,himax8279d.yaml | 72 +++
> 1 file changed, 72 insertions(+)
> create
On Fri, 07 Jan 2022 00:13:32 -0500, Peter Geis wrote:
> Some implementations do not use the reset signal, instead tying it to dvdd.
> Make the reset gpio optional to permit this.
>
> Signed-off-by: Peter Geis
> ---
> .../bindings/display/panel/feiyang,fy07024di26a30d.yaml | 1 -
> 1
Quoting Yong Wu (2022-01-11 04:22:23)
> Hi Stephen,
>
> Thanks for helping update here.
>
> On Thu, 2022-01-06 at 13:45 -0800, Stephen Boyd wrote:
> > Use an aggregate driver instead of component ops so that we can get
> > proper driver probe ordering of the aggregate device with respect to
> >
On Wed, 12 Jan 2022 at 02:12, Kuogee Hsieh wrote:
>
>
> On 1/6/2022 9:26 PM, Dmitry Baryshkov wrote:
> > On 07/01/2022 06:42, Stephen Boyd wrote:
> >> Quoting Dmitry Baryshkov (2022-01-06 18:01:27)
> >>> Currently DP driver will allocate panel bridge for eDP panels.
> >>> Simplify this code to
Add a cancel request selftest that results in an engine reset to cancel
the request as it is non-preemptable. Also insert a NOP request after
the cancelled request and confirm that it completes successfully.
v2:
(Tvrtko)
- Skip test if preemption timeout compiled out
- Skip test if engine
In the i915 there are several hacks in place to make request cancelation
work with an old version of the GuC which delivered the G2H indicating
schedule disable is done before G2H indicating a context reset. Version
69 fixes this, so we can remove these hacks.
Signed-off-by: Matthew Brost
---
Remove a hack required because schedule disable done G2H was received
before context reset G2H in GuC firmware 62.0.0. Since we have upgraded
69.0.3, this is no longer required.
Also revive selftest which proves this works before / after change.
Signed-off-by: Matthew Brost
Matthew Brost (2):
On 1/6/2022 9:26 PM, Dmitry Baryshkov wrote:
On 07/01/2022 06:42, Stephen Boyd wrote:
Quoting Dmitry Baryshkov (2022-01-06 18:01:27)
Currently DP driver will allocate panel bridge for eDP panels.
Simplify this code to just check if there is any next bridge in the
chain (be it a panel bridge
On 2022-01-11 4:02 p.m., Jason Gunthorpe wrote:
> On Tue, Jan 11, 2022 at 03:57:07PM -0700, Logan Gunthorpe wrote:
>>
>>
>> On 2022-01-11 3:53 p.m., Jason Gunthorpe wrote:
>>> I just want to share the whole API that will have to exist to
>>> reasonably support this flexible array of intervals
On 2022-01-11 3:57 p.m., Jason Gunthorpe wrote:
> On Tue, Jan 11, 2022 at 03:09:13PM -0700, Logan Gunthorpe wrote:
>
>> Either that, or we need a wrapper that allocates an appropriately
>> sized SGL to pass to any dma_map implementation that doesn't support
>> the new structures.
>
> This is
On Tue, Jan 11, 2022 at 03:57:07PM -0700, Logan Gunthorpe wrote:
>
>
> On 2022-01-11 3:53 p.m., Jason Gunthorpe wrote:
> > I just want to share the whole API that will have to exist to
> > reasonably support this flexible array of intervals data structure..
>
> Is that really worth it? I feel
On Tue, Jan 11, 2022 at 1:31 PM Akhil P Oommen wrote:
>
> Add support for "Adreno 8c Gen 3" gpu along with the necessary speedbin
> support.
>
> Signed-off-by: Akhil P Oommen
> ---
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 21 +
>
On Tue, Jan 11, 2022 at 03:09:13PM -0700, Logan Gunthorpe wrote:
> Either that, or we need a wrapper that allocates an appropriately
> sized SGL to pass to any dma_map implementation that doesn't support
> the new structures.
This is what I think we should do. If we start with RDMA then we can
On 2022-01-11 3:53 p.m., Jason Gunthorpe wrote:
> I just want to share the whole API that will have to exist to
> reasonably support this flexible array of intervals data structure..
Is that really worth it? I feel like type safety justifies replicating a
bit of iteration and allocation
On Tue, Jan 11, 2022 at 09:25:40PM +, Matthew Wilcox wrote:
> > I don't need the sgt at all. I just need another list of physical
> > addresses for DMA. I see no issue with a phsr_list storing either CPU
> > Physical Address or DMA Physical Addresses, same data structure.
>
> There's a
Hi Andi,
On 2022-01-11 14:15:51, Andi Shyti wrote:
>
> From: Tvrtko Ursulin
>
> On a multi-tile platform, each tile has its own registers + GGTT
> space, and BAR 0 is extended to cover all of them.
>
> Up to four gts are supported in i915->gt[], with slot zero
> shadowing the existing
On 2022-01-11 2:25 p.m., Matthew Wilcox wrote:
> That's reproducing the bad decision of the scatterlist, only with
> a different encoding. You end up with something like:
>
> struct neoscat {
> dma_addr_t dma_addr;
> phys_addr_t phys_addr;
> size_t dma_len;
> size_t
On Tue, Jan 11, 2022 at 04:21:59PM -0400, Jason Gunthorpe wrote:
> On Tue, Jan 11, 2022 at 06:33:57PM +, Matthew Wilcox wrote:
>
> > > Then we are we using get_user_phyr() at all if we are just storing it
> > > in a sg?
> >
> > I did consider just implementing get_user_sg() (actually 4 years
On Tue, Jan 11, 2022 at 10:35:22PM +0200, Laurent Pinchart wrote:
> Hi Dan,
>
> Thank you for the patch.
>
> On Tue, Jan 11, 2022 at 09:27:14PM +0100, Daniel Vetter wrote:
> > Otherwise it's really hard to link to that, which I realized when I
> > wanted to link to the property definitions for a
Hi Paul,
On 1/11/22 12:28, Paul Menzel wrote:
> Dear Linux folks,
>
>
> I am using Linux 5.16, and I am unable to unset `VGA_ARB` in Kconfig (`make
> menuconfig`). I have an Asus F2A85-M PRO with an AMD A6-6400K APU (integrated
> Radeon graphics device), so no legacy stuff.
>
> From
On Tue, Jan 11, 2022 at 7:38 AM Harry Wentland wrote:
>
> Attached is a v2 of the buggy patch that should get this right.
> If you have a chance to try it out let us know
I can confirm that I do not see the horribly flickering behavior with
this patch.
I didn't look at what the actual
Dear Linux folks,
I am using Linux 5.16, and I am unable to unset `VGA_ARB` in Kconfig
(`make menuconfig`). I have an Asus F2A85-M PRO with an AMD A6-6400K APU
(integrated Radeon graphics device), so no legacy stuff.
From `drivers/gpu/vga/Kconfig`:
```
config VGA_ARB
bool "VGA
Hi Dan,
Thank you for the patch.
On Tue, Jan 11, 2022 at 09:27:14PM +0100, Daniel Vetter wrote:
> Otherwise it's really hard to link to that, which I realized when I
> wanted to link to the property definitions for a question on irc.
>
> Fix it.
>
> Fixes: e2d7fc20b3e2 ("drm/writeback: wire
Otherwise it's really hard to link to that, which I realized when I
wanted to link to the property definitions for a question on irc.
Fix it.
Fixes: e2d7fc20b3e2 ("drm/writeback: wire drm_writeback.h to kernel-doc")
Cc: Sam Ravnborg
Cc: Daniel Vetter
Cc: Laurent Pinchart
Cc: Brian Starkey
On Tue, Jan 11, 2022 at 10:05:40AM +0100, Daniel Vetter wrote:
> If we go with page size I think hardcoding a PHYS_PAGE_SIZE KB(4)
> would make sense, because thanks to x86 that's pretty much the lowest
> common denominator that all hw (I know of at least) supports. Not
> having to fiddle with
On Tue, Jan 11, 2022 at 06:33:57PM +, Matthew Wilcox wrote:
> > Then we are we using get_user_phyr() at all if we are just storing it
> > in a sg?
>
> I did consider just implementing get_user_sg() (actually 4 years ago),
> but that cements the use of sg as both an input and output data
- Remove drm_mm references and replace with drm buddy functionalities
- Add res cursor support for drm buddy
v2(Matthew Auld):
- replace spinlock with mutex as we call kmem_cache_zalloc
(..., GFP_KERNEL) in drm_buddy_alloc() function
- lock drm_buddy_block_trim() function as it calls
Move shared vram inline functions and structs
into a header file
Signed-off-by: Arunpravin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 51
1 file changed, 51 insertions(+)
create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h
diff --git
On contiguous allocation, we round up the size
to the *next* power of 2, implement a function
to free the unused pages after the newly allocate block.
v2(Matthew Auld):
- replace function name 'drm_buddy_free_unused_pages' with
drm_buddy_block_trim
- replace input argument name
Implemented a function which walk through the order list,
compares the offset and returns the maximum offset block,
this method is unpredictable in obtaining the high range
address blocks which depends on allocation and deallocation.
for instance, if driver requests address at a low specific
Move the base i915 buddy allocator code into drm
- Move i915_buddy.h to include/drm
- Move i915_buddy.c to drm root folder
- Rename "i915" string with "drm" string wherever applicable
- Rename "I915" string with "DRM" string wherever applicable
- Fix header file dependencies
- Fix alignment issues
- Make drm_buddy_alloc a single function to handle
range allocation and non-range allocation demands
- Implemented a new function alloc_range() which allocates
the requested power-of-two block comply with range limitations
- Moved order computation and memory alignment logic from
i915
yes, I will use Dual MIT/GPL
Regards,
Arun
On 10/01/22 1:33 pm, Christian König wrote:
> Am 09.01.22 um 15:19 schrieb Arunpravin:
>> +// SPDX-License-Identifier: MIT
>
>> +MODULE_DESCRIPTION("DRM Buddy Allocator");
>> +MODULE_LICENSE("GPL");
>
> I'm not an expert on this, but maybe we
Hello Yunfei,
Le lundi 10 janvier 2022 à 16:34 +0800, Yunfei Dong a écrit :
> This series adds support for mt8192 h264/vp8/vp9 decoder drivers. Firstly,
> refactor
> power/clock/interrupt interfaces for mt8192 is lat and core architecture.
>
> Secondly, add new functions to get frame buffer
Hi Andrzej,
On Tue, Jan 11, 2022 at 5:26 AM Andrzej Hajda wrote:
> I am not DP specialist so CC-ed people working with DP
Thanks for the review regardless! I'll also not claim to be a DP
specialist -- although I've had to learn my fair share to debug a good
handful of issues on an SoC using
Acked-by: Lyude Paul
On Wed, 2021-12-15 at 11:43 +0100, Thomas Zimmermann wrote:
> Move DisplayPort functions into a separate module to reduce the size
> of the KMS helpers. Select DRM_DP_HELPER for all users of the code. To
> avoid naming conflicts, rename drm_dp_helper.c to drm_dp.c
>
> This
On Mon, Jan 10, 2022 at 9:10 PM Robert Foss wrote:
>
> On Mon, 10 Jan 2022 at 16:35, Jagan Teki wrote:
> >
> > Hi Robert,
> >
> > On Mon, Jan 10, 2022 at 9:02 PM Robert Foss wrote:
> > >
> > > Hey Jagan,
> > >
> > > This is a mistake on my end, I must have been looking at reviewing
> > > this
On Thu, Jan 06, 2022 at 04:31:43PM -0800, john.c.harri...@intel.com wrote:
> From: John Harrison
>
> There is a race (already documented in the code) whereby a context can
> be (re-)queued for submission at the same time as it is being banned
> due to a hang and reset. That leads to a hang/reset
This reverts commit 92e794fab87af0793403d5e4a547f0be94a0e656.
It is merged by accident, the actual patch series on this bridge
conversion is still under review.
Revert this as it breaks the exynos DSI.
Signed-off-by: Jagan Teki
---
drivers/gpu/drm/exynos/exynos_drm_dsi.c | 93
Each DP link training contains link training 1 followed by link
training 2. There is maximum of 5 retries of DP link training
before declared link training failed. It is required to stop link
training at end of link training 2 if it is failed so that next
link training 1 can start freshly. This
From: Kuogee Hsieh
Some DP sinkers prefer to use tps4 instead of tps3 during training #2.
This patch will use tps4 to perform link training #2 if sinker's DPCD
supports it.
Changes in V2:
-- replace dp_catalog_ctrl_set_pattern() with
dp_catalog_ctrl_set_pattern_state_bit()
Changes in V3:
--
DP CTS test case 4.2.2.6 has valid edid with bad checksum on purpose
and expect DP source return correct checksum. During drm edid read,
correct edid checksum is calculated and stored at
connector::real_edid_checksum.
The problem is struct dp_panel::connector never be assigned, instead the
Current DP drivers have regulators, clocks, irq and phy are grouped
together within a function and executed not in a symmetric manner.
This increase difficulty of code maintenance and limited code scalability.
This patch divides the driver life cycle of operation into four states,
resume
Group below 4 dp driver related patches into one series.
Kuogee Hsieh (4):
drm/msm/dp: do not initialize phy until plugin interrupt received
drm/msm/dp: populate connector of struct dp_panel
drm/msm/dp: add support of tps4 (training pattern 4) for HBR3
drm/msm/dp: stop link training
On Tue, Jan 11, 2022 at 11:01:42AM -0400, Jason Gunthorpe wrote:
> On Tue, Jan 11, 2022 at 04:32:56AM +, Matthew Wilcox wrote:
> > On Mon, Jan 10, 2022 at 08:41:26PM -0400, Jason Gunthorpe wrote:
> > > On Mon, Jan 10, 2022 at 07:34:49PM +, Matthew Wilcox wrote:
> > >
> > > > Finally, it
On 2022-01-11 1:17 a.m., John Hubbard wrote:
> On 1/10/22 11:34, Matthew Wilcox wrote:
>> TLDR: I want to introduce a new data type:
>>
>> struct phyr {
>> phys_addr_t addr;
>> size_t len;
>> };
>>
>> and use it to replace bio_vec as well as using it to replace the array
>> of
Reviewed-by: Lyude Paul
On Fri, 2021-12-17 at 18:56 -0800, Yizhuo Zhai wrote:
> In function nvkm_ioctl_map(), the variable "type" could be
> uninitialized if "nvkm_object_map()" returns error code, however,
> it does not check the return value and directly use the "type" in
> the if statement,
From: Matthew Auld
On discrete platforms like DG2, we need to support a minimum page size
of 64K when dealing with device local-memory. This is quite tricky for
various reasons, so try to document the new implicit uapi for this.
v2: Fixed suggestions on formatting [Daniel]
Signed-off-by:
add test to check handling of misaligned offsets and sizes
Signed-off-by: Robert Beckett
---
drivers/gpu/drm/i915/selftests/i915_gem_gtt.c | 130 ++
1 file changed, 130 insertions(+)
diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_gtt.c
From: Matthew Auld
discrete cards optimise 64K GTT pages for local-memory, since everything
should be allocated at 64K granularity. We say goodbye to sparse
entries, and instead get a compact 256B page-table for 64K pages,
which should be more cache friendly. 4K pages for local-memory
are no
From: Matthew Auld
For local-memory objects we need to align the GTT addresses
to 64K, both for the ppgtt and ggtt.
We need to support vm->min_alignment > 4K, depending
on the vm itself and the type of object we are inserting.
With this in mind update the GTT selftests to take this
into
This series continues support for 64K pages for discrete cards.
It supersedes the 64K patches from
https://patchwork.freedesktop.org/series/95686/#rev4
Changes since that series:
- set min alignment for DG2 to 2MB in i915_address_space_init
- replace coloring with simpler 2MB VA alignment for
Don't use the interruptable version of the timeline mutex lock in the
error path of eb_pin_timeline as the cleanup must always happen.
v2:
(John Harrison)
- Don't check for interrupt during mutex lock
v3:
(Tvrtko)
- A comment explaining why lock helper isn't used
Fixes: 544460c33821
Move the multi-lrc guc_id from the lower allocation partition (0 to
number of multi-lrc guc_ids) to upper allocation partition (number of
single-lrc to max guc_ids).
Signed-off-by: Matthew Brost
---
.../gpu/drm/i915/gt/uc/intel_guc_submission.c | 57 ++-
1 file changed, 42
On 2022-01-10 6:58 p.m., Felix Kuehling
wrote:
On
2022-01-05 9:43 a.m., philip yang wrote:
On 2021-12-22 7:37 p.m., Rajneesh Bhardwaj wrote:
During CRIU restore phase, the VMAs for
the virtual
Hi Ville,
Thanks for your review
On Wed, Dec 15, 2021 at 03:48:39PM +0200, Ville Syrjälä wrote:
> On Wed, Dec 15, 2021 at 01:43:53PM +0100, Maxime Ripard wrote:
> > The current code, when parsing the EDID Deep Color depths, that the
> > YUV422 cannot be used, referring to the HDMI 1.3
On Mon, 10 Jan 2022, Ville Syrjälä wrote:
> On Tue, Jan 04, 2022 at 08:48:56PM +0200, Jani Nikula wrote:
>> DP_SINK_COUNT_ESI and DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 have the same
>> contents as DP_SINK_COUNT and DP_DEVICE_SERVICE_IRQ_VECTOR,
>> respectively.
>
> IIRC there was an oversight in the
On 2022-01-10 7:10 p.m., Felix Kuehling
wrote:
On
2022-01-05 10:22 a.m., philip yang wrote:
On 2021-12-22 7:37 p.m., Rajneesh Bhardwaj wrote:
Recoverable page faults are represented
by the
Pushed out to drm-misc-next-fixes.
Alex
On Fri, Jan 7, 2022 at 9:07 PM Liu Ying wrote:
>
> On Fri, 2022-01-07 at 14:53 -0500, Alex Deucher wrote:
> > On Wed, Dec 29, 2021 at 11:07 PM Liu Ying wrote:
> > >
> > > Actual hardware state of CRTC is controlled by the member 'active'
> > > in
> > >
On 2022-01-11 10:08, Alex Deucher wrote:
> On Mon, Jan 10, 2022 at 9:53 PM Linus Torvalds
> wrote:
>>
>> On Mon, Jan 10, 2022 at 6:44 PM Linus Torvalds
>> wrote:
>>>
>>> I'll double-check to see if a revert fixes it at the top of my tree.
>>
>> Yup. It reverts cleanly, and the end result
On Mon, Jan 10, 2022 at 9:53 PM Linus Torvalds
wrote:
>
> On Mon, Jan 10, 2022 at 6:44 PM Linus Torvalds
> wrote:
> >
> > I'll double-check to see if a revert fixes it at the top of my tree.
>
> Yup. It reverts cleanly, and the end result builds and works fine, and
> doesn't show the horrendous
On Tue, Jan 11, 2022 at 02:01:17PM +, Matthew Wilcox wrote:
> On Tue, Jan 11, 2022 at 12:17:18AM -0800, John Hubbard wrote:
> > Zooming in on the pinning aspect for a moment: last time I attempted to
> > convert O_DIRECT callers from gup to pup, I recall wanting very much to
> > record, in
On Tue, Jan 11, 2022 at 04:32:56AM +, Matthew Wilcox wrote:
> On Mon, Jan 10, 2022 at 08:41:26PM -0400, Jason Gunthorpe wrote:
> > On Mon, Jan 10, 2022 at 07:34:49PM +, Matthew Wilcox wrote:
> >
> > > Finally, it may be possible to stop using scatterlist to describe the
> > > input to the
Hi
Am 11.01.22 um 14:56 schrieb Matthew Wilcox:
On Tue, Jan 11, 2022 at 12:40:10PM +0100, Thomas Zimmermann wrote:
Hi
Am 10.01.22 um 20:34 schrieb Matthew Wilcox:
TLDR: I want to introduce a new data type:
struct phyr {
phys_addr_t addr;
size_t len;
};
Did you look at
On Tue, Jan 11, 2022 at 12:17:18AM -0800, John Hubbard wrote:
> Zooming in on the pinning aspect for a moment: last time I attempted to
> convert O_DIRECT callers from gup to pup, I recall wanting very much to
> record, in each bio_vec, whether these pages were acquired via FOLL_PIN,
> or some
On Tue, Jan 11, 2022 at 12:40:10PM +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 10.01.22 um 20:34 schrieb Matthew Wilcox:
> > TLDR: I want to introduce a new data type:
> >
> > struct phyr {
> > phys_addr_t addr;
> > size_t len;
> > };
>
> Did you look at struct dma_buf_map?
On Tue, Jan 11, 2022 at 5:20 PM Andrzej Hajda wrote:
>
> Hi Jagan,
>
> On 11.01.2022 10:32, Jagan Teki wrote:
> > Hi Andrzej,
> >
> > On Tue, Dec 28, 2021 at 4:18 PM Andrzej Hajda
> > wrote:
> >> Hi Marek,
> >>
> >> On 23.12.2021 10:15, Marek Szyprowski wrote:
> >>> Hi Jagan,
> >>>
> >>> On
Den 11.01.2022 14.26, skrev Thomas Zimmermann:
> Set the source-buffer address after mapping the buffer into the
> kernel's address space. Makes MIPI DBI helpers work again.
>
> Signed-off-by: Thomas Zimmermann
> Fixes: c47160d8edcd ("drm/mipi-dbi: Remove dependency on GEM CMA helper
>
Hi Brian,
I am not DP specialist so CC-ed people working with DP
On 01.10.2021 23:42, Brian Norris wrote:
If the display is not enable()d, then we aren't holding a runtime PM
reference here. Thus, it's easy to accidentally cause a hang, if user
space is poking around at /dev/drm_dp_aux0 at
Set the source-buffer address after mapping the buffer into the
kernel's address space. Makes MIPI DBI helpers work again.
Signed-off-by: Thomas Zimmermann
Fixes: c47160d8edcd ("drm/mipi-dbi: Remove dependency on GEM CMA helper
library")
Reported-by: Noralf Trønnes
Cc: Thomas Zimmermann
Cc:
Hi,
On Mon, Jan 10, 2022 at 10:56:23AM +0100, Javier Martinez Canillas wrote:
> This patch series contains two fixes for the vga16fb driver. I looked at
> the driver due a regression reported [0], caused by commit d391c5827107
> ("drivers/firmware: move x86 Generic System Framebuffers support").
Hi Maxime,
Thank you for the patch.
On Tue, Jan 11, 2022 at 12:06:35PM +0100, Maxime Ripard wrote:
> Following the previous patch, let's introduce a generic panel-lvds
> binding that documents the panels that don't have any particular
> constraint documented.
>
> Reviewed-by: Rob Herring
>
Hi Maxime,
Thank you for the patch.
On Tue, Jan 11, 2022 at 12:06:34PM +0100, Maxime Ripard wrote:
> The lvds.yaml file so far was both defining the generic LVDS properties
> (such as data-mapping) that could be used for any LVDS sink, but also
> the panel-lvds binding.
>
> That last binding
Hi Thomas,
On Tue, Jan 11, 2022 at 10:38:36AM +0100, Thomas Zimmermann wrote:
> Hi
>
> Am 15.12.21 um 10:51 schrieb Maxime Ripard:
> > Once the call to drm_fb_helper_remove_conflicting_framebuffers() has
> > been made, simplefb has been unregistered and the KMS driver is entirely
> > in charge
On Wed, 15 Dec 2021 10:51:13 +0100, Maxime Ripard wrote:
> The VC4 driver has had limited support to disable the HDMI controllers and
> pixelvalves at boot if the firmware has enabled them.
>
> However, this proved to be limited, and a bit unreliable so a new firmware
> command has been
Hi Stephen,
Thanks for helping update here.
On Thu, 2022-01-06 at 13:45 -0800, Stephen Boyd wrote:
> Use an aggregate driver instead of component ops so that we can get
> proper driver probe ordering of the aggregate device with respect to
> all
> the component devices that make up the aggregate
The GT has its own properties and in sysfs they should be grouped
in the 'gt/' directory.
Create a 'gt/' directory in sysfs which will contain gt0...gtN
directories related to each tile configured in the GPU. Move the
power management files inside those directories.
The previous power management
From: Tvrtko Ursulin
On a multi-tile platform, each tile has its own registers + GGTT
space, and BAR 0 is extended to cover all of them.
Up to four gts are supported in i915->gt[], with slot zero
shadowing the existing i915->gt0 to enable source compatibility
with legacy driver paths. A
Hi,
This is the second series that prepares i915 to host multitile
platforms. It introduces the for_each_gt() macro that loops over
the tiles to perform per gt actions.
This patch is a combination of two patches developed originally
by Abdiel, who introduced some refactoring during probe, and
> The MIPI DBI helpers access struct drm_gem_cma_object.vaddr in a
> few places. Replace all instances with the correct generic GEM
> functions. Use drm_gem_fb_vmap() for mapping a framebuffer's GEM
> objects and drm_gem_fb_vunmap() for unmapping them. This removes
> the dependency on CMA helpers
Add helpers for initializing SIL164-based connectors. These used to be
handled by the VGA connector code. But SIL164 provides output via DVI-I,
so set the encoder and connector types accordingly.
If a SIL164 chip has been detected, ast will now create a DVI-I
connector instead of a VGA connector.
Add helpers for DP501-based connectors. DP501 provides output via
DisplayPort. This used to be handled by the VGA connector code.
If a DP501 chip has been detected, ast will now create a DisplayPort
connector instead of a VGA connector.
Remove the DP501 code from
The ITE66121 is an HDMI transmitter chip. There's no code for
detecting or programming the chip within ast. Remove the enum
constant.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/gpu/drm/ast/ast_drv.h
The tests in ast_mode_valid() verify the correct resolution for the
supplied mode. This is a limitation of the CRTC, so move the function
to the CRTC helpers. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_mode.c | 129 +
1
Remove reading the link-rate. The value is maintained by the connector
code but never used.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_dp501.c | 58 -
drivers/gpu/drm/ast/ast_drv.h | 1 -
drivers/gpu/drm/ast/ast_mode.c | 7 ++--
3 files
Prepare for introducing other connectors besides VGA. No functional
changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 10
drivers/gpu/drm/ast/ast_mode.c | 45 +-
2 files changed, 27 insertions(+), 28 deletions(-)
diff --git
Move encoder and connector initialization into a single helper and
put all related mode-setting structures into a single place. Done in
preparation of moving transmitter code into separate helpers. No
functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_drv.h | 8
Update the connector code to fail if the connector could not be
initialized. The current code just ignored the error and failed
later when the connector was supposed to be used.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/ast/ast_mode.c | 13 -
1 file changed, 8
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