://anongit.freedesktop.org/drm-intel for-linux-next
config: mips-randconfig-c004-20220227
(https://download.01.org/0day-ci/archive/20220301/202203010150.l57eax3w-...@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project
d271fc04d5b97b12e6b797c6067d3c96a8d7470e
As the potential failure of the i915_gem_object_trylock(),
it should be better to check it and return error if fails.
Fixes: 94ce0d65076c ("drm/i915/gt: Setup a default migration context on the GT")
Signed-off-by: Jiasheng Jiang
---
drivers/gpu/drm/i915/gt/selftest_migrate.c | 6 +-
1 file
From: Daniele Ceraolo Spurio
HW resources are divided across the active CCS engines at the compute
slice level, with each CCS having priority on one of the cslices.
If a compute slice has no enabled DSS, its paired compute engine is not
usable in full parallel execution because the other ones
Convert the bindings to yaml and add the ast2600 compatible string.
Signed-off-by: Joel Stanley
---
.../devicetree/bindings/gpu/aspeed,gfx.yaml | 69 +++
.../devicetree/bindings/gpu/aspeed-gfx.txt| 41 ---
2 files changed, 69 insertions(+), 41 deletions(-)
create
Hi Andrey,
On Tue, 1 Mar 2022 22:26:12 -0500 Andrey Grodzovsky
wrote:
>
> Please check you have commit c7703ce38c1e Andrey Grodzovsky 3 weeks ago
> drm/amdgpu: Fix htmldoc warning
That has arrived in linux-next today for the first time. It is in the
drm tree, but that tree has had build
On 02/03/2022 05:44, Bjorn Andersson wrote:
On Tue 01 Mar 17:47 PST 2022, Dmitry Baryshkov wrote:
On Wed, 2 Mar 2022 at 04:27, Bjorn Andersson wrote:
It's typical for the bootloader to bring up the display for showing a
boot splash or efi framebuffer. But in some cases the kernel driver
On Wed, Mar 2, 2022 at 4:50 AM Linus Walleij wrote:
>
> On Tue, Mar 1, 2022 at 3:13 PM Jagan Teki wrote:
>
> > + bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);
> > + if (IS_ERR(bridge)) {
> > + dev_err(dev, "error to get bridge\n");
> > + return
On Wed, Mar 2, 2022 at 4:43 AM Linus Walleij wrote:
>
> On Tue, Mar 1, 2022 at 3:13 PM Jagan Teki wrote:
>
> > devm_drm_of_get_bridge is capable of looking up the downstream
> > bridge and panel and trying to add a panel bridge if the panel
> > is found.
> >
> > Replace explicit finding calls
On Tue, Feb 22, 2022 at 06:10:30PM +0100, Thomas Hellström wrote:
vms are not getting properly closed. Rather than fixing that,
Remove the vm open count and instead rely on the vm refcount.
The vm open count existed solely to break the strong references the
vmas had on the vms. Now instead make
Please check you have commit c7703ce38c1e Andrey Grodzovsky 3 weeks
ago drm/amdgpu: Fix htmldoc warning
Andrey
On 2022-03-01 20:31, Stephen Rothwell wrote:
Hi all,
On Thu, 20 Jan 2022 14:26:39 +1100 Stephen Rothwell
wrote:
On Wed, 17 Nov 2021 13:49:26 +1100 Stephen Rothwell
wrote:
On Wed, 2 Mar 2022 at 02:49, Tommy Haung wrote:
>
> v6:
> Remove some unnecessary reset patch.
> Refine patch format.
> Add detail explain of SOC display reset bits.
>
> v5:
> Add lost reset define.
>
> v4:
> Add necessary reset control for ast2600.
> Add chip caps for futher use.
>
On Wed, 2 Mar 2022 at 02:50, Tommy Haung wrote:
>
> Remove the ast2500-gfx from aspeed-g6.dtsi.
> In the AST2600, the ASPEED_RESET_CRT1 is replaced by
> ASPEED_RESET_GRAPHICS. This is no differnce between these two reset
> behavior but reigster location is changed. The HW controller states
> and
Remove the ast2500-gfx from aspeed-g6.dtsi.
In the AST2600, the ASPEED_RESET_CRT1 is replaced by
ASPEED_RESET_GRAPHICS. This is no differnce between these two reset
behavior but reigster location is changed. The HW controller states
and FW programming resgiter will be reset by CRT reset controller
Add AST2600 chip support and setting.
Signed-off-by: Tommy Haung
---
drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
b/drivers/gpu/drm/aspeed/aspeed_gfx_drv.c
index d4b56b3c7597..d10246b1d1c2 100644
v6:
Remove some unnecessary reset patch.
Refine patch format.
Add detail explain of SOC display reset bits.
v5:
Add lost reset define.
v4:
Add necessary reset control for ast2600.
Add chip caps for futher use.
These code are test on AST2500 and AST2600 by below steps.
1. Add
From: Joel Stanley
The GFX device is present in the AST2600 SoC.
Signed-off-by: Joel Stanley
Signed-off-by: Tommy Haung
---
arch/arm/boot/dts/aspeed-g6.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi
Add interrupt clear register define for further chip support.
Signed-off-by: Tommy Haung
---
drivers/gpu/drm/aspeed/aspeed_gfx.h | 1 +
drivers/gpu/drm/aspeed/aspeed_gfx_drv.c | 6 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx.h
From: Joel Stanley
Enable the GFX device with a framebuffer memory region.
Signed-off-by: Joel Stanley
Signed-off-by: Tommy Haung
---
arch/arm/boot/dts/aspeed-ast2600-evb.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts
On 3/1/22 14:18, Lucas Stach wrote:
Am Dienstag, dem 01.03.2022 um 07:03 -0600 schrieb Adam Ford:
On Tue, Mar 1, 2022 at 5:05 AM Lucas Stach wrote:
Am Dienstag, dem 01.03.2022 um 11:19 +0100 schrieb Marek Vasut:
On 3/1/22 11:04, Lucas Stach wrote:
Hi,
[...]
Given the two totally
Hi Arunpravin,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm/drm-next]
[also build test WARNING on drm-tip/drm-tip]
[cannot apply to drm-intel/for-linux-next v5.17-rc6 next-20220301]
[If your patch is applied to the wrong git tree, kindly drop us a note
On 3/1/22 14:37, Robby Cai wrote:
Hi,
[...]
I tend to agree with Marek on this one. We have an instance where the
blk-ctrl and the GPC driver between 8m, mini, nano, plus are close,
but different enough where each SoC has it's own set of tables and
some checks. Lucas created the framework,
On Mon 28 Feb 13:38 PST 2022, Rob Herring wrote:
> Another pass at removing unnecessary use of 'allOf' with a '$ref'.
>
> json-schema versions draft7 and earlier have a weird behavior in that
> any keywords combined with a '$ref' are ignored (silently). The correct
> form was to put a '$ref'
On Tue 01 Mar 17:47 PST 2022, Dmitry Baryshkov wrote:
> On Wed, 2 Mar 2022 at 04:27, Bjorn Andersson
> wrote:
> >
> > It's typical for the bootloader to bring up the display for showing a
> > boot splash or efi framebuffer. But in some cases the kernel driver ends
> > up only partially
DP AUX transactions can consist of many short operations. There's no
need to power things up/down in short intervals.
I pick an arbitrary 100ms; for the systems I'm testing (Rockchip
RK3399), runtime-PM transitions only take a few microseconds.
Signed-off-by: Brian Norris
---
Changes in v4:
-
If the display is not enable()d, then we aren't holding a runtime PM
reference here. Thus, it's easy to accidentally cause a hang, if user
space is poking around at /dev/drm_dp_aux0 at the "wrong" time.
Let's get a runtime PM reference, and check that we "see" the panel.
Don't force any panel
On Mon, 28 Feb 2022 15:38:02 -0600 Rob Herring wrote:
> Another pass at removing unnecessary use of 'allOf' with a '$ref'.
>
> json-schema versions draft7 and earlier have a weird behavior in that
> any keywords combined with a '$ref' are ignored (silently). The correct
> form was to put a '$ref'
On Tue, Feb 22, 2022 at 2:10 PM Doug Anderson wrote:
> On Thu, Feb 17, 2022 at 2:42 PM Brian Norris wrote:
> > --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> > +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> > @@ -1121,7 +1121,7 @@ static int analogix_dp_get_modes(struct
On Wed, 2 Mar 2022 at 04:27, Bjorn Andersson wrote:
>
> It's typical for the bootloader to bring up the display for showing a
> boot splash or efi framebuffer. But in some cases the kernel driver ends
> up only partially configuring (in particular) the DPU, which might
> result in e.g. that two
Quoting Dmitry Baryshkov (2022-03-01 16:14:10)
> Add missing brace in dpu-qcm2290.yaml. While we are at it, also fix
> indentation for another brace, so it matches the corresponding line.
>
> Reported-by: Rob Herring
> Cc: Loic Poulain
> Reviewed-by: Bjorn Andersson
> Signed-off-by: Dmitry
Quoting Dmitry Baryshkov (2022-03-01 16:52:10)
> The number of interrupt cells for the mdss interrupt controller is 1,
> meaning there should only be one cell for the interrupt number, not two.
> Drop the second cell containing (unused) irq flags.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Quoting Dmitry Baryshkov (2022-03-01 16:52:09)
> The number of interrupt cells for the mdss interrupt controller is 1,
> meaning there should only be one cell for the interrupt number, not two.
> Drop the second cell containing (unused) irq flags.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Quoting Dmitry Baryshkov (2022-03-01 16:52:08)
> The number of interrupt cells for the mdss interrupt controller is 1,
> meaning there should only be one cell for the interrupt number, not two.
> Drop the second cell containing (unused) irq flags.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Quoting Dmitry Baryshkov (2022-03-01 16:52:07)
> The number of interrupt cells for the mdss interrupt controller is 1,
> meaning there should only be one cell for the interrupt number, not two.
> Drop the second cell containing (unused) irq flags.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Quoting Dmitry Baryshkov (2022-03-01 16:52:06)
> The number of interrupt cells for the mdss interrupt controller is 1,
> meaning there should only be one cell for the interrupt number, not two.
> Drop the second cell containing (unused) irq flags.
>
> Signed-off-by: Dmitry Baryshkov
> ---
Hi all,
On Wed, 2 Feb 2022 09:38:37 +0100 Hans de Goede wrote:
>
> On 2/2/22 05:03, Stephen Rothwell wrote:
> >
> > On Wed, 2 Feb 2022 15:02:01 +1100 Stephen Rothwell
> > wrote:
> >>
> >> After merging the drm tree, today's linux-next build (htmldocs) produced
> >> this warning:
> >>
> >>
Hi all,
On Wed, 2 Feb 2022 15:10:45 +1100 Stephen Rothwell
wrote:
>
> After merging the drm tree, today's linux-next build (htmldocs) produced
> this warning:
>
> include/drm/drm_connector.h:637: warning: Function parameter or member
> 'edid_hdmi_rgb444_dc_modes' not described in
Hi all,
On Thu, 20 Jan 2022 14:26:39 +1100 Stephen Rothwell
wrote:
>
> On Wed, 17 Nov 2021 13:49:26 +1100 Stephen Rothwell
> wrote:
> >
> > After merging the drm-misc tree, today's linux-next build (htmldocs)
> > produced this warning:
> >
> > include/drm/gpu_scheduler.h:316: warning:
It's typical for the bootloader to bring up the display for showing a
boot splash or efi framebuffer. But in some cases the kernel driver ends
up only partially configuring (in particular) the DPU, which might
result in e.g. that two different data paths attempts to push data to
the interface -
Add an optional reference to the MDSS_CORE reset, which when specified
can be used by the implementation to reset the hardware blocks.
Signed-off-by: Bjorn Andersson
---
Changes since v1:
- New approach/patch
.../devicetree/bindings/display/msm/dpu-qcm2290.yaml | 4
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two.
Drop the second cell containing (unused) irq flags.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 6 +++---
1 file changed,
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two.
Drop the second cell containing (unused) irq flags.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sdm660.dtsi | 2 +-
1 file changed, 1
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two.
Drop the second cell containing (unused) irq flags.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 6 +++---
1 file changed,
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two.
Drop the second cell containing (unused) irq flags.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/sdm630.dtsi | 4 ++--
1 file changed, 2
The number of interrupt cells for the mdss interrupt controller is 1,
meaning there should only be one cell for the interrupt number, not two.
Drop the second cell containing (unused) irq flags.
Signed-off-by: Dmitry Baryshkov
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 6 +++---
1 file
Hi Krzysztof,
22. 2. 7. 01:51에 Krzysztof Kozlowski 이(가) 쓴 글:
> On 25/03/2019 08:13, Andrzej Hajda wrote:
>> GSCALERs in Exynos5433 have local path to DECON and DECON_TV.
>> They can be used as extra planes with support for non-RGB formats and
>> scaling.
>> To enable it on DECON update_plane and
On 3/1/2022 4:14 PM, Dmitry Baryshkov wrote:
Add missing brace in dpu-qcm2290.yaml. While we are at it, also fix
indentation for another brace, so it matches the corresponding line.
Reported-by: Rob Herring
Cc: Loic Poulain
Reviewed-by: Bjorn Andersson
Signed-off-by: Dmitry Baryshkov
From: John Harrison
The CTB registration process changed significantly a while back using
a single KLV based H2G. So drop the original and now obsolete H2G
definitions.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h | 2
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as the limit
for how many context ids are available. Instead, size the pool
according to the number of contexts allowed. Note that this is just a
naming change, the actual limit is identical in value.
While at it, also
From: John Harrison
The LRC descriptor was being initialised early on in the context
registration sequence. It could then be determined that the actual
registration needs to be delayed and the descriptor would be wiped
out. This is inefficient, so move the setup to later in the process
after the
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as a check
for whether submission has been initialised or not.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc.h| 2 ++
From: John Harrison
Some G2H handlers were reading the context id field from the payload
before checking the payload met the minimum length required.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c | 6 --
1 file
From: John Harrison
The LRC descriptor pool is going away. So, stop naming context ids as
descriptor pool indecies.
While at it, add a bunch of missing line feeds to some error messages.
Signed-off-by: John Harrison
Reviewed-by: Daniele Ceraolo Spurio
---
From: John Harrison
The LRC descriptor pool is going away. Further, the function that was
populating it was also doing a bunch of logic about the context
registration sequence. So, split that code apart into separate state
setup and try to register functions. Note that some of those 'try to
From: John Harrison
The LRC descriptor pool is going away. So, stop using it as a check for
context registration, use the GuC id instead (being the thing that
actually gets registered with the GuC).
Also, rename the set/clear/query helper functions for context id
mappings to better reflect
From: John Harrison
The next GuC firmware release includes some significant backwards
breaking API changes. One such is that there is no longer an LRC
descriptor pool. A bunch of prep work for that change can be done in
advance - the descriptor pool was being used for things it shouldn't
really
On Wed, 2 Mar 2022 at 03:14, Dmitry Baryshkov
wrote:
>
> Add missing brace in dpu-qcm2290.yaml. While we are at it, also fix
> indentation for another brace, so it matches the corresponding line.
>
> Reported-by: Rob Herring
> Cc: Loic Poulain
> Reviewed-by: Bjorn Andersson
> Signed-off-by:
On Tue, Mar 01, 2022 at 03:15:45PM -0800, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> Tell GuC that CCS is enabled by setting a bit in its ADS.
>
> Cc: Vinay Belgaumkar
> Original-author: Michel Thierry
> Signed-off-by: Daniele Ceraolo Spurio
> Signed-off-by: Matt Roper
We have to specify in the Render Control Unit Mode register
when CCS is enabled.
v2:
- Move RCU_MODE programming to a helper function. (Tvrtko)
- Clean up and clarify comments. (Tvrtko)
- Add RCU_MODE to the GuC save/restore list. (Daniele)
v3:
- Move this patch before the GuC ADS update
Add missing brace in dpu-qcm2290.yaml. While we are at it, also fix
indentation for another brace, so it matches the corresponding line.
Reported-by: Rob Herring
Cc: Loic Poulain
Reviewed-by: Bjorn Andersson
Signed-off-by: Dmitry Baryshkov
---
Didn't include freedreno@ in the first email, so
Hi,
On Wed, Feb 16, 2022 at 9:00 AM Dave Stevenson
wrote:
>
> Hi All
>
> Hopefully I've cc'ed all those that have bashed this problem around
> previously,
> or are otherwise linked to DRM bridges.
>
> There have been numerous discussions around how DSI support is currently
> broken
> as it
On Tue, Mar 01, 2022 at 03:15:49PM -0800, Matt Roper wrote:
> From: Srinivasan Shanmugam
>
> Registers that exist in the shared render/compute reset domain need to
> be placed on an engine workaround list to ensure that they are properly
> re-applied whenever an RCS or CCS engine is reset. We
On Tue, Mar 01, 2022 at 03:51:21PM -0800, Umesh Nerlige Ramappa wrote:
> On Tue, Mar 01, 2022 at 03:15:44PM -0800, Matt Roper wrote:
> > We have to specify in the Render Control Unit Mode register
> > when CCS is enabled.
> >
> > v2:
> > - Move RCU_MODE programming to a helper function. (Tvrtko)
Hi Joel,
> -Original Message-
> From: Joel Stanley
> Sent: Tuesday, March 1, 2022 7:05 PM
> To: Tommy Huang
> Cc: David Airlie ; Daniel Vetter ; Rob
> Herring ; Andrew Jeffery ;
> linux-aspeed ; open list:DRM DRIVERS
> ; devicetree ;
> Linux ARM ; Linux Kernel Mailing List
> ; BMC-SW
>
On Tue, Mar 1, 2022 at 3:19 PM David Laight wrote:
>
> Having said that there are so few users of list_entry_is_head()
> it is reasonable to generate two new names.
Well, the problem is that the users of list_entry_is_head() may be few
- but there are a number of _other_ ways to check "was that
On Tue, Mar 01, 2022 at 03:15:44PM -0800, Matt Roper wrote:
We have to specify in the Render Control Unit Mode register
when CCS is enabled.
v2:
- Move RCU_MODE programming to a helper function. (Tvrtko)
- Clean up and clarify comments. (Tvrtko)
- Add RCU_MODE to the GuC save/restore list.
On Tue, Mar 01, 2022 at 03:15:47PM -0800, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> HW resources are divided across the active CCS engines at the compute
> slice level, with each CCS having priority on one of the cslices.
> If a compute slice has no enabled DSS, its paired compute
On Mon, Feb 28, 2022 at 8:21 PM Andrey Grodzovsky
wrote:
>
> Acked-by: Andrey Grodzovsky
>
> Andrey
Thanks. Applied to drm-misc-next.
Melissa
>
> On 2022-02-28 13:16, Melissa Wen wrote:
> > Remove redundant error message (since now it is very similar to what
> > we do in drm_sched_init) and
On 3/1/2022 3:15 PM, Matt Roper wrote:
From: Daniele Ceraolo Spurio
Tell GuC that CCS is enabled by setting a bit in its ADS.
It's a mask, not a bit.
Reviewed-by: Daniele Ceraolo Spurio
Daniele
Cc: Vinay Belgaumkar
Original-author: Michel Thierry
Signed-off-by: Daniele Ceraolo
On Tue, Mar 1, 2022 at 3:13 PM Jagan Teki wrote:
> + bridge = devm_drm_of_get_bridge(dev, dev->of_node, 0, 0);
> + if (IS_ERR(bridge)) {
> + dev_err(dev, "error to get bridge\n");
> + return PTR_ERR(bridge);
> }
>
> d->bridge_out = bridge;
From: Linus Torvalds
> Sent: 01 March 2022 23:03
>
> On Tue, Mar 1, 2022 at 2:58 PM David Laight wrote:
> >
> > Can it be resolved by making:
> > #define list_entry_is_head(pos, head, member) ((pos) == NULL)
> > and double-checking that it isn't used anywhere else (except in
> > the list macros
On Wed, 2 Mar 2022 at 00:05, Rob Herring wrote:
>
> The MDSS interrupt provider is a single cell, so specifying interrupt flags
> on the consumers is incorrect.
>
> Signed-off-by: Rob Herring
Reviewed-by: Dmitry Baryshkov
> ---
> .../devicetree/bindings/display/msm/dpu-msm8998.yaml
Additional workarounds are required once we start exposing CCS engines.
Note that we have a number of workarounds that update registers in the
shared render/compute reset domain. Historically we've just added such
registers to the RCS engine's workaround list. But going forward we
should be
From: Daniele Ceraolo Spurio
Tell GuC that CCS is enabled by setting a bit in its ADS.
Cc: Vinay Belgaumkar
Original-author: Michel Thierry
Signed-off-by: Daniele Ceraolo Spurio
Signed-off-by: Matt Roper
---
drivers/gpu/drm/i915/gt/uc/intel_guc_ads.c | 1 +
1 file changed, 1 insertion(+)
From: Srinivasan Shanmugam
Registers that exist in the shared render/compute reset domain need to
be placed on an engine workaround list to ensure that they are properly
re-applied whenever an RCS or CCS engine is reset. We have a number of
workarounds (updating registers MLTICTXCTL,
We have to specify in the Render Control Unit Mode register
when CCS is enabled.
v2:
- Move RCU_MODE programming to a helper function. (Tvrtko)
- Clean up and clarify comments. (Tvrtko)
- Add RCU_MODE to the GuC save/restore list. (Daniele)
v3:
- Move this patch before the GuC ADS update
From: Matthew Brost
A different emit breadcrumbs ring programming is required for compute /
render and we don't have UMD user so just reject parallel submission for
these engine classes.
Signed-off-by: Matthew Brost
Signed-off-by: Matt Roper
Reviewed-by: Daniele Ceraolo Spurio
---
From: Daniele Ceraolo Spurio
HW resources are divided across the active CCS engines at the compute
slice level, with each CCS having priority on one of the cslices.
If a compute slice has no enabled DSS, its paired compute engine is not
usable in full parallel execution because the other ones
In Dual Context mode the EUs are shared between render and compute
command streamers. The hardware provides a field in the lrc descriptor
to indicate the prioritization of the thread dispatch associated to the
corresponding context.
The context priority is set to 'low' at creation time and relies
The compute engine handles the same commands the render engine can
(except 3D pipeline), so it makes sense that CCS is more similar to RCS
than non-render engines.
The CCS context state (lrc) is also similar to the render one, so reuse
it. Note that the compute engine has its own
This is a more appropriate header for these definitions.
v2:
- Cleanup whitespace. (Lucas)
Signed-off-by: Matt Roper
Reviewed-by: Lucas De Marchi
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
drivers/gpu/drm/i915/gt/intel_gt_regs.h | 34 ---
From: Daniele Ceraolo Spurio
CCS will reuse the RCS functions for breadcrumb and flush emission.
However, CCS pipe_control has additional programming restrictions:
- Command Streamer Stall Enable must be always set
- Post Sync Operations must not be set to Write PS Depth Count
- 3D-related
Add execlists and GuC interrupts for compute CS into existing IRQ handlers.
All compute command streamers belong to the same compute class, so the
only change needed to enable their interrupts is to program their GT engine
interrupt mask registers.
CCS0 shares the register with CCS1, while CCS2
Introduce a Compute Command Streamer (CCS), which has access to
the media and GPGPU pipelines (but not the 3D pipeline).
To begin with, define the compute class/engine common functions, based
on the existing render ones.
v2:
- Add kerneldoc for drm_i915_gem_engine_class since we're adding a new
The reset domain is shared between render and all compute engines,
so resetting one will affect the others.
Note: Before performing a reset on an RCS or CCS engine, the GuC will
attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid
impacting other clients (since some shared
The Xe_HP architecture introduces compute engines as a new engine class.
These compute command streamers (CCS) are similar to the render engine,
except that they're intended for GPGPU usage and lack support for the 3D
pipeline.
For now we're just sending some initial "under the hood" preparation
On Tue, Mar 1, 2022 at 3:13 PM Jagan Teki wrote:
> devm_drm_of_get_bridge is capable of looking up the downstream
> bridge and panel and trying to add a panel bridge if the panel
> is found.
>
> Replace explicit finding calls with devm_drm_of_get_bridge.
>
> Cc: Linus Walleij
> Signed-off-by:
On Tue, Mar 1, 2022 at 2:58 PM David Laight wrote:
>
> Can it be resolved by making:
> #define list_entry_is_head(pos, head, member) ((pos) == NULL)
> and double-checking that it isn't used anywhere else (except in
> the list macros themselves).
Well, yes, except for the fact that then the name
From: Linus Torvalds
> Sent: 01 March 2022 19:07
> On Mon, Feb 28, 2022 at 2:29 PM James Bottomley
> wrote:
> >
> > However, if the desire is really to poison the loop variable then we
> > can do
> >
> > #define list_for_each_entry(pos, head, member) \
> > for
On Mon, Feb 28, 2022 at 09:42:43AM -0800, Matt Roper wrote:
> From: Daniele Ceraolo Spurio
>
> HW resources are divided across the active CCS engines at the compute
> slice level, with each CCS having priority on one of the cslices.
> If a compute slice has no enabled DSS, its paired compute
Hi Dave & Daniel,
This is the main pull for v5.18.
We're experimenting a bit with the process this time, with Dmitry
collecting display patches and merging them into msm-next with me
handling the gpu/etc side of things. Summary of interesting new bits
and pieces
* dpu + dp support for sc8180x
Le mercredi 23 février 2022 à 11:40 +0800, Yunfei Dong a écrit :
> Add support for VP9 decoding using the stateless API,
> as supported by MT8192. And the drivers is lat and core architecture.
You already have a reviewed tag, but I'm under the impression that there is a
fair amount of duplication
Thanks for this work.
Le mercredi 23 février 2022 à 11:40 +0800, Yunfei Dong a écrit :
> Add support for VP8 decoding using the stateless API,
> as supported by MT8192.
With the struct members naming made consistent, even though I would like your
patch better if it was not duplicating so much
Le mercredi 23 février 2022 à 11:40 +0800, Yunfei Dong a écrit :
> Adds h264 lat and core architecture driver for mt8192,
> and the decode mode is frame based for stateless decoder.
>
> Signed-off-by: Yunfei Dong
> ---
> drivers/media/platform/mtk-vcodec/Makefile| 1 +
>
On 2/24/2022 5:52 PM, john.c.harri...@intel.com wrote:
From: John Harrison
It is possible for reset notifications to arrive for a context that is
in the process of being banned. So don't flag these as an error, just
report it as informational (because it is still useful to know that
resets
When we are swapping out the local memory obj on flat-ccs capable platform,
we need to capture the ccs data too along with main meory and we need to
restore it when we are swapping in the content.
When lmem object is swapped into a smem obj, smem obj will
have the extra pages required to hold the
On Xe-HP and later devices, we use dedicated compression control
state (CCS) stored in local memory for each surface, to support the
3D and media compression formats.
The memory required for the CCS of the entire local memory is 1/256 of
the local memory size. So before the kernel boot, the
When a driver needs extra pages in ttm_tt, to facilidate such
requirement, parameter called "extra_pages" is added for
ttm_tt_init
Signed-off-by: Ramalingam C
cc: Christian Koenig
cc: Hellstrom Thomas
---
drivers/gpu/drm/drm_gem_vram_helper.c | 2 +-
From: Ayaz A Siddiqui
Xe-HP and latest devices support Flat CCS which reserved a portion of
the device memory to store compression metadata, during the clearing of
device memory buffer object we also need to clear the associated
CCS buffer.
Flat CCS memory can not be directly accessed by S/W.
On Xe-HP and later devices, we use dedicated compression control
state (CCS) stored in local memory for each surface, to support
the 3D and media compression formats.
The memory required for the CCS of the entire local memory is
1/256 of the local memory size. So before the kernel
boot, the
From: Ayaz A Siddiqui
Xe-HP and latest devices support Flat CCS which reserved a portion of
the device memory to store compression metadata, during the clearing of
device memory buffer object we also need to clear the associated
CCS buffer.
Flat CCS memory can not be directly accessed by S/W.
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