Hi Matt,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on drm-tip/drm-tip]
[also build test WARNING on drm-exynos/exynos-drm-next drm/drm-next
next-20220310]
[cannot apply to drm-intel/for-linux-next tegra-drm/drm/tegra/for-next
airlied/drm-next v5.17-rc8]
[If
On 18/02/2022 12:03, Ville Syrjala wrote:
From: Ville Syrjälä
struct drm_display_mode embeds a list head, so overwriting
the full struct with another one will corrupt the list
(if the destination mode is on a list). Use drm_mode_copy()
instead which explicitly preserves the list head of
the
- Some DPU versions support inline rot90. It is supported only for
limited amount of UBWC formats.
- There are two versions of inline rotators, v1 (present on sm8250 and
sm7250) and v2 (sc7280). These versions differ in the list of supported
formats and in the scaler possibilities.
Changes in
Julia,
> drivers/scsi/aic7xxx/aicasm/aicasm.c|2 +-
> drivers/scsi/elx/libefc_sli/sli4.c |2 +-
> drivers/scsi/lpfc/lpfc_mbox.c |2 +-
> drivers/scsi/qla2xxx/qla_gs.c |2 +-
Applied patches 2, 17, 24,
From: John Harrison
sseu_dev_info is already a pretty large structure which will likely
continue to grow when future platforms increase potential DSS and EU
counts. Let's switch the stack placement of this structure in debugfs
with a dynamic allocation.
Signed-off-by: John Harrison
On Tue, 15 Mar 2022 at 01:21, Linus Walleij wrote:
>
> On Fri, Mar 4, 2022 at 1:03 AM Joel Stanley wrote:
>
> > The example needs updating to match the to be added yaml bindings for
> > the gfx node.
> >
> > Signed-off-by: Joel Stanley
>
> Reviewed-by: Linus Walleij
>
> I guess you will merge
On Fri, Mar 4, 2022 at 1:03 AM Joel Stanley wrote:
> The example needs updating to match the to be added yaml bindings for
> the gfx node.
>
> Signed-off-by: Joel Stanley
Reviewed-by: Linus Walleij
I guess you will merge this elsewhere or shall I apply it to the pinctrl tree?
Yours,
Linus
From: Daniele Ceraolo Spurio
GuC has its own steering mechanism and can't use the default set by i915,
so we need to provide the steering information that the FW will need to
save/restore registers while processing an engine reset. The GUC
interface allows us to do so as part of the register
Upcoming patches will need to steer writes to multicast registers as
well as reading them.
Although the setting of the 'multicast' bit should only really matter
for write operations (reads always operate in a unicast manner and give
us the result from one specific instance), Wa_22013088509
Add a new 'steering' node in each gt's debugfs directory that tells
whether we're using explicit steering for various types of MCR ranges
and, if so, what MMIO ranges it applies to.
We're going to be transitioning away from implicit steering, even for
slice/dss steering soon, so the information
A few minor steering updates, mostly to prepare for other upcoming work.
We'll soon be doing most of our steering explicitly, rather than relying
on implicit steering as we do now, so reporting the steering assignments
in debugfs will be helpful for debugging. We also have some features
coming up
On 3/15/22 02:26, Alyssa Rosenzweig wrote:
> On Tue, Mar 15, 2022 at 01:42:53AM +0300, Dmitry Osipenko wrote:
>> Replace Panfrost's memory shrinker with a generic DRM memory shrinker.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> drivers/gpu/drm/panfrost/Makefile | 1 -
>>
On Tue, Mar 15, 2022 at 01:42:53AM +0300, Dmitry Osipenko wrote:
> Replace Panfrost's memory shrinker with a generic DRM memory shrinker.
>
> Signed-off-by: Dmitry Osipenko
> ---
> drivers/gpu/drm/panfrost/Makefile | 1 -
> drivers/gpu/drm/panfrost/panfrost_device.h | 4
>
On Tue, Mar 8, 2022 at 9:27 AM Jagan Teki wrote:
> devm_drm_of_get_bridge is capable of looking up the downstream
> bridge and panel and trying to add a panel bridge if the panel
> is found.
>
> Replace explicit finding calls with devm_drm_of_get_bridge.
>
> Cc: Linus Walleij
> Signed-off-by:
On 2022-03-08 10:58 a.m., Lucas De Marchi wrote:
On Tue, Feb 22, 2022 at 08:24:31PM +0100, Thomas Hellström (Intel) wrote:
Hi, Michael,
On 2/22/22 18:26, Michael Cheng wrote:
This patch removes logic for wbinvd_on_all_cpus and brings in
drm_cache.h. This header has the logic that outputs a
On 3/10/22 01:43, Dmitry Osipenko wrote:
>> I think that, given virgl uses host storage, guest shrinker should be
>> still useful.. so I think continue with this series.
> Guest shrinker indeed will be useful for virgl today. I was already
> questioning why virgl needs both host and guest
DRM API requires the DRM's driver to be backed with the device that can
be used for generic DMA operations. The VirtIO-GPU device can't perform
DMA operations if it uses PCI transport because PCI device driver creates
a virtual VirtIO-GPU device that isn't associated with the PCI. Use PCI's
GPU
Replace Panfrost's memory shrinker with a generic DRM memory shrinker.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/panfrost/Makefile | 1 -
drivers/gpu/drm/panfrost/panfrost_device.h | 4
drivers/gpu/drm/panfrost/panfrost_drv.c| 19 ++-
Add memory shrinker support and new madvise IOCTL to the VirtIO-GPU
driver. Userspace (BO cache manager of Mesa driver) will mark BOs as
"don't need" using the new IOCTL to let shrinker purge the marked BOs
on OOM, thus shrinker will lower memory pressure and prevent OOM kills.
For the starter
Introduce a common DRM SHMEM shrinker. It allows to reduce code
duplication among DRM drivers, it also handles complicated lockings
for the drivers. This is initial version of the shrinker that covers
basic needs of GPU drivers.
This patch is based on a couple ideas borrowed from Rob's Clark MSM
drm_gem_shmem_get_sg_table() never returns NULL on error, but a ERR_PTR.
Correct the doc comment which says that it returns NULL on error.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/drm_gem_shmem_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Unlock reservations in the error code path of virtio_gpu_object_create()
to silence debug warning splat produced by ww_mutex_destroy(>lock)
when GEM is released with the held lock.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/virtio/virtgpu_object.c | 2 ++
1 file changed, 2 insertions(+)
Transferred 2D BO always must be a shmem BO. Add check for that to prevent
NULL dereference if userspace passes a VRAM BO.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/virtio/virtgpu_vq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
drm_gem_shmem_get_sg_table() never ever returned NULL on error. Correct
the error handling to avoid crash on OOM.
Cc: sta...@vger.kernel.org
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/virtio/virtgpu_object.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
Hello,
This patchset introduces memory shrinker for the VirtIO-GPU DRM driver.
During OOM, the shrinker will release BOs that are marked as "not needed"
by userspace using the new madvise IOCTL. The userspace in this case is
the Mesa VirGL driver, it will mark the cached BOs as "not needed",
Hi! First a little bit of background: I've recently been trying to get rid of
all of the non-atomic payload bandwidth management code in the MST helpers in
order to make it easier to implement DSC and fallback link rate retraining
support down the line. Currently bandwidth information is stored in
On Fri, Feb 18, 2022 at 12:03:41PM +0200, Ville Syrjala wrote:
> drm: Add drm_mode_init()
> drm/bridge: Use drm_mode_copy()
> drm/imx: Use drm_mode_duplicate()
> drm/panel: Use drm_mode_duplicate()
> drm/vc4: Use drm_mode_copy()
These have been pushed to drm-misc-next.
> drm/amdgpu:
On Sat, 12 Mar 2022 20:23:48 +0100
Jonathan Neuschäfer wrote:
> Hello Andreas,
>
> Sorry for the delay, I finally got around to having a look at the
> patchset.
>
> Some comments from skimming the patches below, and in my other replies.
>
>
> On Sun, Feb 06, 2022 at 09:00:11AM +0100, Andreas
On 3/11/22 17:22, Maxime Ripard wrote:
> Hi Dmitry,
>
> On Thu, Mar 10, 2022 at 03:33:07AM +0300, Dmitry Osipenko wrote:
>> I was playing/testing SuperTuxKart using VirtIO-GPU driver and spotted a
>> UAF bug in drm_atomic_helper_wait_for_vblanks().
>>
>> SuperTuxKart can use DRM directly, i.e.
On 3/11/22 20:06, jim.cro...@gmail.com wrote:
> On Fri, Mar 11, 2022 at 12:06 PM Jason Baron wrote:
>>
>>
>>
>> On 3/10/22 23:47, Jim Cromie wrote:
>>> DRM defines/uses 10 enum drm_debug_category's to create exclusive
>>> classes of debug messages. To support this directly in dynamic-debug,
On Mon, Mar 14, 2022 at 10:40:47AM +0200, Jani Nikula wrote:
> On Sun, 13 Mar 2022, Lee Shawn C wrote:
> > drm_find_cea_extension() always look for a top level CEA block. Pass
> > ext_index from caller then this function to search next available
> > CEA ext block from a specific EDID block
Hi Thomas,
On Sun, Mar 13, 2022 at 8:29 PM Thomas Zimmermann wrote:
> Commit 6f29e04938bf ("fbdev: Improve performance of sys_imageblit()")
> broke sys_imageblit() for image width that are not aligned to 8-bit
> boundaries. Fix this by handling the trailing pixels on each line
> separately. The
Hi Christophe,
Le lun., mars 7 2022 at 19:12:49 +0100, Christophe Branchereau
a écrit :
Hi Paul, it should in theory, but doesn't work in practice, the
display doesn't like having that bit set outside of the init sequence.
Feel free to experiment if you think you can make it work though, you
Hello:
This series was applied to netdev/net-next.git (master)
by Jakub Kicinski :
On Mon, 14 Mar 2022 12:53:24 +0100 you wrote:
> Various spelling mistakes in comments.
> Detected with the help of Coccinelle.
>
> ---
>
> drivers/base/devres.c |4 ++--
>
Hi Christophe,
Le ven., mars 11 2022 at 18:02:37 +0100, Christophe Branchereau
a écrit :
This allows the CRTC to be enabled after panels have slept out,
and before their display is turned on, solving a graphical bug
on the newvision nv3502c
Signed-off-by: Christophe Branchereau
---
Hi Christophe,
Le ven., mars 11 2022 at 18:02:38 +0100, Christophe Branchereau
a écrit :
This driver supports the NewVision NV3052C based LCDs. Right now, it
only supports the LeadTek LTK035C5444T 2.4" 640x480 TFT LCD panel,
which
can be found in the Anbernic RG-350M handheld console.
handle a situation in the condition order-- == min_order,
when order = 0, leading to order = -1, it now won't exit
the loop. To avoid this problem, added a order check in
the same condition, (i.e) when order is 0, we return
-ENOSPC
Signed-off-by: Arunpravin
---
drivers/gpu/drm/drm_buddy.c | 2
On Mon, 14 Mar 2022 at 20:27, Vinod Polimera wrote:
>
> - Some DPU versions support inline rot90. It is supported only for
> limited amount of UBWC formats.
> - There are two versions of inline rotators, v1 (present on sm8250 and
> sm7250) and v2 (sc7280). These versions differ in the list of
handle instances when size is not aligned with the min_page_size.
Unigine Heaven has allocation requests for example required pages
are 161 and alignment request is 128. To allocate the left over
33 pages, continues the iteration to find the order value which
is 5 and 0 and when it compares with
On 10/03/22 8:59 pm, Matthew Auld wrote:
> On 10/03/2022 14:47, Arunpravin wrote:
>>
>>
>> On 08/03/22 10:31 pm, Matthew Auld wrote:
>>> On 08/03/2022 13:59, Arunpravin wrote:
On 07/03/22 10:11 pm, Matthew Auld wrote:
> On 07/03/2022 14:37, Arunpravin wrote:
>> place
On Mon, 14 Mar 2022 at 17:47, Vinod Polimera wrote:
>
> use max clock during probe/bind sequence from the opp table.
> The clock will be scaled down when framework sends an update.
>
> Fixes: 25fdd5933("drm/msm: Add SDM845 DPU support")
> Signed-off-by: Vinod Polimera
Reviewed-by: Dmitry
Hi Pekka,
On Mon, Mar 14, 2022 at 4:05 PM Pekka Paalanen wrote:
> On Mon, 14 Mar 2022 14:30:18 +0100
> Geert Uytterhoeven wrote:
> > On Mon, Mar 7, 2022 at 9:53 PM Geert Uytterhoeven
> > wrote:
> > > Introduce fourcc codes for color-indexed frame buffer formats with two,
> > > four, and
From: Chris Wilson
When testing whether we can get the GPU to leak information about
non-privileged state, we first need to ensure that the output buffer is
set to a known value as the HW may opt to skip the write into memory for
a non-privileged read of a sensitive register. We chose
From: Chris Wilson
Ensure that we always signal the semaphore when timing out, so that if it
happens to be stuck waiting for the semaphore we will quickly recover
without having to wait for a reset.
Reported-by: CQ Tang
Signed-off-by: Chris Wilson
Cc: CQ Tang
cc: Joonas Lahtinen
From: Chris Wilson
In order to keep the context image parser simple, we assume that all
commands follow a similar format. A few, especially not MI commands on
the render engines, have fixed lengths not encoded in a length field.
This caused us to incorrectly skip over 3D state commands, and
From: Chris Wilson
Even though the initial protocontext we load onto HW has the register
cleared, by the time we save it into the default image, BB_OFFSET has
had the enable bit set. Reclear BB_OFFSET for each new context.
Testcase: igt/i915_selftests/gt_lrc
Signed-off-by: Chris Wilson
Cc:
Few bug fixes for lrc selftest.
Chris Wilson (4):
drm/i915/gt: Explicitly clear BB_OFFSET for new contexts
drm/i915/selftests: Check for incomplete LRI from the context image
drm/i915/selftest: Clear the output buffers before GPU writes
drm/i915/selftest: Always cancel semaphore on error
Few bug fixes for lrc selftest.
Chris Wilson (4):
drm/i915/gt: Explicitly clear BB_OFFSET for new contexts
drm/i915/selftests: Check for incomplete LRI from the context image
drm/i915/selftest: Clear the output buffers before GPU writes
drm/i915/selftest: Always cancel semaphore on error
On 3/14/22 11:18, Sascha Hauer wrote:
> On Sun, Mar 13, 2022 at 12:07:56AM +0300, Dmitry Osipenko wrote:
>> On 3/11/22 11:33, Sascha Hauer wrote:
>>> The rk3568 HDMI has an additional clock that needs to be enabled for the
>>> HDMI controller to work. This clock is not needed for the HDMI
>>>
On Mon, 14 Mar 2022 08:35:17 -0700, Tvrtko Ursulin wrote:
>
> >> Alternatively, all other uapi uses struct i915_engine_class_instance to
> >> address engines which uses u16:u16.
> >>
> >> How ugly it is to stuff a struct into u32 flags is the question... But you
> >> could at least use u16:u16 for
On Fri, Mar 04, 2022 at 09:34:14PM +0200, Andy Shevchenko wrote:
> In the fbtft_init_display() the init sequence is printed for
> the debug purposes. Unfortunately the current code doesn't take
> into account that values in the buffer are of the s16 type.
>
> Consider that and replace the
- Some DPU versions support inline rot90. It is supported only for
limited amount of UBWC formats.
- There are two versions of inline rotators, v1 (present on sm8250 and
sm7250) and v2 (sc7280). These versions differ in the list of supported
formats and in the scaler possibilities.
Changes in
This series:
1. Enables support of GuC to report error-state-capture
using a list of MMIO registers the driver registers
and GuC will dump, log and notify right before a GuC
triggered engine-reset event.
2. Updates the ADS blob creation to register said lists
of global,
On 2022-03-14 11:31, Robin Murphy wrote:
On 2022-03-13 12:56, Peter Geis wrote:
On Sun, Mar 13, 2022 at 6:13 AM Piotr Oniszczuk
wrote:
Wiadomość napisana przez Peter Geis w dniu
26.01.2022, o godz. 21:24:
The hdmi-cec clock must be 32khz in order for cec to work correctly.
Ensure after
This driver supports the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.
Signed-off-by: Biju Das
---
RFC->v1:
* Added "depends on ARCH_RENESAS || COMPILE_TEST" on KCONFIG
and dropped DRM as it is implied by DRM_BRIDGE
* Used devm_reset_control_get_exclusive()
The RZ/G2L MIPI DSI TX is embedded in the Renesas RZ/G2L family SoC's. It
can operate in DSI mode, with up to four data lanes.
Signed-off-by: Biju Das
---
RFC->v1:
* Added a ref to dsi-controller.yaml.
RFC:-
*
This patch series aims to support the MIPI DSI encoder found in the RZ/G2L
SoC. It currently supports DSI mode only.
This unit supports MIPI Alliance Specification for Display Serial Interface
(DSI) Specification. This unit provides a
solution for transmitting MIPI DSI compliant digital video
On 12/03/2022 04:16, Matt Atwood wrote:
On Thu, Mar 10, 2022 at 12:26:12PM +, Tvrtko Ursulin wrote:
On 10/03/2022 05:18, Matt Atwood wrote:
Newer platforms have DSS that aren't necessarily available for both
geometry and compute, two queries will need to exist. This introduces
the
On Mon, 14 Mar 2022 10:23:27 -0400
Alex Deucher wrote:
> On Fri, Mar 11, 2022 at 3:30 AM Pekka Paalanen wrote:
> >
> > On Thu, 10 Mar 2022 11:56:41 -0800
> > Rob Clark wrote:
> >
> > > For something like just notifying a compositor that a gpu crash
> > > happened, perhaps drm_event is more
On Mon, 14 Mar 2022 14:30:18 +0100
Geert Uytterhoeven wrote:
> On Mon, Mar 7, 2022 at 9:53 PM Geert Uytterhoeven
> wrote:
> > Introduce fourcc codes for color-indexed frame buffer formats with two,
> > four, and sixteen colors, and provide a mapping from bit per pixel and
> > depth to fourcc
Hi Julia
thanks for the patch.
Reviewed-by: Alain Volmat
Alain
On Mon, Mar 14, 2022 at 12:53:40PM +0100, Julia Lawall wrote:
> Various spelling mistakes in comments.
> Detected with the help of Coccinelle.
>
> Signed-off-by: Julia Lawall
>
> ---
> drivers/gpu/drm/sti/sti_gdp.c |2 +-
>
> -Original Message-
> From: Doug Anderson
> Sent: Monday, March 14, 2022 7:28 PM
> To: dmitry.barysh...@linaro.org
> Cc: Vinod Polimera ; Stephen Boyd
> ; quic_vpolimer ;
> devicet...@vger.kernel.org; dri-devel@lists.freedesktop.org;
> freedr...@lists.freedesktop.org;
> -Original Message-
> From: Doug Anderson
> Sent: Thursday, March 10, 2022 12:55 AM
> To: quic_vpolimer
> Cc: dri-devel ; linux-arm-msm m...@vger.kernel.org>; freedreno ;
> open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
> ; LKML ; Rob
> Clark ; Stephen Boyd ;
>
> -Original Message-
> From: Dmitry Baryshkov
> Sent: Tuesday, March 8, 2022 10:40 PM
> To: quic_vpolimer
> Cc: dri-devel@lists.freedesktop.org; linux-arm-...@vger.kernel.org;
> freedr...@lists.freedesktop.org; devicet...@vger.kernel.org; linux-
> ker...@vger.kernel.org;
Hi Ilia,
On Mon, Mar 14, 2022 at 3:39 PM Ilia Mirkin wrote:
> On Mon, Mar 14, 2022 at 10:06 AM Geert Uytterhoeven
> wrote:
> > On Mon, Mar 14, 2022 at 2:44 PM Ilia Mirkin wrote:
> > > On Mon, Mar 14, 2022 at 9:07 AM Geert Uytterhoeven
> > > wrote:
> > > > On Tue, Mar 8, 2022 at 8:57 AM Geert
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
This patch is dependent on below patch
https://patchwork.kernel.org/patch/12774067/
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7280.dtsi | 9
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
This patch is dependent on below patch
https://patchwork.kernel.org/patch/12774067/
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 9
use max clock during probe/bind sequence from the opp table.
The clock will be scaled down when framework sends an update.
Fixes: 25fdd5933("drm/msm: Add SDM845 DPU support")
Signed-off-by: Vinod Polimera
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
1 file changed, 8 insertions(+)
Drop the assigned clock rate property and vote on the mdp clock to max frequency
during bind/probe sequence.
Changes in v2:
- Remove assigned-clock-rate property and set mdp clk during resume sequence.
- Add fixes tag.
Changes in v3:
- Remove extra line after fixes tag.(Stephen Boyd)
- Add
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
This patch is dependent on below patch
https://patchwork.kernel.org/patch/12774067/
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9
Drop the assigned clock rate property and vote on the mdp clock as per
calculated value during the usecase.
This patch is dependent on below patch
https://patchwork.kernel.org/patch/12774067/
Signed-off-by: Vinod Polimera
Reviewed-by: Stephen Boyd
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 9
On Sun, 13 Mar 2022 13:38:51 +0100, Marek Vasut wrote:
> The i.MX8MP contains two syscon registers which are responsible
> for configuring the on-SoC DPI-to-LVDS serializer. Add DT binding
> which represents this serializer as a bridge.
>
> Signed-off-by: Marek Vasut
> Cc: Laurent Pinchart
>
On Mon, Mar 14, 2022 at 10:06 AM Geert Uytterhoeven
wrote:
>
> Hi Ilia,
>
> On Mon, Mar 14, 2022 at 2:44 PM Ilia Mirkin wrote:
> > On Mon, Mar 14, 2022 at 9:07 AM Geert Uytterhoeven
> > wrote:
> > > On Tue, Mar 8, 2022 at 8:57 AM Geert Uytterhoeven
> > > wrote:
> > > > On Mon, Mar 7, 2022 at
Hi Laurent,
Thanks for the feedback.
> Subject: Re: [RFC 22/28] drm: rcar-du: Add RZ/G2L DSI driver
>
> Hi Biju,
>
> Thank you for the patch.
>
> On Wed, Jan 12, 2022 at 05:46:06PM +, Biju Das wrote:
> > This driver supports the MIPI DSI encoder found in the RZ/G2L SoC. It
> > currently
On Fri, Mar 11, 2022 at 3:30 AM Pekka Paalanen wrote:
>
> On Thu, 10 Mar 2022 11:56:41 -0800
> Rob Clark wrote:
>
> > For something like just notifying a compositor that a gpu crash
> > happened, perhaps drm_event is more suitable. See
> > virtio_gpu_fence_event_create() for an example of
Hello,
this is another try to convince the relevant people that
devm_clk_get_enabled() is a nice idea. Compared to v7 (back in May 2021) this
series is rebased to v5.17-rc8 and converts quite some drivers that open code
devm_clk_get_enabled() up to now (patches #3 - #11).
A concern about
When a driver keeps a clock prepared (or enabled) during the whole
lifetime of the driver, these helpers allow to simplify the drivers.
Reviewed-by: Jonathan Cameron
Reviewed-by: Alexandru Ardelean
Signed-off-by: Uwe Kleine-König
---
drivers/clk/clk-devres.c | 31 ++
Allow to add an exit hook to devm managed clocks. Also use
clk_get_optional() in devm_clk_get_optional instead of open coding it.
The generalisation will be used in the next commit to add some more
devm_clk helpers.
Reviewed-by: Jonathan Cameron
Reviewed-by: Alexandru Ardelean
Signed-off-by:
devm_clk_get_enabled() returns a clock prepared and enabled and already
registers a devm exit handler to disable (and unprepare) the clock.
There is slight change in behavior as a failure to enable the clock
now results in an error message, too. Also the actual error code is added
to the message.
Hello Geert,
On 3/14/22 14:40, Geert Uytterhoeven wrote:
> Hi Javier,
>
> On Mon, Jan 31, 2022 at 9:12 PM Javier Martinez Canillas
> wrote:
>> Add support to convert 8-bit grayscale to reversed monochrome for drivers
>> that control monochromatic displays, that only have 1 bit per pixel depth.
Hi Ilia,
On Mon, Mar 14, 2022 at 2:44 PM Ilia Mirkin wrote:
> On Mon, Mar 14, 2022 at 9:07 AM Geert Uytterhoeven
> wrote:
> > On Tue, Mar 8, 2022 at 8:57 AM Geert Uytterhoeven
> > wrote:
> > > On Mon, Mar 7, 2022 at 10:23 PM Ilia Mirkin wrote:
> > > > On Mon, Mar 7, 2022 at 3:53 PM Geert
On 11.03.2022 10:40, Lucas De Marchi wrote:
> On Tue, Mar 08, 2022 at 10:17:42PM +0530, Balasubramani Vivekanandan wrote:
> > This patch is continuation of the effort to move all pointers in i915,
> > which at any point may be pointing to device memory or system memory, to
> > iosys_map interface.
Hi,
On Fri, Mar 11, 2022 at 1:22 AM Dmitry Baryshkov
wrote:
>
> On Fri, 11 Mar 2022 at 11:06, Vinod Polimera
> wrote:
> >
> >
> >
> > > -Original Message-
> > > From: Stephen Boyd
> > > Sent: Wednesday, March 9, 2022 1:36 AM
> > > To: quic_vpolimer ;
> > > devicet...@vger.kernel.org;
On Mon, Mar 14, 2022 at 9:07 AM Geert Uytterhoeven wrote:
>
> Hi Ilia,
>
> On Tue, Mar 8, 2022 at 8:57 AM Geert Uytterhoeven
> wrote:
> > On Mon, Mar 7, 2022 at 10:23 PM Ilia Mirkin wrote:
> > > On Mon, Mar 7, 2022 at 3:53 PM Geert Uytterhoeven
> > > wrote:
> > > > diff --git
Hi Javier,
On Mon, Jan 31, 2022 at 9:12 PM Javier Martinez Canillas
wrote:
> Add support to convert 8-bit grayscale to reversed monochrome for drivers
> that control monochromatic displays, that only have 1 bit per pixel depth.
>
> This helper function was based on
Hi Andy,
On Mon, 14 Mar 2022 at 11:02, Andy Yan wrote:
>Remember you said our downstream vop2 driver is very slow on weston.
>
> Would you please share the case you run ? or how can i test frame rate
> on weston?
We were able to observe this by just using either waylandsink (using
dmabuf
On Mon, Mar 7, 2022 at 9:53 PM Geert Uytterhoeven wrote:
> Introduce fourcc codes for color-indexed frame buffer formats with two,
> four, and sixteen colors, and provide a mapping from bit per pixel and
> depth to fourcc codes.
>
> As the number of bits per pixel is less than eight, these rely
Hi Ilia,
On Tue, Mar 8, 2022 at 8:57 AM Geert Uytterhoeven wrote:
> On Mon, Mar 7, 2022 at 10:23 PM Ilia Mirkin wrote:
> > On Mon, Mar 7, 2022 at 3:53 PM Geert Uytterhoeven
> > wrote:
> > > diff --git a/tests/util/pattern.c b/tests/util/pattern.c
> > > index 953bf95492ee150c..42d75d700700dc3d
Hi Sascha Hauer
From: Sascha Hauer
Date: 2022-03-11 16:33:21
To: dri-devel@lists.freedesktop.org
Cc:
linux-arm-ker...@lists.infradead.org,linux-rockc...@lists.infradead.org,devicet...@vger.kernel.org,ker...@pengutronix.de,Andy
Yan ,Benjamin Gaignard
,Michael Riesch
,Sandy Huang ,"Heiko
Hi Rob and Linus,
On Mon, 7 Mar 2022 at 14:07, Naresh Kamboju wrote:
>
> Hi Rob,
>
> On Sun, 20 Feb 2022 at 00:02, Rob Clark wrote:
> >
> > From: Rob Clark
> >
> > Avoid going down devfreq paths on devices where devfreq is not
> > initialized.
> >
> > Reported-by: Linux Kernel Functional
From: Thomas Zimmermann
commit 3755d35ee1d2454b20b8a1e20d790e56201678a4 upstream.
As reported in [1], DRM_PANEL_EDP depends on DRM_DP_HELPER. Select
the option to fix the build failure. The error message is shown
below.
arm-linux-gnueabihf-ld: drivers/gpu/drm/panel/panel-edp.o: in function
From: Thomas Zimmermann
commit 3755d35ee1d2454b20b8a1e20d790e56201678a4 upstream.
As reported in [1], DRM_PANEL_EDP depends on DRM_DP_HELPER. Select
the option to fix the build failure. The error message is shown
below.
arm-linux-gnueabihf-ld: drivers/gpu/drm/panel/panel-edp.o: in function
On 13.03.2022 20:45, Andi Shyti wrote:
Hi Andrzej,
I'm sorry, but I'm not fully understanding,
+struct intel_gt *intel_gt_sysfs_get_drvdata(struct device *dev,
+ const char *name)
+{
+ struct kobject *kobj = >kobj;
+
+ /*
+* We
On Mon, Mar 14, 2022, 12:53 Julia Lawall wrote:
> Various spelling mistakes in comments.
> Detected with the help of Coccinelle.
>
> Signed-off-by: Julia Lawall
>
> ---
> drivers/gpu/drm/bridge/analogix/analogix_dp_core.c |4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff
Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: Julia Lawall
---
drivers/gpu/drm/amd/display/dc/bios/command_table.c |6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: Julia Lawall
---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
Various spelling mistakes in comments.
Detected with the help of Coccinelle.
---
drivers/base/devres.c |4 ++--
drivers/clk/qcom/gcc-sm6125.c |2 +-
drivers/clk/ti/clkctrl.c|2 +-
Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: Julia Lawall
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: Julia Lawall
---
drivers/gpu/drm/sti/sti_gdp.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sti/sti_gdp.c b/drivers/gpu/drm/sti/sti_gdp.c
index
Various spelling mistakes in comments.
Detected with the help of Coccinelle.
Signed-off-by: Julia Lawall
---
drivers/gpu/drm/amd/pm/amdgpu_pm.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index
1 - 100 of 126 matches
Mail list logo
