On Fri, 1 Dec 2023 at 03:41, Paloma Arellano wrote:
>
> When the irq callback returns a value other than zero,
> modify vblank_refcount by performing the inverse
> operation of its corresponding if-else condition.
I think it might be better to follow Bjorn's suggestion: once we have
the lock, we
On Fri, 1 Dec 2023 at 03:41, Paloma Arellano wrote:
>
> There is currently a race condition occuring when accessing
> vblank_refcount. Therefore, vblank irq timeouts may occur.
>
> Avoid any vblank irq timeouts by stablizing the use of vblank_refcount.
>
> Changes from prior versions:
>v2: -
On Fri, 1 Dec 2023 at 03:31, Jessica Zhang wrote:
>
> This series drops the frame_count and enable parameters (as they're always
> set to the same value). It also sets input_sel=0x1 for INTF.
>
> Signed-off-by: Jessica Zhang
> ---
> Jessica Zhang (2):
> drm/msm/dpu: Drop enable and
On Fri, 1 Dec 2023 at 03:31, Jessica Zhang wrote:
>
> Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they
> are always set to the same values.
>
> In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
> frame_count is always set to the same value.
>
> Fixes:
On Fri, 1 Dec 2023 at 03:31, Jessica Zhang wrote:
>
> Set the input_sel bit for encoders as it was missed in the initial
> implementation.
>
> Reported-by: Rob Clark
> Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
> Closes:
On Fri, 1 Dec 2023 at 02:41, Abhinav Kumar wrote:
>
>
>
> On 8/30/2023 5:11 PM, Dmitry Baryshkov wrote:
> > On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar
> > wrote:
> >>
> >> Add an API dpu_encoder_helper_phys_setup_cdm() which can be used by
> >> the writeback encoder to setup the CDM block.
>
On Fri, 1 Dec 2023 at 02:50, Abhinav Kumar wrote:
>
>
>
> On 8/30/2023 5:24 PM, Dmitry Baryshkov wrote:
> > On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar
> > wrote:
> >>
> >> On chipsets where CDM block is not available OR where support has
> >> not been added yet do not allow YUV formats for
On Fri, 1 Dec 2023 at 01:36, Abhinav Kumar wrote:
>
>
>
> On 8/30/2023 5:00 PM, Dmitry Baryshkov wrote:
> > On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar
> > wrote:
> >>
> >> CDM block comes with its own set of registers and operations
> >> which can be done. In-line with other hardware
Hi Linus,
Weekly fixes, mostly amdgpu fixes with a scattering of nouveau, i915,
and a couple of reverts. Hopefully it will quieten down in coming
weeks.
Regards,
Dave.
drm-fixes-2023-12-01:
drm fixes for 6.7-rc4
drm:
- Revert unexport of prime helpers for fd/handle conversion
dma_resv:
- Do
Hi Tomi,
Thank you for the patches!
On 09/11/23 13:07, Tomi Valkeinen wrote:
> While working on the TI BSP kernel, adding bootload splash screen
> support, I noticed some issues with the driver and opportunities for
> cleanups and improvements.
>
> Tomi
>
> Signed-off-by: Tomi Valkeinen
>
"Zeng, Oak" writes:
> See inline comments
>
>> -Original Message-
>> From: dri-devel On Behalf Of
>> zhuweixi
>> Sent: Thursday, November 30, 2023 5:48 AM
>> To: Christian König ; Zeng, Oak
>> ; Christian König ; linux-
>> m...@kvack.org; linux-ker...@vger.kernel.org;
zhuweixi writes:
> Glad to know that there is a common demand for a new syscall like
> hmadvise(). I expect it would also be useful for homogeneous NUMA
> cases. Credits to cudaMemAdvise() API which brought this idea to
> GMEM's design.
It's not clear to me that this would need to be a new
See inline comments
> -Original Message-
> From: dri-devel On Behalf Of
> zhuweixi
> Sent: Thursday, November 30, 2023 5:48 AM
> To: Christian König ; Zeng, Oak
> ; Christian König ; linux-
> m...@kvack.org; linux-ker...@vger.kernel.org; a...@linux-foundation.org;
> Danilo Krummrich ;
Nothing else to be done on this front from Xe perspective.
Signed-off-by: Rodrigo Vivi
---
Documentation/gpu/rfc/xe.rst | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/Documentation/gpu/rfc/xe.rst b/Documentation/gpu/rfc/xe.rst
index
The must-have part of the documentation was already added to the existing
/gpu/drm-vm-bind-async. The other extra discussion around GPUVM helpers
are currently active in the community. None of those discussion should
block Xe since documentation, specially around locking was completed in
a
Current drm-xe-next doesn't have any drm/scheduler patch that is not
already accepted in drm-misc-next. This completed this goal with
the consensus of how the drm/scheduler fits to the fw scheduling and
the relationship between drm_gpu_scheduler and drm_sched_entity.
Signed-off-by: Rodrigo Vivi
Let's move more items from the 'WIP' section to the 'Completed' one.
When Xe was an initial experiment we had written down our goals and
promises in this RFC with the goal to work with and contribute back
to key common DRM items such as drm_scheduler, gpuvm, drm_exec, and
establish documentations
As already indicated in this block, the consensus was already
reached out and documented as:
The ASYNC VM_BIND document
However this was item was not moved to the completed section.
Let's move and clean up the WIP block.
Signed-off-by: Rodrigo Vivi
---
Documentation/gpu/rfc/xe.rst | 24
From: Matthew Brost
No DRM scheduler changes required, drivers just return NULL in run_job
vfunc.
The rough consensus is that no helper or extra scaffolding is needed
around long-running jobs and no further changes to drm-scheduler.
At least for now. Other drivers that currently do
On Thu, Nov 30, 2023 at 05:40:55PM -0800, Paloma Arellano wrote:
> Add a missing mutex lock to control vblank irq. Thus prevent race
> conditions when registering/unregistering the irq callback.
>
I'm guessing that the mutex is needed because vblank_refcount, while
being an atomic_t, doesn't
Thanks! I am planning to present GMEM in Linux MM Alignment Sessions so I can
collect more input from the mm developers.
@Christian @Oak I will also send you invitations once a presentation is
scheduled. :)
-Weixi
-Original Message-
From: David Hildenbrand
Sent: Thursday, November
From your argument on KVM I can see that the biggest miscommunication between
us is that you believed that GMEM wanted to share the whole address space. No,
it is not the case. GMEM is only providing coordination via certain mmap()
calls. So you are raising a case supporting GMEM again --
Hi,
On 2023/11/28 18:45, Thomas Zimmermann wrote:
The udl driver is the only caller of drm_plane_helper_atomic_check().
Move the function into the driver. No functional changes.
Signed-off-by: Thomas Zimmermann
---
drivers/gpu/drm/drm_plane_helper.c | 32 --
Add a missing mutex lock to control vblank irq. Thus prevent race
conditions when registering/unregistering the irq callback.
v2: Slightly changed wording of commit message
v3: Mistakenly did not change wording in last version. It is done now.
Signed-off-by: Paloma Arellano
---
When the irq callback returns a value other than zero,
modify vblank_refcount by performing the inverse
operation of its corresponding if-else condition.
Signed-off-by: Paloma Arellano
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 9 +++--
There is currently a race condition occuring when accessing
vblank_refcount. Therefore, vblank irq timeouts may occur.
Avoid any vblank irq timeouts by stablizing the use of vblank_refcount.
Changes from prior versions:
v2: - Slightly changed wording of patch #2 commit message
v3: -
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Signed-off-by: Jessica Zhang
---
Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they
are always set to the same values.
In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as
frame_count is always set to the same value.
Fixes: 7b37523fb1d1 ("drm/msm/dpu: Move MISR methods to dpu_hw_util")
This series drops the frame_count and enable parameters (as they're always
set to the same value). It also sets input_sel=0x1 for INTF.
Signed-off-by: Jessica Zhang
---
Jessica Zhang (2):
drm/msm/dpu: Drop enable and frame_count parameters from
dpu_hw_setup_misr()
drm/msm/dpu: Set
To add a missing mutex lock to control vblank irq. To prevent race
conditions when registering/unregistering the irq callback.
Signed-off-by: Paloma Arellano
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 6 ++
There is currently a race condition occuring when accessing
vblank_refcount. Therefore, vblank irq timeouts may occur.
Avoid any vblank irq timeouts by stablizing the use of vblank_refcount.
Changes from prior versions:
v2: - Slightly changed wording of patch #2 commit message
Paloma
When the irq callback returns a value other than zero,
modify vblank_refcount by performing the inverse
operation of its corresponding if-else condition.
Signed-off-by: Paloma Arellano
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 9 +++--
To add a missing mutex lock to control vblank irq. To prevent race
conditions when registering/unregistering the irq callback.
Signed-off-by: Paloma Arellano
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 6 ++
When the irq callback returns a value other than zero,
modify vblank_refcount by performing the inverse
operation of its corresponding if-else condition.
Signed-off-by: Paloma Arellano
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 9 +++--
There is currently a race condition occuring when accessing
vblank_refcount. Therefore, vblank irq timeouts may occur.
Avoid any vblank irq timeouts by stablizing the use of vblank_refcount.
Paloma Arellano (2):
drm/msm/dpu: Modify vblank_refcount if error in callback
drm/msm/dpu: Add mutex
On Thu, Nov 30, 2023 at 05:07:40PM -0300, André Almeida wrote:
> From: Pekka Paalanen
>
> Specify how the atomic state is maintained between userspace and
> kernel, plus the special case for async flips.
>
> Signed-off-by: Pekka Paalanen
> Signed-off-by: André Almeida
> ---
>
> This is a
On 8/30/2023 5:24 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
On chipsets where CDM block is not available OR where support has
not been added yet do not allow YUV formats for writeback block.
Signed-off-by: Abhinav Kumar
---
; {.nentry = ARRAY_SIZE(sc7180_qos_linear),
> .entries = sc7180_qos_linear
>
> ---
> base-commit: 3cd3fe06ff81cfb3a969acb12a56796cff5af23d
> change-id: 20231130-sc8180x-dpu-safe-lut-ffd0df221d67
>
> Best regards,
> --
> Bjorn Andersson
>
On 8/30/2023 5:23 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
Reserve CDM blocks for writeback if the format of the output fb
is YUV. At the moment, the reservation is done only for writeback
but can easily be extended by relaxing the checks once other
On 8/30/2023 5:11 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
Add an API dpu_encoder_helper_phys_setup_cdm() which can be used by
the writeback encoder to setup the CDM block.
Currently, this is defined and used within the writeback's physical
encoder
x, 0x0},
+ .safe_lut_tbl = {0xfff0, 0xf000, 0x},
.qos_lut_tbl = {
{.nentry = ARRAY_SIZE(sc7180_qos_linear),
.entries = sc7180_qos_linear
---
base-commit: 3cd3fe06ff81cfb3a969acb12a56796cff5af23d
change-id: 20231130-sc8180x-dpu-safe-lut-ffd0df22
_CHIP_IDS(0x0608),
+ .chip_ids = ADRENO_CHIP_IDS(0x06080001),
.family = ADRENO_6XX_GEN2,
.revn = 680,
.fw = {
---
base-commit: 3cd3fe06ff81cfb3a969acb12a56796cff5af23d
change-id: 20231130-adreno-a680-1-639717a53b56
Best regards,
--
Bjorn Andersson
> As far as i can tell, its only if we started resetting / wedging right after
> this
> queued worker got started.
alan: hope Daniele can proof read my tracing and confirm if got it right.
On Thu, 2023-11-30 at 16:18 -0500, Vivi, Rodrigo wrote:
> On Wed, Nov 29, 2023 at 04:20:13PM -0800, Alan Previn wrote:
alan:snip
> > +
> > if (unlikely(disabled)) {
> > release_guc_id(guc, ce);
> > __guc_context_destroy(ce);
> > - return;
> > +
On 8/30/2023 5:14 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
In preparation of setting up CDM block, add the logic to disable it
properly during encoder cleanup.
Signed-off-by: Abhinav Kumar
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8
On 8/30/2023 5:12 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
CDM block will need its own logic to program the flush and active
bits in the dpu_hw_ctl layer.
Make necessary changes in dpu_hw_ctl to support CDM programming.
Signed-off-by: Abhinav Kumar
On 8/30/2023 5:06 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
Even though there is usually only one CDM block, it can be
used by either HDMI, DisplayPort OR Writeback interfaces.
Hence its allocation needs to be tracked properly by the
resource manager
On 8/30/2023 4:48 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
Add the RM APIs necessary to initialize and allocate CDM
blocks by the rest of the DPU pipeline.
... to be used by the rest?
Yes, thanks.
Signed-off-by: Abhinav Kumar
---
On 8/30/2023 5:00 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:50, Abhinav Kumar wrote:
CDM block comes with its own set of registers and operations
which can be done. In-line with other hardware sub-blocks, this
change adds the dpu_hw_cdm abstraction for the CDM block.
On Wed, Nov 29, 2023 at 10:47 PM Luben Tuikov wrote:
>
> On 2023-11-29 22:36, Luben Tuikov wrote:
> > On 2023-11-29 15:49, Alex Deucher wrote:
> >> On Wed, Nov 29, 2023 at 3:10 PM Alex Deucher wrote:
> >>>
> >>> Actually I think I see the problem. I'll try and send out a patch
> >>> later today
DP2.1 Specs added new DPCDs definitions for square pattern configs[1]
These new definitions are used for UHBR Source Transmitter
Equalizations tests[2]. Add the 3 new values for square pattern.
v2: rebase
[1]: DP2.1 Specs - 2.12.3.6.5 Square Pattern
[2]: DP2.1 PHY CTS specs - 4.3 UHBR Source
On 11/30/2023 2:47 PM, Paloma Arellano wrote:
Trigger a devcoredump to dump dpu registers and capture the drm atomic
state when the frame_done_timer timeouts.
v2: Optimize the format in which frame_done_timeout_cnt is incremented
v3: Describe parameter frame_done_timeout_cnt in
Trigger a devcoredump to dump dpu registers and capture the drm atomic
state when the frame_done_timer timeouts.
v2: Optimize the format in which frame_done_timeout_cnt is incremented
v3: Describe parameter frame_done_timeout_cnt in dpu_encoder_virt
Reported-by: kernel test robot
Closes:
Hi Andy,
Am Donnerstag, 30. November 2023, 13:25:00 CET schrieb Andy Yan:
> From: Andy Yan
>
> Add a Rockchip RK3588 compatible
>
> Signed-off-by: Andy Yan
> ---
>
> (no changes since v1)
>
> Documentation/devicetree/bindings/iommu/rockchip,iommu.yaml | 1 +
> 1 file changed, 1
On 8/30/2023 3:57 PM, Dmitry Baryshkov wrote:
On Thu, 31 Aug 2023 at 01:49, Abhinav Kumar wrote:
Add CDM blocks to the sc7280 dpu_hw_catalog to support
YUV format output from writeback block.
Signed-off-by: Abhinav Kumar
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 9
On Mon, 16 Oct 2023 22:38:20 +, Justin Stitt wrote:
> `strncpy` is deprecated for use on NUL-terminated destination strings
> [1] and as such we should prefer more robust and less ambiguous string
> interfaces.
>
> We should NUL-pad as there are full struct copies happening in places:
> |
Hi Dave, Sima,
Fixes for 6.7. Mostly fixes for new IPs. Also including a revert of
the unexport of the currently unused prime helpers for fd/handle conversion
since amdgpu will use them in 6.8 so I see no reason to remove them only
to re-add them again in 6.8.
The following changes since
On Wed, Nov 29, 2023 at 10:36 PM Luben Tuikov wrote:
>
> On 2023-11-29 15:49, Alex Deucher wrote:
> > On Wed, Nov 29, 2023 at 3:10 PM Alex Deucher wrote:
> >>
> >> Actually I think I see the problem. I'll try and send out a patch
> >> later today to test.
> >
> > Does the attached patch fix it?
On 11/30/2023 11:21 AM, Rob Clark wrote:
From: Rob Clark
The UBWC settings need to match between the display and GPU. When we
updated the GPU settings, we forgot to make the corresponding update on
the display side.
Reported-by: Steev Klimaszewski
Fixes: 07e6de738aa6 ("drm/msm/a690: Fix
On Thu, Nov 30, 2023 at 1:21 PM Rob Clark wrote:
>
> From: Rob Clark
>
> The UBWC settings need to match between the display and GPU. When we
> updated the GPU settings, we forgot to make the corresponding update on
> the display side.
>
> Reported-by: Steev Klimaszewski
> Fixes: 07e6de738aa6
On Wed, Nov 29, 2023 at 04:20:13PM -0800, Alan Previn wrote:
> If we are at the end of suspend or very early in resume
> its possible an async fence signal (via rcu_call) is triggered
> to free_engines which could lead us to the execution of
> the context destruction worker (after a prior worker
Add support for the Adreno 305B GPU that is found in MSM8226(v2) SoC.
Previously this was mistakenly claimed to be supported but using wrong
a configuration.
In MSM8226v1 there's also a A305B but with chipid 0x03000510 which
should work with the same configuration but due to lack of hardware for
Some GPUs like the Adreno A305B has a patchid higher than 9, in this
case 18. Make sure the regexes can account for that.
Signed-off-by: Luca Weiss
---
Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git
| 5 +++
5 files changed, 71 insertions(+), 10 deletions(-)
---
base-commit: 32bbbdc6dbe6ca65a3e3e2ed2ca3c562793e7797
change-id: 20231130-msm8226-gpu-c2ff8473a9ff
Best regards,
--
Luca Weiss
The msm8226 SoC contains an Adreno 305B. Add a node to configure it.
Signed-off-by: Luca Weiss
---
arch/arm/boot/dts/qcom/qcom-msm8226.dtsi | 40
1 file changed, 40 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/qcom-msm8226.dtsi
Hello dri maintainers/developers,
This is a 31-day syzbot report for the dri subsystem.
All related reports/information can be found at:
https://syzkaller.appspot.com/upstream/s/dri
During the period, 1 new issues were detected and 0 were fixed.
In total, 15 issues are still open and 30 have
From: Pekka Paalanen
Specify how the atomic state is maintained between userspace and
kernel, plus the special case for async flips.
Signed-off-by: Pekka Paalanen
Signed-off-by: André Almeida
---
This is a standalone patch from the following serie, the other patches are
already merged:
On Thu, Nov 30, 2023 at 04:58:48PM +0200, Jani Nikula wrote:
>
> Hi Dave & Sima -
>
> i915 fixes for v6.7-rc4.
>
> drm-intel-fixes-2023-11-30:
> drm/i915 fixes for v6.7-rc4:
> - Mark internal GSC engine with reserved uabi class
> - Take VGA converters into account in eDP probe
> - Fix
On Thu, 2023-11-30 at 22:58 +0800, kernel test robot wrote:
> If you fix the issue in a separate patch/commit (i.e. not just a new
> version of
> the same patch/commit), kindly add following tags
> > Reported-by: kernel test robot
> > Closes:
From: Rob Clark
The UBWC settings need to match between the display and GPU. When we
updated the GPU settings, we forgot to make the corresponding update on
the display side.
Reported-by: Steev Klimaszewski
Fixes: 07e6de738aa6 ("drm/msm/a690: Fix reg values for a690")
Signed-off-by: Rob Clark
Hi Paloma,
kernel test robot noticed the following build warnings:
[auto build test WARNING on drm-misc/drm-misc-next]
[also build test WARNING on linus/master v6.7-rc3 next-20231130]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest
This patch introduces an initial KUnit test suite for GEM objects
backed by shmem buffers.
Suggested-by: Javier Martinez Canillas
Signed-off-by: Marco Pagani
v5:
- using __drm_kunit_helper_alloc_drm_device() to avoid local struct
v4:
- Add missing MMU dependency for DRM_GEM_SHMEM_HELPER
Applied. Thanks!
On Tue, Aug 8, 2023 at 2:08 PM Nikita Zhandarovich
wrote:
>
> In the unlikely event of radeon_ring_lock() failing, its errno return
> value should be processed. This patch checks said return value and
> prints a debug message in case of an error.
>
> Found by Linux Verification
Applied. Thanks!
On Wed, Nov 29, 2023 at 10:28 AM Nikita Zhandarovich
wrote:
>
> It may be possible, albeit unlikely, to encounter integer overflow
> during the multiplication of several unsigned int variables, the
> result being assigned to a variable 'size' of wider type.
>
> Prevent this
Applied. Thanks!
On Wed, Nov 29, 2023 at 10:28 AM Nikita Zhandarovich
wrote:
>
> While improbable, there may be a chance of hitting integer
> overflow when the result of radeon_get_ib_value() gets shifted
> left.
>
> Avoid it by casting one of the operands to larger data type (u64).
>
> Found
A CPU job is a type of job that performs operations that requires CPU
intervention. A copy performance query job is a job that copy the complete
or partial result of a query to a buffer. In order to copy the result of
a performance query to a buffer, we need to get the values from the
performance
A CPU job is a type of job that performs operations that requires CPU
intervention. A copy timestamp query job is a job that copy the complete
or partial result of a query to a buffer. As V3D doesn't provide any
mechanism to obtain a timestamp from the GPU, it is a job that needs
CPU intervention.
A CPU job is a type of job that performs operations that requires CPU
intervention. An indirect CSD job is a job that, when executed in the
queue, will map the indirect buffer, read the dispatch parameters, and
submit a regular dispatch. Therefore, it is a job that needs CPU
intervention.
So,
A CPU job is a type of job that performs operations that requires CPU
intervention. A reset timestamp job is a job that resets the timestamp
queries based on the value offset of the first query. As V3D doesn't
provide any mechanism to obtain a timestamp from the GPU, it is a job
that needs CPU
A CPU job is a type of job that performs operations that requires CPU
intervention. A reset performance query job is a job that resets the
performance queries by resetting the values of the perfmons. Moreover,
we also reset the syncobjs related to the availability of the query.
So, create a user
A CPU job is a type of job that performs operations that requires CPU
intervention. A timestamp query job is a job that calculates the
query timestamp and updates the query availability by signaling a
syncobj. As V3D doesn't provide any mechanism to obtain a timestamp
from the GPU, it is a job
From: Melissa Wen
Create a new type of job, a CPU job. A CPU job is a type of job that
performs operations that requires CPU intervention. The overall idea is
to use user extensions to enable different types of CPU job, allowing the
CPU job to perform different operations according to the type
For the indirect CSD CPU job, we will need to access the internal
contents of the BO with the dispatch parameters. Therefore, create
methods to allow the mapping and unmapping of the BO.
Signed-off-by: Maíra Canal
Reviewed-by: Iago Toral Quiroga
---
drivers/gpu/drm/v3d/v3d_bo.c | 18
From: Melissa Wen
Detach CSD job setup from CSD submission ioctl to reuse it in CPU
submission ioctl for indirect CSD job.
Signed-off-by: Melissa Wen
Co-developed-by: Maíra Canal
Signed-off-by: Maíra Canal
Reviewed-by: Iago Toral Quiroga
---
drivers/gpu/drm/v3d/v3d_submit.c | 68
Currently, v3d_get_extensions() only parses multisync data and assigns
it to the `struct v3d_submit_ext`. But, to implement the CPU job with
user extensions, we want v3d_get_extensions() to be able to parse CPU
job data and assign it to the `struct v3d_cpu_job`.
Therefore, allow the function
We want to allow the IOCTLs to allocate the job without initiating it.
This will be useful for the CPU job submission IOCTL, as the CPU job has
the need to use information from the user extensions. Currently, the
user extensions are parsed before the job allocation, making it
impossible to fill
Create tracepoints to track the three major events of a CPU job
lifetime:
1. Submission of a `v3d_submit_cpu` IOCTL
2. Beginning of the execution of a CPU job
3. Ending of the execution of a CPU job
Signed-off-by: Maíra Canal
Reviewed-by: Iago Toral Quiroga
---
Currently, two multisync extensions can be added to the same job and
only the last multisync extension will be used. To avoid this
vulnerability, don't allow two multisync extensions in the same job.
Signed-off-by: Maíra Canal
Reviewed-by: Iago Toral Quiroga
---
From: Melissa Wen
Instead of checking if the job is NULL every time we call the function,
check it inside the function.
Signed-off-by: Melissa Wen
Signed-off-by: Maíra Canal
Reviewed-by: Iago Toral Quiroga
---
drivers/gpu/drm/v3d/v3d_submit.c | 9 +
1 file changed, 5 insertions(+),
From: Melissa Wen
We will include a new job submission type, the CPU job submission. For
readability and maintability, separate the job submission IOCTLs and
related operations from v3d_gem.c.
Minor fix in the CSD submission kernel doc:
CSD (texture formatting) -> CSD (compute shader).
From: Melissa Wen
IOCTLs related to BO operations reside on the file v3d_bo.c. The wait BO
ioctl is the only IOCTL regarding BOs that is placed in a different file.
So, move it to the v3d_bo.c file.
Signed-off-by: Melissa Wen
Signed-off-by: Maíra Canal
Reviewed-by: Iago Toral Quiroga
---
This patchset implements the basic infrastructure for a new type of
V3D job, a CPU job. A CPU job is a job that requires CPU intervention.
It would be nice to perform this operations on the kernel space as we
can attach multiple in/out syncobjs to it.
Why we want a CPU job on the kernel?
From: Melissa Wen
v3d_mmu_get_offset header was added but the function was never defined.
Just remove it.
Signed-off-by: Melissa Wen
Signed-off-by: Maíra Canal
Reviewed-by: Iago Toral Quiroga
---
drivers/gpu/drm/v3d/v3d_drv.h | 2 --
1 file changed, 2 deletions(-)
diff --git
On Tue, Nov 28, 2023 at 12:12:08PM +0100, Andrzej Hajda wrote:
> On 28.11.2023 04:47, Paz Zcharya wrote:
> >
> > On Mon, Nov 27, 2023 at 8:20 PM Paz Zcharya wrote:
> > >
> > > On 21.11.2023 13:06, Andrzej Hajda wrote:
> > >
> > > > The simplest approach would be then do the same as in case of
There was an assumption that for iGPU there should be a 1:1 mapping
of GGTT to physical address pointing to actual framebuffer.
This assumption is not valid anymore for MTL.
Fix that by checking GGTT to determine the phys address.
The following algorithm for phys_base should be valid for all
On 30.11.23 16:57, Frieder Schrempf wrote:
> Hi Emil,
>
> On 27.10.23 14:22, Emil Abildgaard Svendsen wrote:
>> [Sie erhalten nicht häufig E-Mails von e...@bang-olufsen.dk. Weitere
>> Informationen, warum dies wichtig ist, finden Sie unter
>> https://aka.ms/LearnAboutSenderIdentification ]
>>
The function below is used only within this source file, but is not static.
drivers/gpu/drm/imagination/pvr_vm.c:542:6: error: no previous prototype for
'pvr_gpuvm_free' [-Werror=missing-prototypes]
542 | void pvr_gpuvm_free(struct drm_gpuvm *gpuvm)
Make it static.
Reported-by: Arnd Bergmann
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