Commit c472d828348caf ("drm/nouveau/gsp: move subdev/engine impls to
subdev/gsp/rm/r535/") moves GSP-RM message queue implementation in
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c to versioned path in
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/gsp.c, but forgets to
update kernel-doc referen
From: Markus Elfring
Date: Tue, 10 Jun 2025 07:42:40 +0200
The label “cleanup” was used to jump to another pointer check despite of
the detail in the implementation of the function
“dm_validate_stream_and_context”
that it was determined already that corresponding variables contained
still null p
On 6/6/25 7:45 PM, Diogo Ivo wrote:
Add the NVJPG power-domain node in order to support the NVJPG
accelerator.
Signed-off-by: Diogo Ivo
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
b/arch/arm6
On 6/10/25 12:20, Alexey Kardashevskiy wrote:
On 31/5/25 02:23, Xu Yilun wrote:
On Fri, May 30, 2025 at 12:29:30PM +1000, Alexey Kardashevskiy wrote:
On 30/5/25 00:41, Xu Yilun wrote:
FLR to a bound device is absolutely fine, just break the CC state.
Sometimes it is exactly what host need
856173186d5922899d65686
change-id: 20250609-msm-dp-mst-cddc2f61daee
prerequisite-message-id:
<20250529-hpd_display_off-v1-0-ce33bac29...@oss.qualcomm.com>
prerequisite-patch-id: a1f426b99b4a99d63daa9902cde9ee38ae1128d1
prerequisite-patch-id: ae9e0a0db8edd05da06f9673e9de56761
On 14/5/25 13:20, Xu Yilun wrote:
On Mon, May 12, 2025 at 07:30:21PM +1000, Alexey Kardashevskiy wrote:
On 10/5/25 13:47, Xu Yilun wrote:
On Fri, May 09, 2025 at 03:43:18PM -0300, Jason Gunthorpe wrote:
On Sat, May 10, 2025 at 12:28:48AM +0800, Xu Yilun wrote:
On Fri, May 09, 2025 at 07:
On 31/5/25 02:23, Xu Yilun wrote:
On Fri, May 30, 2025 at 12:29:30PM +1000, Alexey Kardashevskiy wrote:
On 30/5/25 00:41, Xu Yilun wrote:
FLR to a bound device is absolutely fine, just break the CC state.
Sometimes it is exactly what host need to stop CC immediately.
The problem is in VFI
On 2025/6/10 0:07, Dmitry Baryshkov wrote:
On Mon, Jun 09, 2025 at 08:21:19PM +0800, Yongxing Mou wrote:
Add support for Multi-stream transport for MSM chipsets that allow
a single instance of DP controller to send multiple streams.
This series has been validated on sa8775p ride platform usi
On Tue, Jun 10, 2025 at 12:48:09PM +1000, Stephen Rothwell wrote:
> After merging the drm-misc tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> drivers/accel/qaic/qaic_ras.c: In function 'decode_ras_msg':
> drivers/accel/qaic/qaic_ras.c:325:17: error: implicit declarati
On 6/6/25 7:45 PM, Diogo Ivo wrote:
Add support for booting and using NVJPG on Tegra210 to the Host1x
and TegraDRM drivers. This driver only supports the new TegraDRM uAPI.
Hello Diogo -- I'm happy to see this driver!
Signed-off-by: Diogo Ivo
---
drivers/gpu/drm/tegra/Makefile | 1 +
d
Hi all,
After merging the drm-misc tree, today's linux-next build (x86_64
allmodconfig) failed like this:
drivers/accel/qaic/qaic_ras.c: In function 'decode_ras_msg':
drivers/accel/qaic/qaic_ras.c:325:17: error: implicit declaration of function
'pci_printk'; did you mean 'pci_intx'? [-Wimplicit-
On 09-06-25, 09:22, Guilherme Giacomo Simoes wrote:
> Commit 38559da6afb2 ("rust: module: introduce `authors` key") introduced
> a new `authors` key to support multiple module authors, while keeping
> the old `author` key for backward compatibility.
>
> Now that all in-tree modules have migrated t
On 6/9/25 20:46, Felix Kuehling wrote:
On 2025-06-09 5:36, francisco_flynn wrote:
HMM device memory is allocated at the top of
iomem_resource, when iomem_resource is larger than
GPU device's dma mask, after devm_memremap_pages,
max_pfn will also be update and exceed device's
dma mask, when there
Hi,
On Fri, Jun 6, 2025 at 2:06 AM Jani Nikula wrote:
>
> Use firmware node based lookups for panel followers, to make the code
> independent of OF and device tree, and make it work also for ACPI with
> an appropriate _DSD.
>
> ASL example:
>
> Package (0x02)
> {
>
From: Lad Prabhakar
Simplify the high-speed clock frequency (HSFREQ) calculation by removing
the redundant multiplication and division by 8. The updated equation:
hsfreq = mode->clock * bpp / dsi->lanes;
produces the same result while improving readability and clarity.
Additionally, update
From: Lad Prabhakar
Document support for the DU IP found on the Renesas RZ/V2N (R9A09G056) SoC.
The DU IP is functionally identical to that on the RZ/V2H(P) SoC, so no
driver changes are needed. The existing `renesas,r9a09g057-du` compatible
will be used as a fallback for the RZ/V2N SoC.
Signed-
From: Lad Prabhakar
n preparation for adding support for the Renesas RZ/V2H(P) SoC, this patch
introduces a mechanism to pass SoC-specific information via OF data in the
DSI driver. This enables the driver to adapt dynamically to various
SoC-specific requirements without hardcoding configurations
From: Lad Prabhakar
In preparation for adding support for the Renesas RZ/V2H(P) SoC, make the
"rst" reset control optional in the MIPI DSI driver. The RZ/V2H(P) SoC
does not provide this reset line, and attempting to acquire it using the
mandatory API causes probe failure.
Switching to devm_rese
From: Lad Prabhakar
Introduce the `RZ_MIPI_DSI_FEATURE_16BPP` flag in `rzg2l_mipi_dsi_hw_info`
to indicate support for 16BPP pixel formats. The RZ/V2H(P) SoC supports
16BPP, whereas this feature is missing on the RZ/G2L SoC.
Update the `mipi_dsi_host_attach()` function to check this flag before
From: Lad Prabhakar
Introduce `dphy_conf_clks` and `dphy_mode_clk_check` callbacks in
`rzg2l_mipi_dsi_hw_info` to configure the VCLK and validate
supported display modes.
On the RZ/V2H(P) SoC, the DSI PLL dividers need to be as accurate as
possible. To ensure compatibility with both RZ/G2L and R
From: Lad Prabhakar
Pass the HSFREQ in milli-Hz to the `dphy_init()` callback to improve
precision, especially for the RZ/V2H(P) SoC, where PLL dividers require
high accuracy.
These changes prepare the driver for upcoming RZ/V2H(P) SoC support.
Co-developed-by: Fabrizio Castro
Signed-off-by: F
From: Lad Prabhakar
Hi All,
This patch series prepares the MIPI DSI driver to support the Renesas
RZ/V2H(P) SoC. These patches were originally part of series [0], but I have
split them into two parts to make them easier to review and merge.
v6->v7:
- Rebased the changes on drm-misc/next
- Dropp
From: Lad Prabhakar
Update the RZ/G2L MIPI DSI driver to calculate HSFREQ using the actual
VCLK rate instead of the mode clock. The relationship between HSCLK and
VCLK is:
vclk * bpp <= hsclk * 8 * lanes
Retrieve the VCLK rate using `clk_get_rate(dsi->vclk)`, ensuring that
HSFREQ accurately
From: Lad Prabhakar
Introduce the `dphy_late_init` callback in `rzg2l_mipi_dsi_hw_info` to
allow additional D-PHY register configurations after enabling data and
clock lanes. This is required for the RZ/V2H(P) SoC but not for the
RZ/G2L SoC.
Modify `rzg2l_mipi_dsi_startup()` to invoke `dphy_late
From: Lad Prabhakar
The VCLK range for Renesas RZ/G2L SoC is 5.803 MHz to 148.5 MHz. Add a
minimum clock check in the mode_valid callback to ensure that the clock
value does not fall below the valid range.
Co-developed-by: Fabrizio Castro
Signed-off-by: Fabrizio Castro
Signed-off-by: Lad Prabh
HMM device memory is allocated at the top of
iomem_resource, when iomem_resource is larger than
GPU device's dma mask, after devm_memremap_pages,
max_pfn will also be update and exceed device's
dma mask, when there are multiple card on system
need to be init, ttm_device_init would be called
with us
Commit 38559da6afb2 ("rust: module: introduce `authors` key") introduced
a new `authors` key to support multiple module authors, while keeping
the old `author` key for backward compatibility.
Now that all in-tree modules have migrated to `authors`, remove:
1. The deprecated `author` key support fr
Hi Diederik, sorry for late response
> Interesting that it also happened with drm=y.
I actually checked now and i don't have the issue with drm=y, sorry for
misinforming you all, hopefully no one's time was wasted.
> As you're more knowledgeable then I am with this, maybe look through
> https:/
Hi,
On Wed, May 28, 2025 at 6:21 AM Michael Walle wrote:
>
> The bridge has three bootstrap pins which are sampled to determine the
> frequency of the external reference clock. The driver will also
> (over)write that setting. But it seems this is racy after the bridge is
> enabled. It was observe
Hi,
On Mon, Jun 2, 2025 at 4:05 AM Jayesh Choudhary wrote:
>
> Hello Geert, Krzysztof,
>
> (continuing discussion from both patches on this thread...)
>
> On 30/05/25 13:25, Geert Uytterhoeven wrote:
> > Hi Jayesh,
> >
> > CC devicetree
> >
> > On Fri, 30 May 2025 at 04:54, Jayesh Choudhary wrot
- Ursprüngliche Mail -
> Von: "Guenter Roeck"
>>> I am trying to boot from "pnor". It looks like the partition data (from
>>> devicetree)
>>> is now ignored. mtdblock6 used to be the second flash.
>>>
>>> Guenter
>>
>> Is this with CONFIG_MTD_PARTITIONED_MASTER?
>>
>
> Yes
>
>> I think
Commit 1017560164b6 ("drm/meson: use unsigned long long / Hz for
frequency types") attempts to resolve video playback using 59.94Hz.
using YUV420 by changing the clock calculation to use
Hz instead of kHz (thus yielding more precision).
The basic calculation itself is correct, however the compari
its/Markus-Elfring/drm-amd-display-Fix-exception-handling-in-dm_validate_stream_and_context/20250609-151039
base: next-20250606
patch link:
https://lore.kernel.org/r/da489521-7786-4716-8fb8-d79b3c08d93c%40web.de
patch subject: [PATCH v2] drm/amd/display: Fix exception h
On Mon, Jun 09, 2025 at 11:24:35AM -0700, Rob Clark wrote:
> To better match add_gpu_components().
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_drv.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
Reviewed-by: Dmitry Baryshkov
--
With best wishes
Dmitry
On Mon, Jun 09, 2025 at 11:24:36AM -0700, Rob Clark wrote:
> We are going to want to re-use this before the component is bound, when
> we don't yet have the device pointer (but we do have the of node).
>
> v2: use %pOF
>
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/adreno_devic
On Mon, Jun 09, 2025 at 11:24:37AM -0700, Rob Clark wrote:
> If we have a newer dtb than kernel, we could end up in a situation where
> the GPU device is present in the dtb, but not in the drivers device
> table. We don't want this to prevent the display from probing. So
> check that we recognize
On Mon, Jun 09, 2025 at 10:56:09PM +0800, Yongbang Shi wrote:
>
> > On Fri, May 30, 2025 at 05:54:27PM +0800, Yongbang Shi wrote:
> > > From: Baihan Li
> > >
> > > DP Link training successful at 8.1Gbps with some monitors' max link rate
> > > are 2.7Gbps. So change the default 8.1Gbps link rate
We are going to want to re-use this before the component is bound, when
we don't yet have the device pointer (but we do have the of node).
v2: use %pOF
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff
If we have a newer dtb than kernel, we could end up in a situation where
the GPU device is present in the dtb, but not in the drivers device
table. We don't want this to prevent the display from probing. So
check that we recognize the GPU before adding the GPU component.
v2: use %pOF
Signed-off
To better match add_gpu_components().
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 710046906229..87ee9839ca4a 100644
--- a/drivers/gpu/drm/msm
Detect earlier if the GPU is supported, and skip binding the GPU
sub-component if not. This way the rest of the driver can still
probe and get working display if the only thing unsupported is
the GPU.
v2: use %pOF [Dmitry]
Rob Clark (3):
drm/msm: Rename add_components_mdp()
drm/msm/adreno: P
Hi,
Should I go ahead make the diagram more detailed or just add the links
in 'Slides and articles' & 'Conference talks' to the existing
diagram?
Best regards,
On Wed, Jun 4, 2025 at 10:37 AM Simona Vetter wrote:
>
> On Mon, Jun 02, 2025 at 08:28:30AM +0700, Bagas Sanjaya wrote:
> > On Sun, Ju
On Wed, 2025-06-04 at 12:12 +0300, Jani Nikula wrote:
> On Thu, 29 May 2025, Jeff Layton wrote:
> > Add a new "ref_tracker" directory in debugfs. Each individual refcount
> > tracker can register files under there to display info about
> > currently-held references.
> >
> > Reviewed-by: Andrew Lu
On 09/06/2025 20:04, Rob Clark wrote:
If we have a newer dtb than kernel, we could end up in a situation where
the GPU device is present in the dtb, but not in the drivers device
table. We don't want this to prevent the display from probing. So
check that we recognize the GPU before adding the
On 09.06.2025 19:39, Miguel Ojeda wrote:
> On Mon, Jun 9, 2025 at 2:22 PM Guilherme Giacomo Simoes
> wrote:
>>
>> Now that all in-tree modules have migrated to `authors`, remove:
>
> Nit: I would have said "most modules", since we have new/remaining
> ones (no need for a new version for this).
>
On Mon, Jun 9, 2025 at 2:22 PM Guilherme Giacomo Simoes
wrote:
>
> Now that all in-tree modules have migrated to `authors`, remove:
Nit: I would have said "most modules", since we have new/remaining
ones (no need for a new version for this).
I think this patch is OK -- we could wait to do this m
On 07/06/2025 00:10, Martin Blumenstingl wrote:
meson_vclk_vic_supported_freq() has a debug print which includes the
pixel freq. However, within the whole function the pixel freq is
irrelevant, other than checking the end of the params array. Switch to
printing the vclk_freq which is being compar
On 06/06/2025 22:37, Martin Blumenstingl wrote:
The "phy" and "vclk" frequency labels were swapped, making it more
difficult to debug driver errors. Swap the label order to make them
match with the actual frequencies printed to correct this.
Fixes: e5fab2ec9ca4 ("drm/meson: vclk: add support for
On 22/05/2025 21:03, Dmitry Baryshkov wrote:
From: Dmitry Baryshkov
Continue migration to the MDSS-revision based checks and replace
DPU_MDP_AUDIO_SELECT feature bit with the core_major_ver == 4 ||
core_major_ver == 5 check.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Dmitry Baryshkov
---
On Mon, Jun 09, 2025 at 10:47:50PM +0800, Yongbang Shi wrote:
>
> > On Fri, May 30, 2025 at 05:54:24PM +0800, Yongbang Shi wrote:
> > > From: Baihan Li
> > >
> > > The debouncing when HPD pulled out still remains sometimes, 200ms still
> > > can
> > > not ensure helper_detect() is correct. So a
On Mon, May 12, 2025 at 04:06:45PM +0100, Matthew Auld wrote:
> Goal here is cut over to gpusvm and remove xe_hmm, relying instead on
> common code. The core facilities we need are get_pages(), unmap_pages()
> and free_pages() for a given useptr range, plus a vm level notifier
> lock, which is now
To better match add_gpu_components().
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_drv.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 710046906229..87ee9839ca4a 100644
--- a/drivers/gpu/drm/msm
Detect earlier if the GPU is supported, and skip binding the GPU
sub-component if not. This way the rest of the driver can still
probe and get working display if the only thing unsupported is
the GPU.
Rob Clark (3):
drm/msm: Rename add_components_mdp()
drm/msm/adreno: Pass device_node to find
We are going to want to re-use this before the component is bound, when
we don't yet have the device pointer (but we do have the of node).
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/driver
If we have a newer dtb than kernel, we could end up in a situation where
the GPU device is present in the dtb, but not in the drivers device
table. We don't want this to prevent the display from probing. So
check that we recognize the GPU before adding the GPU component.
Signed-off-by: Rob Clark
On Mon, May 12, 2025 at 04:06:44PM +0100, Matthew Auld wrote:
> This will simplify compiling out the bits that depend on DRM_GPUSVM in a
> later patch. Without this we end up littering the code with ifdef
> checks, plus it becomes hard to be sure that something won't blow at
> runtime due to someth
On Sun, Jun 08, 2025 at 04:28:16PM +0200, Marek Vasut wrote:
> Document the 7" Raspberry Pi 720x1280 DSI panel based on ili9881.
>
> Signed-off-by: Marek Vasut
Acked-by: Conor Dooley
signature.asc
Description: PGP signature
Instead of having ggtt->size point to the end of ggtt, have ggtt->size
be the actual size of the GGTT, and introduce ggtt->start to point to
the beginning of GGTT.
This will allow a massive cleanup of GGTT in case of SRIOV-VF.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/xe/tests/xe_guc
From: Tomasz Lis
Due to resource reprovisioning, sometimes a need arises to move
a living address space to a new area, preserving all the nodes
and holes stored within.
It is possible to do that by removing all nodes to a temporary list,
reiniting the drm_mm instance and re-adding everything whi
The previous code was using a complicated system with 2 balloons to
set GGTT size and adjust GGTT offset. While it works, it's overly
complicated.
A better approach is to set the offset and size when initialising GGTT,
this removes the need for adding balloons. The resize function only
needs to re
On Mon, Jun 09, 2025 at 08:21:19PM +0800, Yongxing Mou wrote:
> Add support for Multi-stream transport for MSM chipsets that allow
> a single instance of DP controller to send multiple streams.
>
> This series has been validated on sa8775p ride platform using multiple
> MST dongles and also daisy
Hi,
On Mon, Jun 9, 2025 at 6:02 AM Jerome Brunet wrote:
>
> On Tue 25 Feb 2025 at 08:04, Doug Anderson wrote:
>
> > Hi,
> >
> > On Tue, Feb 18, 2025 at 11:30 AM Jerome Brunet wrote:
> >>
> >> The auxiliary device creation of this driver is simple enough to
> >> use the available auxiliary devic
On Mon, Jun 09, 2025 at 08:21:45PM +0800, Yongxing Mou wrote:
> From: Abhinav Kumar
>
> For MST cases, EDID is handled through AUX sideband messaging.
> Skip the EDID read during hotplug handle for MST cases.
Why? It makes sense to read it during the HPD processing, ping HDMI
codec, update CEC i
On Mon, Jun 09, 2025 at 08:21:47PM +0800, Yongxing Mou wrote:
> From: Abhinav Kumar
>
> Add a new file dp_mst_drm to manage the DP MST bridge operations
> similar to the dp_drm file which manages the SST bridge operations.
> Each MST encoder creates one bridge and each bridge is bound to its
> ow
On 6/9/25 08:16, Usyskin, Alexander wrote:
Subject: Re: [PATCH v6 01/11] mtd: core: always create master device
On 6/9/25 05:23, Usyskin, Alexander wrote:
Subject: Re: [PATCH v6 01/11] mtd: core: always create master device
Several of my qemu boot tests fail to boot from mtd devices with thi
On Mon, Jun 09, 2025 at 08:21:48PM +0800, Yongxing Mou wrote:
> From: Abhinav Kumar
>
> Add connector abstraction for the DP MST. Each MST encoder
> is connected through a DRM bridge to a MST connector and each
> MST connector has a DP panel abstraction attached to it.
>
> Signed-off-by: Abhinav
On Fri, Jun 6, 2025 at 7:03 AM Maxime Ripard wrote:
> On Wed, Jun 04, 2025 at 10:45:11PM -0500, Anusha Srivatsa wrote:
> > Put the panel reference back when driver is no
> > longer using it.
> >
> > Signed-off-by: Anusha Srivatsa
> > ---
> > drivers/gpu/drm/bridge/samsung-dsim.c | 1 +
> > 1 fi
On Mon, Jun 09, 2025 at 08:21:48PM +0800, Yongxing Mou wrote:
> From: Abhinav Kumar
>
> Add connector abstraction for the DP MST. Each MST encoder
> is connected through a DRM bridge to a MST connector and each
> MST connector has a DP panel abstraction attached to it.
>
> Signed-off-by: Abhinav
On Fri, May 30, 2025 at 05:54:27PM +0800, Yongbang Shi wrote:
From: Baihan Li
DP Link training successful at 8.1Gbps with some monitors' max link rate
are 2.7Gbps. So change the default 8.1Gbps link rate to the rate that reads
from devices' capabilities.
I've hard time understanding this me
> Subject: Re: [PATCH v6 01/11] mtd: core: always create master device
>
> On 6/9/25 05:23, Usyskin, Alexander wrote:
> >> Subject: Re: [PATCH v6 01/11] mtd: core: always create master device
> >>
> >>
> >> Several of my qemu boot tests fail to boot from mtd devices with this
> >> patch
>
From: Abhinav Kumar
dp_display_enable() currently re-trains the link if needed
and then enables the pixel clock, programs the controller to
start sending the pixel stream. Splite these two parts into
prepare/enable APIs, to support MST bridges_enable inserte
the MST payloads funcs between enable
On Mon, Jun 09, 2025 at 08:21:49PM +0800, Yongxing Mou wrote:
> From: Abhinav Kumar
>
> Add HPD callback for the MST module which shall be invoked from the
> dp_display's HPD handler to perform MST specific operations in case
> of HPD. In MST case, route the HPD messages to MST module.
>
> Signe
On Sat, 07 Jun 2025 19:44:58 +0530, Akhil P Oommen wrote:
> Add support for X1-45 GPU found in X1P41200 chipset (8 cpu core
> version). X1-45 is a smaller version of X1-85 with lower core count and
> smaller memories. From UMD perspective, this is similar to "FD735"
> present in Mesa.
>
> Tested
On Fri, May 30, 2025 at 05:54:28PM +0800, Yongbang Shi wrote:
From: Baihan Li
If DP is connected, add mode check and BW check in mode_valid_ctx() to
ensure DP's cfg is usable.
Fixes: f9698f802e50 ("drm/hisilicon/hibmc: Restructuring the header dp_reg.h")
Signed-off-by: Baihan Li
---
driv
On Mon, Jun 09, 2025 at 08:21:50PM +0800, Yongxing Mou wrote:
> Introduce APIs to update the MST state change to MST framework when
> device is plugged/unplugged.
>
> Signed-off-by: Yongxing Mou
> Signed-off-by: Abhinav Kumar
Hmm, who is the author of the patch?
> ---
> drivers/gpu/drm/msm/dp
On 09/06/2025 17:50, Yongbang Shi wrote:
On Fri, May 30, 2025 at 05:54:25PM +0800, Yongbang Shi wrote:
From: Baihan Li
The local variable of irq name is passed to devm_request_threaded_irq(),
which will make request_irq failed. Using the global irq name instead
of it to fix.
This doesn't ex
From: Abhinav Kumar
Add support to program the MST enabled bit in the mainlink
control when a mst session is active and disabled.
Signed-off-by: Abhinav Kumar
Signed-off-by: Yongxing Mou
---
drivers/gpu/drm/msm/dp/dp_catalog.c | 17 +
drivers/gpu/drm/msm/dp/dp_catalog.h | 1 +
From: Abhinav Kumar
QCS8300 support 4 streams MST and SA8775P support 2 x 2 MST. Add
support for other 3 pixels register block, and introduced
msm_dp_read_pn/msm_dp_write_pn to minimize repetitive code. All PCLK
share the same register definitions with different base addresses.
Signed-off-by: Ab
From: Abhinav Kumar
Currently the dp_display bridge helpers, in particular the
dp_display_enable()/dp_display_disable() use the cached panel.
To be able to re-use these helpers for MST use-case abstract the
helpers to use the panel which is passed in to them.
Signed-off-by: Abhinav Kumar
Signed
On Fri, May 30, 2025 at 05:54:25PM +0800, Yongbang Shi wrote:
From: Baihan Li
The local variable of irq name is passed to devm_request_threaded_irq(),
which will make request_irq failed. Using the global irq name instead
of it to fix.
This doesn't explain, why does it fail and which IRQ nam
On Mon, Jun 09, 2025 at 08:21:51PM +0800, Yongxing Mou wrote:
> From: Abhinav Kumar
>
> Hook up the mst framework APIs with atomic_commit_setup() and
> atomic_commit_tail() APIs to handle non-blocking commits.
Were non-blocking commits not supported before this patch?
>
> Signed-off-by: Abhina
On 09/06/2025 17:47, Yongbang Shi wrote:
On Fri, May 30, 2025 at 05:54:24PM +0800, Yongbang Shi wrote:
From: Baihan Li
The debouncing when HPD pulled out still remains sometimes, 200ms
still can
not ensure helper_detect() is correct. So add a flag to hold the sink
status, and changed detec
On Fri, May 30, 2025 at 05:54:24PM +0800, Yongbang Shi wrote:
From: Baihan Li
The debouncing when HPD pulled out still remains sometimes, 200ms still can
not ensure helper_detect() is correct. So add a flag to hold the sink
status, and changed detect_ctx() functions by using flag to check st
On Mon, Jun 09, 2025 at 08:21:57PM +0800, Yongxing Mou wrote:
> This change enables support for Multi-Stream Transport (MST), allowing
> each controller to handle up to two DisplayPort streams. As all
> necessary code for MST support was already implemented in the previous
> series of patches.
>
>
On Mon, Jun 09, 2025 at 08:21:56PM +0800, Yongxing Mou wrote:
> From: Abhinav Kumar
>
> Interface type of MST interfaces is currently INTF_NONE.
> Fix this to INTF_DP.
>
> Signed-off-by: Abhinav Kumar
> Signed-off-by: Yongxing Mou
> ---
> drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_4_sa8775p.
On Fri, May 30, 2025 at 05:54:23PM +0800, Yongbang Shi wrote:
From: Baihan Li
Currently the driver missed to clean the i2c adapter when vdac init failed.
It may cause resource leak.
Fixes: 94ee73ee3020 ("drm/hisilicon/hibmc: add dp hw moduel in hibmc driver")
No, the tag is incorrect. Offe
On Mon, Jun 09, 2025 at 08:21:54PM +0800, Yongxing Mou wrote:
> From: Abhinav Kumar
>
> Use msm_dp_get_mst_intf_id() to get the intf id for the DP MST
> controller as the intf_id is unique for each MST stream of each
> DP controller.
>
> Signed-off-by: Abhinav Kumar
> Signed-off-by: Yongxing Mo
I'm moving all my kernel work over to using my kernel.org email address.
Update .mailmap and MAINTAINER entries still using hdego...@redhat.com.
Signed-off-by: Hans de Goede
---
.mailmap| 1 +
MAINTAINERS | 72 ++---
2 files changed, 37 insert
Hi All,
I'm moving all my kernel work over to using my kernel.org email address.
The single patch in this series updates .mailmap and all MAINTAINERS
entries still using hdego...@redhat.com.
Since most of my work is pdx86 related I believe it would be best for Ilpo
to merge this through the pdx8
Pushed to drm-misc-fixes
On 6/9/25 06:35, Alex Deucher wrote:
On Wed, Jun 4, 2025 at 8:12 PM Lizhi Hou wrote:
On 6/4/25 07:51, Alex Deucher wrote:
On Wed, Jun 4, 2025 at 10:42 AM Lizhi Hou wrote:
The incorrect PSP firmware size is used for initializing. It may
cause error for newer version
On Mon, Jun 09, 2025 at 08:21:53PM +0800, Yongxing Mou wrote:
> From: Abhinav Kumar
>
> For each MST capable DP controller, initialize a dp_mst module to
> manage its DP MST operations. The DP MST module for each controller
> is the central entity to manage its topology related operations as
> we
On Mon, Jun 09, 2025 at 08:21:52PM +0800, Yongxing Mou wrote:
> From: Abhinav Kumar
>
> Initiliaze a DPMST encoder for each MST capable DP controller
> and the number of encoders it supports depends on the number
> of streams it supports.
>
> Signed-off-by: Abhinav Kumar
> Signed-off-by: Yongx
From: "Lin.Cao"
[ Upstream commit 471db2c2d4f80ee94225a1ef246e4f5011733e50 ]
When an entity from application B is killed, drm_sched_entity_kill()
removes all jobs belonging to that entity through
drm_sched_entity_kill_jobs_work(). If application A's job depends on a
scheduled fence from applicat
From: "Lin.Cao"
[ Upstream commit 471db2c2d4f80ee94225a1ef246e4f5011733e50 ]
When an entity from application B is killed, drm_sched_entity_kill()
removes all jobs belonging to that entity through
drm_sched_entity_kill_jobs_work(). If application A's job depends on a
scheduled fence from applicat
From: "Lin.Cao"
[ Upstream commit 471db2c2d4f80ee94225a1ef246e4f5011733e50 ]
When an entity from application B is killed, drm_sched_entity_kill()
removes all jobs belonging to that entity through
drm_sched_entity_kill_jobs_work(). If application A's job depends on a
scheduled fence from applicat
From: "Lin.Cao"
[ Upstream commit 471db2c2d4f80ee94225a1ef246e4f5011733e50 ]
When an entity from application B is killed, drm_sched_entity_kill()
removes all jobs belonging to that entity through
drm_sched_entity_kill_jobs_work(). If application A's job depends on a
scheduled fence from applicat
From: Abhinav Kumar
dp_display_prepare() only prepares the link in case its not
already ready before dp_display_enable(). Hence separate it into
its own API.
Signed-off-by: Abhinav Kumar
Signed-off-by: Yongxing Mou
---
drivers/gpu/drm/msm/dp/dp_display.c | 18 ++
drivers/gpu/d
From: Abhinav Kumar
Whenever virtual channel slot allocation changes, the DP
source must send the action control trigger sequence to notify
the sink about the same. This would be applicable during the
start and stop of the pixel stream. Add the infrastructure
to be able to send ACT packets for th
From: Abhinav Kumar
For MST cases, EDID is handled through AUX sideband messaging.
Skip the EDID read during hotplug handle for MST cases.
Signed-off-by: Abhinav Kumar
Signed-off-by: Yongxing Mou
---
drivers/gpu/drm/msm/dp/dp_display.c | 8 +---
1 file changed, 5 insertions(+), 3 deletion
From: Abhinav Kumar
Add a new file dp_mst_drm to manage the DP MST bridge operations
similar to the dp_drm file which manages the SST bridge operations.
Each MST encoder creates one bridge and each bridge is bound to its
own dp_panel abstraction to manage the operations of its pipeline.
Signed-o
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