and
couldn't think of a more appropriate generic name (the term "subsystem"
would probably be more accurate, but that's already used by cgroup
controllers).
Cc: Tejun Heo <t...@kernel.org>
Cc: cgro...@vger.kernel.org
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
inclu
(once I gather some more general feedback and move
out of the early RFC stage):
* Document this more fully in both the cgroups documentation and the
i915 kerneldoc.
* Write some i-g-t tests to exercise the ioctl and all the corner
cases.
Matt Roper (7):
cgroup: Allow drivers to s
On Fri, Jan 26, 2018 at 05:08:48PM +, Emil Velikov wrote:
> On 22 January 2018 at 15:44, Matt Roper <matthew.d.ro...@intel.com> wrote:
> > drm_set_cgrp_param is a simple tool to set DRM parameters associated with a
> > cgroup. It is intended to be called at system ini
On Sat, Jan 20, 2018 at 10:40:19AM +, Chris Wilson wrote:
> Quoting Chris Wilson (2018-01-20 09:36:10)
> > Quoting Matt Roper (2018-01-20 01:51:40)
> > > GPU contexts are usually created with "normal" priority as a starting
> > > point and
> > &
.
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
configure.ac | 1 +
tests/Makefile.am | 2 +-
tests/drm_set_cgrp_param/Makefile.am | 18 ++
tests/drm_set_cgrp_param/drm_set_cgrp_param.
Update i915_context_status to include priority.
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c
b/drivers/gpu/drm/i915/i915_debugfs.c
index cc659b
provide a helper
library for drivers that will take care of the details of storing per-cgroup
data structures in a hashtable and destroying those structures if/when the
cgroup itself is removed.
Cc: Tejun Heo <t...@kernel.org>
Cc: cgro...@vger.kernel.org
Signed-off-by: Matt Roper <mat
Drivers that handle processes on a per-cgroup basis need to be able to lookup
the cgroup that a process belongs to.
Cc: Tejun Heo <t...@kernel.org>
Cc: cgro...@vger.kernel.org
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
include/linux/cgroup.h | 5 -
k
Cc: Tejun Heo <t...@kernel.org>
Cc: cgro...@vger.kernel.org
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
include/drm/drm_file.h | 28
1 file changed, 28 insertions(+)
diff --git a/include/drm/drm_file.h b/include/drm/drm_file.h
index
Drivers may wish to access a cgroup's inode to perform permission checks on
driver-specific operations.
Cc: Tejun Heo <t...@kernel.org>
Cc: cgro...@vger.kernel.org
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
fs/kernfs/inode.c | 1 +
1 file changed, 1 insertion(+)
dif
supported by all DRM
drivers. We define parameter keys 0-0xFF as being driver-specific
parameters and reserve all higher keys for DRM core use.
Cc: Tejun Heo <t...@kernel.org>
Cc: cgro...@vger.kernel.org
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
drivers/gpu/
U priority for a group of
processes by setting a parameter on the cgroup that these processes belong to.
Cc: Tejun Heo <t...@kernel.org>
Cc: cgro...@vger.kernel.org
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/d
certainly relax that restriction if someone comes up with
a use case that needs this on the v1 hierarchies.
Cc: Tejun Heo <t...@kernel.org>
Cc: cgro...@vger.kernel.org
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
include/linux/cgroup.h | 3 +++
kernel/cgroup/c
ctory)
- Documentation: the new code here has a lot of kerneldoc embedded in
it, but none of that is actually integrated into the rst files in the
Documentation/gpu directory yet.
Matt Roper (9):
kernfs: Export kernfs_get_inode
cgroup: Add notifier call chain for cgroup
Drivers may wish to limit their own cgroup operations to cgroups in the
cgroup-v2 hierarchy. Let's make this helper function usable outside the cgroup
core code.
Cc: Tejun Heo <t...@kernel.org>
Cc: cgro...@vger.kernel.org
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
---
i
t;
> > Date: Sun Dec 3 11:01:47 2017 -0500
> >
> > Linux 4.15-rc2
> >
> > https://github.com/downor/linux_hyper_dmabuf.git hyper_dmabuf_integration_v3
> >
> > ___
> > dri-devel mailing
e CRTC on, but
also preserve the framebuffer and leave the planes on; that wound up
causing some kind of regression for vmwgfx, but I'm unclear on the
details there. I'd suggest getting an Ack from one of the vmware guys
to ensure that the less drastic change in behavior here won't cau
0e8fb7ba7ca5 ("drm/i915/skl: Flush the WM configuration")
> > Fixes: 8211bd5bdf5e ("drm/i915/skl: Program the DDB allocation")
> > Signed-off-by: Lyude
> > [omitting CC for stable, since this patch will need to be changed for
> >
On Wed, Aug 03, 2016 at 02:14:53PM -0700, Matt Roper wrote:
...
>
> I imagine we'll eventually probably want to create a new display vfunc
> to handle platform-specific pipe-level stuff that needs to happen under
> vblank evasion (like the scalers and linetime WM we have today) to kee
On Tue, Aug 02, 2016 at 02:20:33PM -0700, Matt Roper wrote:
> On Tue, Aug 02, 2016 at 02:52:51PM -0400, Lyude wrote:
> > Thanks to Ville for suggesting this as a potential solution to pipe
> > underruns on Skylake.
> >
> > On Skylake all of the registers for co
se needs braces, you need to put them on both branches).
> + if (result == 1)
As I mentioned before, the 1=off looks confusing if someone isn't
looking at the bspec carefully. Using a #define for the various 0x1's
in this patch might help clarify the code slightly.
With
8211bd5bdf5e ("drm/i915/skl: Program the DDB allocation")
> Signed-off-by: Lyude
> [omitting CC for stable, since this patch will need to be changed for
> such backports first]
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Cc: Radhakrishna Sripada
> Cc: Hans de Goede
his patch will need to be changed for
> such backports first]
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Cc: Radhakrishna Sripada
> Cc: Hans de Goede
> Cc: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 +
> drivers/gpu/drm/i915/intel_display.c | 74
&
ate if we have a change in
active pipes. I think what you meant to write was "...we'll need to
modify the watermarks on all active *planes*. Since those *planes*
won't..."
Aside from the commit message, I believe the logic is correct, so you
can consider this
Reviewed-by: M
vblank evasion
>
> Changes since v3:
> - Rebase against new SAGV patch changes
>
> Changes since v4:
> - Add a parameter to choose what skl_wm_values struct to use when
>writing new plane watermarks
>
> Fixes: 2d41c0b59afc ("drm/i915/skl: SKL Watermark C
te(): (temp & 0x1) indicates disabled, 0x0
>enabled
> - Call skl_sagv_enable/disable() from pre/post-plane updates
> Changes since v3:
> - Use time_before() to compare timeout to jiffies
> Changes since v2:
> - Really apply minor style nitpicks to patch this time
>
> we've got enough workarounds to make this tolerable. I've shown this to
> > matt roper, but I should probably post what I've been trying to do for
> > you as well.
> >
> > So the approach I came up with is here
> >
> > https://github.com/lyude/linux/tree/wip/s
On Fri, Jul 29, 2016 at 12:39:05PM +0300, Ville Syrjälä wrote:
> On Thu, Jul 28, 2016 at 05:03:52PM -0700, Matt Roper wrote:
> > This is completely untested (and probably horribly broken/buggy), but
> > here's a quick mockup of the general approach I was thinking for
> > en
mically during plane updates
> drm/i915/skl: Always wait for pipes to update after a flush
>
> Matt Roper (1):
> drm/i915/gen9: Only copy WM results for changed pipes to skl_hw
>
> drivers/gpu/drm/i915/i915_drv.h | 3 +
> drivers/gpu/drm/i915/i915_reg.h |
vblank evasion
>
> Changes since v3:
> - Rebase against new SAGV patch changes
>
> Fixes: 2d41c0b59afc ("drm/i915/skl: SKL Watermark Computation")
> Signed-off-by: Lyude
> Cc: stable at vger.kernel.org
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Cc: Ra
tate);
>
> - ret = skl_allocate_pipe_ddb(cstate, ddb);
> + ret = skl_allocate_pipe_ddb(cstate, new_ddb);
> if (ret)
> return ret;
> +
> + if (!intel_state->wm_results.ddb_changed &&
I think you c
minor style nitpicks to patch this time
> Changes since v1:
> - Added comments about this probably being one of the requirements to
>fixing Skylake's watermark issues
> - Minor style nitpicks from Matt Roper
> - Disable these functions on Broxton, since it doesn't have an SAGV
N9() instead of IS_SKYLAKE() since these fixes apply to more
>then just Skylake
> - Update description to make it clear this patch doesn't fix everything
> - Check if pipes were actually changed before writing watermarks
>
> Fixes: 2d41c0b59afc ("drm/i915/skl: SKL
skl_allocate_pipe_ddb(cstate, new_ddb);
> if (ret)
> return ret;
> +
> + if (!intel_state->wm_results.ddb_changed &&
> + skl_pipe_ddb_changed(old_ddb, new_ddb, intel_crtc->pipe))
> + intel_state->wm_results.ddb_changed = true;
> }
>
> return 0;
> --
> 2.7.4
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
pletely overlooking some stumbling block that makes it much
more complicated than I'm envisioning.
Matt
>
> Fixes: 0e8fb7ba7ca5 ("drm/i915/skl: Flush the WM configuration")
> Signed-off-by: Lyude
> Cc: stable at vger.kernel.org
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
not
worry about copying over the unchanged values.
Matt
>
> Fixes: 734fa01f3a17 ("drm/i915/gen9: Calculate watermarks during atomic
> 'check' (v2)")
> Cc: stable at vger.kernel.org
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Cc: Radhakrishna Sripada
> Cc: Han
On Wed, Jul 20, 2016 at 04:59:58PM -0400, Lyude wrote:
> From: Matt Roper
>
> When we write watermark values to the hardware, those values are stored
> in dev_priv->wm.skl_hw. However with recent watermark changes, the
> results structure we're copying from only contai
oop in skl_write_plane_wm (level < max_level
> should be level <= max_level)
> - Make diagram in commit more accurate to what's actually happening
> - Add Fixes:
>
> Fixes: 2d41c0b59afc ("drm/i915/skl: SKL Watermark Computation")
> Signed-off-by: Lyude
> Cc: stab
ude Paul
> Cc: stable at vger.kernel.org
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Cc: Radhakrishna Sripada
> Cc: Hans de Goede
> Cc: Matt Roper
> ---
> drivers/gpu/drm/i915/intel_pm.c | 16 +++-
> 1 file changed, 11 insertions(+), 5 deletions(-)
>
n to fixing all of the
> underrun issues we're currently seeing with skl
>
> Signed-off-by: Lyude Paul
> Cc: stable at vger.kernel.org
> Cc: Ville Syrjälä
> Cc: Daniel Vetter
> Cc: Radhakrishna Sripada
> Cc: Hans de Goede
> Cc: Matt Roper
> ---
>
On Wed, Jul 13, 2016 at 09:12:09PM +0300, Ville Syrjälä wrote:
> On Wed, Jul 13, 2016 at 11:08:46AM -0700, Matt Roper wrote:
> > On Tue, Jul 12, 2016 at 11:21:39AM -0700, Matt Roper wrote:
> > > On Tue, Jul 12, 2016 at 01:36:03PM -0400, Lyude wrote:
> > > > Si
On Tue, Jul 12, 2016 at 11:21:39AM -0700, Matt Roper wrote:
> On Tue, Jul 12, 2016 at 01:36:03PM -0400, Lyude wrote:
> > Since the watermark calculations for Skylake are still broken, we're apt
> > to hitting underruns very easily under multi-monitor configurations.
> > Whi
gt; - Added comments about this probably being one of the requirements to
>fixing Skylake's watermark issues
> - Minor style nitpicks from Matt Roper
> - Disable these functions on Broxton, since it doesn't have an SAGV
>
> Cc: Matt Roper
> Cc: Daniel Vetter
> Cc: Ville Syrj
.." which I believe indicates
that this isn't relevant to the Atom processors like Broxton. The SAGV
block time table also lists "SKL, EXCLUDE(BXT)."
This would also explain why I've been unable to reproduce your SKL
problems on my Broxton hardware.
Matt
> for_each_i
king
> provided to allow for dynamic removal of planes/encoders/crtcs.
>
> v2: Convert drm_crtc_index() and drm_encoder_index() as well.
> v3: Stop adjusting the indices upon removal; consider the list
> construct-only.
>
> Signed-off-by: Chris Wilson
> Cc: Daniel Vetter
> C
construction and then only walking the tail upon removal should
> be a major improvement for all.
>
> v2: Convert drm_crtc_index() and drm_encoder_index() as well.
>
> Signed-off-by: Chris Wilson
> Cc: Daniel Vetter
> Cc: Matt Roper
> Cc: Ville Syrjälä
Looks good to me.
On Thu, Mar 03, 2016 at 03:50:23PM +, Lionel Landwerlin wrote:
> Hi Matt,
>
> On 11/02/16 02:32, Matt Roper wrote:
> >Gen9 platforms allow CRTC's to be programmed with a background/canvas
> >color below the programmable planes. Let's expose this as a property to
> >
on't have a strong feeling either way, but we should
probably just make sure everyone is on the same page. If we decide as a
community that we *do* want the atomic requirement going forward, maybe
we can add a note about that to the kerneldoc or something so we
remember in the future.
Matt
--
Matt Ro
ashank Sharma
> Signed-off-by: Lionel Landwerlin
> Signed-off-by: Kumar, Kiran S
> Signed-off-by: Kausal Malladi
Reviewed-by: Matt Roper
> ---
> drivers/gpu/drm/i915/i915_drv.c| 3 +
> drivers/gpu/drm/i915/i915_reg.h| 31
s
of this patch. It's a pretty large/complicated patch overall, so there
may be things I missed, but I think it's in good enough shape to merge.
Acknowledged-by: Matt Roper
> ---
> Documentation/DocBook/gpu.tmpl | 6 +-
> drivers/gpu/drm/i915/i915_drv.c | 24 ++-
>
dex acbb1d9..19f8284 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9891,6 +9891,8 @@ static bool haswell_get_pipe_config(struct intel_crtc
> *crtc,
>
> intel_get_pipe_timings(crtc, pipe_config);
>
> + pi
On Tue, Feb 23, 2016 at 10:36:36AM +, Lionel Landwerlin wrote:
> On 23/02/16 00:38, Matt Roper wrote:
> >On Mon, Feb 22, 2016 at 02:18:08PM +, Lionel Landwerlin wrote:
> >>Implement Daniel Stone's recommendation to not read registers to infer
> >>the hardware's
* Only update color management when not doing
> + * a modeset as this will be done by
> + * crtc_enable already.
> + */
> + intel_color_set_csc(crtc);
> + intel_color_load_luts(crtc);
> + }
> +
> if (!modeset)
> intel_pre_plane_update(to_intel_crtc_state(crtc_state));
>
> @@ -13487,8 +13504,9 @@ out:
> #undef for_each_intel_crtc_masked
>
> static const struct drm_crtc_funcs intel_crtc_funcs = {
> - .gamma_set = intel_color_legacy_gamma_set,
> + .gamma_set = drm_atomic_helper_legacy_gamma_set,
> .set_config = drm_atomic_helper_set_config,
> + .set_property = drm_atomic_helper_crtc_set_property,
> .destroy = intel_crtc_destroy,
> .page_flip = intel_crtc_page_flip,
> .atomic_duplicate_state = intel_crtc_duplicate_state,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 9742d5b..3082dbe 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1624,9 +1624,8 @@ extern const struct drm_plane_helper_funcs
> intel_plane_helper_funcs;
>
> /* intel_color.c */
> void intel_color_init(struct drm_crtc *crtc);
> +int intel_color_check(struct drm_crtc *crtc, struct drm_crtc_state *state);
> void intel_color_set_csc(struct drm_crtc *crtc);
> void intel_color_load_luts(struct drm_crtc *crtc);
> -void intel_color_legacy_gamma_set(struct drm_crtc *crtc, u16 *red, u16
> *green,
> - u16 *blue, uint32_t start, uint32_t size);
>
> #endif /* __INTEL_DRV_H__ */
> diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
> b/drivers/gpu/drm/i915/intel_fbdev.c
> index 97a91e6..777f98c 100644
> --- a/drivers/gpu/drm/i915/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> @@ -379,6 +379,7 @@ retry:
> struct drm_connector *connector;
> struct drm_encoder *encoder;
> struct drm_fb_helper_crtc *new_crtc;
> + struct intel_crtc *intel_crtc;
>
> fb_conn = fb_helper->connector_info[i];
> connector = fb_conn->connector;
> @@ -420,6 +421,13 @@ retry:
>
> num_connectors_enabled++;
>
> + intel_crtc = to_intel_crtc(connector->state->crtc);
> + for (j = 0; j < 256; j++) {
> + intel_crtc->lut_r[j] = j;
> + intel_crtc->lut_g[j] = j;
> + intel_crtc->lut_b[j] = j;
> + }
> +
> new_crtc = intel_fb_helper_crtc(fb_helper,
> connector->state->crtc);
>
> /*
> --
> 2.7.0
>
> ___
> dri-devel mailing list
> dri-devel at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
517,6 +517,9 @@ struct intel_crtc_state {
> struct skl_pipe_wm skl;
> } optimal;
> } wm;
> +
> + /* Gamma mode programmed on the pipe */
> + uint32_t gamma_mode;
> };
>
> struct vlv_wm_state {
> --
> 2.7.0
>
> ___
iew which is recognized
> as a gen 8 but doesn't have the same enhanced color correction unit
> from Haswell on.
>
> v2: Fix access to GAMMA_MODE register on older generations than
> Haswell (from Matt Roper's comments)
>
> Signed-off-by: Lionel Landwerlin
Reviewe
intel_color_load_gamma_lut,
> + .load_lut = intel_color_legacy_load_lut,
> .atomic_begin = intel_begin_crtc_commit,
> .atomic_flush = intel_finish_crtc_commit,
> .atomic_check = intel_crtc_atomic_check,
> @@ -13428,6 +13428,17 @@ static int intel_atomic_commit(struct drm_device
> *dev,
> hw_check = true;
> }
>
> + if (!modeset &&
> + crtc->state->active &&
> + crtc->state->color_mgmt_changed) {
> + /* Only update color management when not doing
Minor nitpick; kernel coding style says the opening "/*" of multi-line
comments should be on a line by itself.
> + * a modeset as this will be done by
> + * crtc_enable already.
> + */
> + intel_color_set_csc(crtc);
> + intel_color_load_luts(crtc);
> + }
> +
> if (!modeset)
> intel_pre_plane_update(to_intel_crtc_state(crtc_state));
>
> @@ -13519,6 +13530,7 @@ out:
> static const struct drm_crtc_funcs intel_crtc_funcs = {
> .gamma_set = intel_color_legacy_gamma_set,
> .set_config = drm_atomic_helper_set_config,
> + .set_property = drm_atomic_helper_crtc_set_property,
> .destroy = intel_crtc_destroy,
> .page_flip = intel_crtc_page_flip,
> .atomic_duplicate_state = intel_crtc_duplicate_state,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 2b5d03a..c384c78 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -507,6 +507,8 @@ struct intel_crtc_state {
> /* IVB sprite scaling w/a (WaCxSRDisabledForSpriteScaling:ivb) */
> bool disable_lp_wm;
>
> + uint32_t gamma_mode;
> +
> struct {
> /*
>* optimal watermarks, programmed post-vblank when this state
> @@ -1620,9 +1622,11 @@ extern const struct drm_plane_helper_funcs
> intel_plane_helper_funcs;
>
> /* intel_color.c */
> void intel_color_init(struct drm_crtc *crtc);
> +void intel_color_update(struct drm_crtc *crtc);
> void intel_color_set_csc(struct drm_crtc *crtc);
> -void intel_color_load_gamma_lut(struct drm_crtc *crtc);
> +void intel_color_load_luts(struct drm_crtc *crtc);
> void intel_color_legacy_gamma_set(struct drm_crtc *crtc, u16 *red, u16
> *green,
> u16 *blue, uint32_t start, uint32_t size);
> +void intel_color_legacy_load_lut(struct drm_crtc *crtc);
intel_color_load_gamma_lut() was a rename from patch #1 of the series.
Maybe we should squash this name change back into that patch, even
though we only have a single LUT at that point? I guess it doesn't
really matter too much either way.
Matt
>
> #endif /* __INTEL_DRV_H__ */
> --
> 2.7.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
IPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME, _PIPE_C_CSC_POSTOFF_ME)
> +#define PIPE_CSC_POSTOFF_LO(pipe)_MMIO_PIPE3(pipe,
> _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO, _PIPE_C_CSC_POSTOFF_LO)
>
> /* MIPI DSI registers */
>
> --
> 2.7.0
>
> ___
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
the blob has an invalid size) so that it will
be more apparent why we failed when looking at kernel logs.
* Looks like one minor whitespace error, noted below.
* One minor helper note below.
Aside from those,
Reviewed-by: Matt Roper
Also, somewhere (probably as a followup patch to this
On Thu, Feb 11, 2016 at 12:00:50PM +0200, Ville Syrjälä wrote:
> On Wed, Feb 10, 2016 at 06:32:59PM -0800, Matt Roper wrote:
> > Gen9 platforms allow CRTC's to be programmed with a background/canvas
> > color below the programmable planes. Let's expose this as a property to
>
Paauwe
Cc: dri-devel at lists.freedesktop.org
Signed-off-by: Matt Roper
---
Documentation/DocBook/gpu.tmpl | 10 +++-
drivers/gpu/drm/i915/i915_debugfs.c | 8 +++
drivers/gpu/drm/i915/i915_reg.h | 9 +++
drivers/gpu/drm/i915/intel_display.c | 46
create the background
color property. (Bob)
- Add helper to build 64-bit RGBA internal value in appropriate format
(e.g., for the initial value when attaching a property). (Bob)
Cc: dri-devel at lists.freedesktop.org
Signed-off-by: Matt Roper
---
drivers/gpu/drm/drm_atomic.c | 4 ++
drivers/g
Vetter
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93313
Signed-off-by: Matt Roper
---
drivers/gpu/drm/drm_fb_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 69cbab5..1e103c4 100644
--- a/drive
e(struct drm_device *dev)
> {
> diff --git a/include/drm/drm_atomic_helper.h b/include/drm/drm_atomic_helper.h
> index 8cba54a2a0a0..8045cdea8cc9 100644
> --- a/include/drm/drm_atomic_helper.h
> +++ b/include/drm/drm_atomic_helper.h
> @@ -81,6 +81,12 @@ int drm_atomic_helper_set_config
in drm_for_each_connector
Cc: Daniel Vetter
Cc: Maarten Lankhorst
Signed-off-by: Matt Roper
---
drivers/gpu/drm/drm_atomic_helper.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic_helper.c
b/drivers/gpu/drm/drm_atomic_helper.c
index 3731a26..e5d0b21 100644
--- a/drivers/gpu/drm
On Wed, Nov 18, 2015 at 01:35:54PM -0800, Bob Paauwe wrote:
> On Thu, 22 Oct 2015 17:25:34 -0700
> Matt Roper wrote:
>
> > To support CRTC background color, we need a way of communicating RGB
> > color values to the DRM. However there is often a mismatch between ho
Now that we've added an RGBA property type to the kernel that handles
RGBA values with a specific bit layout, let's add a userspace helper to
allow userspace to easily build values in the proper format.
Cc: dri-devel at lists.freedesktop.org
Signed-off-by: Matt Roper
---
xf86drmMode.c | 36
patches were written
(pre-atomic) that the functionality had to be pretty much completely
rewritten for the new i915 atomic internals.
Cc: Chandra Konduru
Cc: dri-devel at lists.freedesktop.org
Signed-off-by: Matt Roper
---
Documentation/DocBook/gpu.tmpl | 10 -
drivers/gpu/drm/i915
e need are some helpers to build RGBA values
appropriately.
Cc: dri-devel at lists.freedesktop.org
Cc: Chandra Konduru
Signed-off-by: Matt Roper
---
drivers/gpu/drm/drm_atomic.c | 4
drivers/gpu/drm/drm_crtc.c | 33 +
include/drm/drm_crtc.h
support isn't there yet).
Cc: dri-devel at lists.freedesktop.org
Cc: Chandra Konduru
Matt Roper (2):
drm: Add infrastructure for CRTC background color property
drm/i915/skl: Add support for pipe background color
Documentation/DocBook/gpu.tmpl | 10 +++-
drivers/gpu/drm/drm_atomic.c
On Fri, Oct 16, 2015 at 11:27:10PM +0100, Emil Velikov wrote:
> On 16 October 2015 at 23:11, Matt Roper wrote:
> > Both drmGetDevice() and drmGetDevices() currently print a warning when
> > they encounter an unknown (non-PCI) subsystem type for a device node,
> > but they st
handling to bypass the rest of the processing for devices we
can't handle.
Cc: Emil Velikov
Signed-off-by: Matt Roper
---
xf86drm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/xf86drm.c b/xf86drm.c
index 951edbb..7e28b4f 100644
--- a/xf86drm.c
+++ b/xf86drm.c
@@ -3140,7
Some of the error conditions in drmGetDevice() can lead to us calling
closedir(NULL) or leaking memory. Fix these conditions the same way we
did for drmGetDevices() in commit:
commit 8c4a1cbd98bd8d185d489395f33302a17db643a9
Author: Matt Roper
Date: Wed Sep 30 09:30:51
On Fri, Oct 16, 2015 at 07:17:31PM +0200, Daniel Vetter wrote:
> On Fri, Oct 16, 2015 at 05:40:59PM +0100, Tvrtko Ursulin wrote:
> >
> > On 16/10/15 17:27, Matt Roper wrote:
> > >On Thu, Oct 15, 2015 at 08:40:02PM +0300, ville.syrjala at linux.intel.com
> > >
uring page flip.
>
> Cc: Matt Roper
> Cc: Tvrtko Ursulin
> Cc: Daniel Vetter
> Signed-off-by: Ville Syrjälä
For the series:
Reviewed-by: Matt Roper
I also confirmed that the i-g-t test I wrote here:
http://lists.freedesktop.org/archives/intel-gfx/2015-October/077394.html
now
On Fri, Oct 16, 2015 at 06:10:20PM +0300, Ville Syrjälä wrote:
> On Fri, Oct 16, 2015 at 04:35:02PM +0200, Daniel Vetter wrote:
> > On Fri, Oct 16, 2015 at 11:38:18AM +0300, Ville Syrjälä wrote:
> > > On Thu, Oct 15, 2015 at 05:32:12PM -0700, Matt Roper wrote:
> >
t by anyone except omapdrm, and it would be
> racy to set it the same way in the atomic helpers.
Can't we just remove the invert_dimensions field completely now? It's a
legacy-only field, but no legacy drivers actually set it, so it winds up
being completely unused.
Matt
>
> Cc: Matt
vrtko Ursulin
Cc: Tvrtko Ursulin
Cc: Ville Syrjälä
Signed-off-by: Matt Roper
---
drivers/gpu/drm/drm_crtc.c | 87 +-
1 file changed, 71 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
inde
On Thu, Oct 01, 2015 at 11:12:34AM +0100, Emil Velikov wrote:
> Hi Matt,
>
> On 30 September 2015 at 17:30, Matt Roper
> wrote:
> > If the opendir() call in drmGetDevices() returns failure, we jump to an
> > error label that calls closedir() and then returns. However t
the opendir() call.
Fix both of these issues by jumping to an earlier error label (to free
local_devices) and guarding the closedir() call with a NULL test.
Cc: Emil Velikov
Signed-off-by: Matt Roper
---
xf86drm.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/xf86drm.c
y're not allowed to do anything else
> like compute derived state, check constraints or put the state into the hw.
> That's for the atomic_check and atomic_commit callbacks. So for this patchset
> here you should move all the code in the atomic_get/set_property callbacks
> you add in i915
x140
> > > > [] process_one_work+0x1fd/0x670
> > > > [] ? process_one_work+0x16c/0x670
> > > > [] worker_thread+0x4e/0x450
> > > > [] ? process_one_work+0x670/0x670
> > > > [] kthread+0x101/0x120
> > > > [] ? kthread_create_on_node+0x250/0x250
> > > > [] ret_from_fork+0x3f/0x70
> > > > [] ? kthread_create_on_node+0x250/0x250
> > > > ---[ end trace 54cab2e0c772d5d9 ]---
> > > >
> > > >
> > > > 00:02.0 VGA compatible controller: Intel Corporation Xeon E3-1200 v3
> > > Processor Integrated Graphics Controller (rev 06)
> > >
> > > ___
> > > Intel-gfx mailing list
> > > Intel-gfx at lists.freedesktop.org
> > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
> > >
> >
> > ___
> > dri-devel mailing list
> > dri-devel at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
sktop.org
Signed-off-by: Matt Roper
---
I don't see any existing bugzilla's (or mailing list complaints) for this,
which surprises me a bit since it seems to be very easy to reproduce for me on
latest drm-intel-nightly running on IVB...boot the system, load X, kill X,
panic.
drivers/gpu/drm/drm_fb_help
_u32 num_samples_before_ctm;
> + /* This will be non-zero for pipe. May be zero for planes on some HW */
> + __u32 num_samples_after_ctm;
> +};
> +
> /* typedef area */
> #ifndef __KERNEL__
> typedef struct drm_clip_rect drm_clip_rect_t;
> --
> 1.9.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
drm_property *cm_crtc_palette_capabilities_property;
> + struct drm_property *cm_palette_before_ctm_property;
> + struct drm_property *cm_palette_after_ctm_property;
> + struct drm_property *cm_ctm_property;
> +
> /* dumb ioctl parameters */
> uint32_t preferred_depth, prefer_shadow;
>
> --
> 1.9.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
rst parameter rather than the DRM object pointer. We can
update handful of existing callsites to just pass obj->state for it.
Cc: dri-devel at lists.freedesktop.org
Signed-off-by: Matt Roper
---
drivers/gpu/drm/drm_atomic_helper.c | 12 ++--
drivers/gpu/drm/i915/intel_atomic.c
r.h
> @@ -35,6 +35,9 @@
> #define CHV_DEGAMMA_MAX_VALS 65
> #define CHV_10BIT_GAMMA_MAX_VALS 257
>
> +#define GEN9_PALETTE_STRUCT_VERSION 1
> +#define GEN9_SPLITGAMMA_MAX_VALS 512
> +
> /* Gamma correction */
> #define CHV_GAMMA_DATA_STRUCT_VERSION1
> #define CHV_10BIT_GAMMA_MAX_VALS 257
> --
> 1.9.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13641,6 +13641,8 @@ static void intel_begin_crtc_commit(struct drm_crtc
> *crtc,
>
> if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
> skl_detach_scalers(intel_crtc);
> +
> + intel_color_manager_crtc_commit(dev, crtc->state);
> }
>
> static void intel_finish_crtc_commit(struct drm_crtc *crtc,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 820ded7..de3e6e7 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1444,5 +1444,7 @@ void intel_attach_color_properties_to_crtc(struct
> drm_device *dev,
> int intel_color_manager_set_pipe_gamma(struct drm_device *dev,
> struct drm_crtc_state *crtc_state,
> struct drm_mode_object *obj, uint32_t blob_id);
> +void intel_color_manager_crtc_commit(struct drm_device *dev,
> + struct drm_crtc_state *crtc_state);
>
> #endif /* __INTEL_DRV_H__ */
> --
> 1.9.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
ne_helper_funcs;
> /* intel_color_manager.c */
> void intel_attach_color_properties_to_crtc(struct drm_device *dev,
> struct drm_mode_object *mode_obj);
> +int intel_color_manager_set_pipe_gamma(struct drm_device *dev,
> + struct drm_crtc_state *crtc_state,
> + struct drm_mode_object *obj, uint32_t blob_id);
>
> #endif /* __INTEL_DRV_H__ */
> --
> 1.9.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
perty_blob *ctm_blob;
> +
> struct drm_pending_vblank_event *event;
>
> struct drm_atomic_state *state;
> --
> 1.9.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = _crtc->base;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index b3dc138..dee5f91 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1438,4 +1438,8 @@ void intel_plane_destroy_state(struct drm_plane *plane,
> struct drm_plane_state *state);
> extern const struct drm_plane_helper_funcs intel_plane_helper_funcs;
>
> +/* intel_color_manager.c */
> +void intel_attach_color_properties_to_crtc(struct drm_device *dev,
> + struct drm_mode_object *mode_obj);
> +
> #endif /* __INTEL_DRV_H__ */
> --
> 1.9.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
tomic_get_property(struct drm_crtc *plane,
> +const struct drm_crtc_state *state,
> +struct drm_property *property,
> + uint64_t *val);
>
> /* intel_atomic_plane.c */
> struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
> --
> 1.9.1
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
On Tue, Jul 21, 2015 at 04:40:08PM +0530, Malladi, Kausal wrote:
> On Tuesday 21 July 2015 05:33 AM, Matt Roper wrote:
> >On Wed, Jul 15, 2015 at 06:39:35PM +0530, Kausal Malladi wrote:
...
> >>diff --git a/drivers/gpu/drm/i915/intel_display.c
> >>b/drivers/gpu/drm/i91
lay.c
> @@ -13773,6 +13773,9 @@ static void intel_begin_crtc_commit(struct drm_crtc
> *crtc)
>
> if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
> skl_detach_scalers(intel_crtc);
> +
> + if (!needs_modeset(crtc->state))
> +
> /* intel_color_manager.c */
> void intel_attach_color_properties_to_crtc(struct drm_device *dev,
> struct drm_mode_object *mode_obj);
> +int intel_color_manager_set_pipe_gamma(struct drm_device *dev,
> + struct drm_crtc_state *crtc_state,
> + struct drm_mode_object *obj, uint32_t blob_id);
>
> #endif /* __INTEL_DRV_H__ */
> --
> 2.4.5
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
uct drm_crtc_state *state,
> + struct drm_property *property,
> +uint64_t val);
>
> /* intel_atomic_plane.c */
> struct intel_plane_state *intel_create_plane_state(struct drm_plane *plane);
> --
> 2.4.5
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
_attach_property(mode_obj,
> config->prop_palette_before_ctm, 0);
> diff --git a/drivers/gpu/drm/i915/intel_color_manager.h
> b/drivers/gpu/drm/i915/intel_color_manager.h
> index 04c921d..51aeb91 100644
> --- a/drivers/gpu/drm/i915/intel_color_
ing) ||
> dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
> dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = _crtc->base;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index b9c01c5..05c809b 100644
+#define CHV_8BIT_GAMMA_SHIFT_RED_REG 16
> +#define CHV_8BIT_GAMMA_SHIFT_GREEN_REG 8
> +#define CHV_10BIT_GAMMA_MSB_SHIFT6
> +#define CHV_GAMMA_SHIFT_GREEN16
> +
> #define CHV_CSC_COEFF_MAX_PRECISION 12
> #define CHV_CSC_COEFF_MAX_INT7
> #define CHV_CSC_COEFF_MIN_INT-7
> +
> +/* CHV CGM Block */
> +/* Bit 2 to be enabled in CGM block for CHV */
> +#define CGM_GAMMA_EN 4
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 053ceb0..a7aaadf 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1453,5 +1453,7 @@ extern const struct drm_plane_helper_funcs
> intel_plane_helper_funcs;
> /* intel_color_manager.c */
> void intel_color_manager_attach(struct drm_device *dev,
> struct drm_mode_object *mode_obj);
> +int intel_color_manager_set_gamma(struct drm_device *dev,
> + struct drm_mode_object *obj, uint32_t blob_id);
>
> #endif /* __INTEL_DRV_H__ */
> --
> 2.4.5
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
>base.base);
> +
> BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
> dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
> dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = _crtc->base;
> diff --git a/drivers/gpu/drm/i91
t; + /* Color Management Properties */
> + struct drm_property *prop_color_capabilities;
> + struct drm_property *prop_palette_before_ctm;
> + struct drm_property *prop_palette_after_ctm;
> + struct drm_property *prop_ctm;
> +
> /* dumb ioctl parameters */
> uint32_t preferred_depth, prefer_shadow;
>
> --
> 2.4.5
>
--
Matt Roper
Graphics Software Engineer
IoTG Platform Enabling & Development
Intel Corporation
(916) 356-2795
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