On Wed, 18 May 2016, Mario Kleiner wrote:
> On 05/17/2016 08:51 AM, Daniel Vetter wrote:
>> On Thu, May 12, 2016 at 06:43:58PM +0200, Mario Kleiner wrote:
>>> This fixes a regression in output precision for DVI and VGA
>>> video sinks connected to Intel hw via active DisplayPort->DVI/VGA
>>>
On 05/17/2016 08:51 AM, Daniel Vetter wrote:
> On Thu, May 12, 2016 at 06:43:58PM +0200, Mario Kleiner wrote:
>> This fixes a regression in output precision for DVI and VGA
>> video sinks connected to Intel hw via active DisplayPort->DVI/VGA
>> converters.
>>
>> The regression was indirectly
On Thu, May 12, 2016 at 06:43:58PM +0200, Mario Kleiner wrote:
> This fixes a regression in output precision for DVI and VGA
> video sinks connected to Intel hw via active DisplayPort->DVI/VGA
> converters.
>
> The regression was indirectly introduced by commit 013dd9e03872
> ("drm/i915/dp: fall
This fixes a regression in output precision for DVI and VGA
video sinks connected to Intel hw via active DisplayPort->DVI/VGA
converters.
The regression was indirectly introduced by commit 013dd9e03872
("drm/i915/dp: fall back to 18 bpp when sink capability is unknown").
Our current drm edid 1.3