Hi Hans,
On Thu, Feb 28, 2019 at 05:54:21PM +0100, Hans de Goede wrote:
> Hi Heikki,
>
> On 28-02-19 15:47, Heikki Krogerus wrote:
> > Hi Hans,
> >
> > On Thu, Feb 28, 2019 at 12:24:25PM +0100, Hans de Goede wrote:
> > > Hi,
> > >
> > > On 28-02-19 10:15, Heikki Krogerus wrote:
>
>
>
> > >
Hi,
On 04-03-19 16:17, Heikki Krogerus wrote:
Hi Hans,
On Thu, Feb 28, 2019 at 05:54:21PM +0100, Hans de Goede wrote:
Hi Heikki,
On 28-02-19 15:47, Heikki Krogerus wrote:
Hi Hans,
On Thu, Feb 28, 2019 at 12:24:25PM +0100, Hans de Goede wrote:
Hi,
On 28-02-19 10:15, Heikki Krogerus wrote:
On Wed, Feb 27, 2019 at 04:45:32PM +0100, Hans de Goede wrote:
> Hi,
>
> On 27-02-19 12:16, Jani Nikula wrote:
> > On Wed, 27 Feb 2019, Heikki Krogerus
> > wrote:
> > > One thing that this series does not consider is the DP lane count
> > > problem. The GPU drivers (i915 in this case) does not
Hi Hans,
On Thu, Feb 28, 2019 at 12:24:25PM +0100, Hans de Goede wrote:
> Hi,
>
> On 28-02-19 10:15, Heikki Krogerus wrote:
> > On Wed, Feb 27, 2019 at 04:45:32PM +0100, Hans de Goede wrote:
> > > Hi,
> > >
> > > On 27-02-19 12:16, Jani Nikula wrote:
> > > > On Wed, 27 Feb 2019, Heikki Krogerus
Hi Heikki,
On 28-02-19 15:47, Heikki Krogerus wrote:
Hi Hans,
On Thu, Feb 28, 2019 at 12:24:25PM +0100, Hans de Goede wrote:
Hi,
On 28-02-19 10:15, Heikki Krogerus wrote:
I've been thinking about this... Do we actually need to link the
correct drm_connector to the Type-C connector?
Hi,
On 28-02-19 10:15, Heikki Krogerus wrote:
On Wed, Feb 27, 2019 at 04:45:32PM +0100, Hans de Goede wrote:
Hi,
On 27-02-19 12:16, Jani Nikula wrote:
On Wed, 27 Feb 2019, Heikki Krogerus wrote:
One thing that this series does not consider is the DP lane count
problem. The GPU drivers
Hi,
On 27-02-19 12:16, Jani Nikula wrote:
On Wed, 27 Feb 2019, Heikki Krogerus wrote:
One thing that this series does not consider is the DP lane count
problem. The GPU drivers (i915 in this case) does not know is four,
two or one DP lanes in use.
Also, orientation.
The orientation should
On Wed, Feb 27, 2019 at 01:16:27PM +0200, Jani Nikula wrote:
> On Wed, 27 Feb 2019, Heikki Krogerus wrote:
> > One thing that this series does not consider is the DP lane count
> > problem. The GPU drivers (i915 in this case) does not know is four,
> > two or one DP lanes in use.
>
> Also,
Hi Hans,
On Mon, Feb 25, 2019 at 02:20:34PM +0100, Hans de Goede wrote:
> Hi All,
>
> On some Cherry Trail devices, DisplayPort over Type-C is supported through
> a USB-PD microcontroller (e.g. a fusb302) + a mux to switch the superspeed
> datalines between USB-3 and DP (e.g. a pi3usb30532). The
On Wed, 27 Feb 2019, Heikki Krogerus wrote:
> One thing that this series does not consider is the DP lane count
> problem. The GPU drivers (i915 in this case) does not know is four,
> two or one DP lanes in use.
Also, orientation.
> I guess that is not a critical issue since there is a
Hi All,
On some Cherry Trail devices, DisplayPort over Type-C is supported through
a USB-PD microcontroller (e.g. a fusb302) + a mux to switch the superspeed
datalines between USB-3 and DP (e.g. a pi3usb30532). The kernel in this
case does the PD/alt-mode negotiation itself, rather then
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