Add support for the JDI LT070ME05000 WUXGA DSI panel used in
Nexus 7 2013 devices.
Programming sequence for the panel is was originally found in the
android-msm-flo-3.4-lollipop-release branch from:
https://android.googlesource.com/kernel/msm.git
And video mode setting is from dsi-panel-jdi-d
Provide a small convenience wrapper that set/get the
display brightness value
Cc: John Stultz
Cc: Sumit Semwal
Cc: Archit Taneja
Cc: Rob Clark
Cc: Jani Nikula
Cc: Thierry Reding
Signed-off-by: Vinay Simha BN
---
v1:
*tested in nexus7 2nd gen.
v2:
* implemented jani review comments
-f
On Sat, Jun 18, 2016 at 05:24:30AM +0800, kernel test robot wrote:
> [1.338384] 00:05: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a
> 16550A
> [1.340531] toshiba: not a supported Toshiba laptop
> [1.341126] [drm] Initialized drm 1.1.0 20060810
> [1.342029] INFO: trying to
On 17 June 2016 at 08:33, Daniel Vetter wrote:
> Ever since
>
> commit 2e1868b560315a8b20d688e646c489a5ad93eeae
> Author: Eric Anholt
> Date: Wed Jun 16 09:25:21 2004 +
>
> DRI trunk-20040613 import
>
> the X server supports drm 1.1, and doesn't even call this ioctl any
> more. When rev
Hi Daniel,
On 17 June 2016 at 08:33, Daniel Vetter wrote:
> Lots of arm drivers get this wrong and for most arm boards this is the
> right thing actually. And anyway with most loaders you want to chase
> sysfs links anyway to figure out which dri device you want.
>
> This will fix dmesg noise for
On Sat, Jun 18, 2016 at 05:24:30AM +0800, kernel test robot wrote:
>
>
> FYI, we noticed the following commit:
>
> git://anongit.freedesktop.org/drm-intel topic/drm-misc
> commit e28cd4d0a223e1bcea616326e2281900e7e7e9a2 ("drm: Automatically
> register/unregister all connectors")
>
>
> on test
The callback function dma_buf_describe() returns an int not void so the
function pointer cast in dma_buf_show() is wrong. dma_buf_describe() can
also fail when acquiring the mutex gets interrupted so always returning
0 in dma_buf_show() is wrong, too.
Fix both issues by casting the function pointe
Yes, USB device can fixes the issue (only attaching a device has no
effect, attching and do data transferring can fix).
Huacai
On Fri, Jun 17, 2016 at 5:31 PM, Koenig, Christian
wrote:
> Hi Huacai,
>
> Adding our internal list on CC as well, maybe somebody else has an idea.
>
> I unfortunately d
From: Thierry Reding
Some backlight drivers ignore the power property and instead only use
the state property. Fixup the panel driver to set the state property in
addition to the power property.
Signed-off-by: Thierry Reding
---
Jingoo, Lee,
What's the correct way to do this? Should we update
to resolve conflicts against if needed?
Thierry
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s and you are onboard with the change.
Thierry
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ill be considered as
> I2C slaves.
>
> How are #address-cells and #size-cells handled in this case? I assume
> that they should live under the i2c-bus subnode, which should be called
> out.
Good catch. Yes, I think the i2c-bus subnode would be the right place
for #address-cells and #size-cells.
Thierry
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TEGRA210_CLK_DSIB>,
> + <&tegra_car TEGRA210_CLK_MIPI_CAL>,
Does this mean that all of these clocks will be running while the SOR
partition is enabled? Seems like a waste because we rarely need MIPI_CAL
and DSIA and DSIB are completely unused on boards that for example have
only an HDMI output.
I vaguely remember the power domain driver only making sure these are
enabled during the partition power transitions, so perhaps my concerns
aren't justified?
Thierry
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Did you mean to use the devm_ variant here? Because I don't see a
pinctrl_unregister() in tegra_dpaux_remove().
Thierry
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The IO pins of Tegra SoCs are grouped for common control of IO
interface like setting voltage signal levels and power state of
the interface. The group is generally referred as IO pads. The
power state and voltage control of IO pins can be done at IO pads
level.
Tegra generation SoC supports the p
The function tegra_pmc_readl() returns the u32 type data and hence
change the data type of variable where this data is stored to u32
type.
Signed-off-by: Laxman Dewangan
Reviewed-by: Jon Hunter
---
Changes from V1:
-This is new in series as per discussion on V1 series to use u32 for
tegra_pmc_r
one
Changes from V3:
- None
Changes from V4:
- Collected ack from Jon.
Changes from V5/V6:
- None
Changes from V7:
- Rebase on next-20160617
---
drivers/soc/tegra/pmc.c | 42 +-
1 file changed, 21 insertions(+), 21 deletions(-)
diff --git a/drivers/soc/t
se and refactor APIs to
convert io-pads to bit.
Changes from V7:
- Fix document format.
- Document public APIs.
- Fix the bit check.
- Add check of pad ID validatity.
Changes from V8:
- Fix comment style and typo.
- Rebase the series on 20160617
Laxman Dewangan (3):
soc/tegra: pmc: Use BIT mac
erties:
> +- groups: Must be "dpaux-io"
Above you say that we don't need to describe the pads, but then the
groups property does describe the pads. Why?
Thierry
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From: Wei Yongjun
In case of error, the function devm_clk_get() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().
Signed-off-by: Wei Yongjun
---
drivers/gpu/drm/hisilicon/kirin/kirin_drm_ade.c | 12 ++--
1 file changed,
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-456,6 +479,8 @@ static int tegra_dpaux_remove(struct platform_device
> *pdev)
> clk_disable_unprepare(dpaux->clk_parent);
> reset_control_assert(dpaux->rst);
> clk_disable_unprepare(dpaux->clk);
> + if (dpaux->clk_sor)
> + clk_disable_unprepare(dpaux->clk_sor);
Same here.
Thierry
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ual role of the clock, whereas sor-safe is the system name of the
clock.
Thierry
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ion)
Can function not be unsigned?
Thierry
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Forgot to mention, Ville: if you could get me an example of how to get
vlv into an infinite loop with these patches I'd appreciate that. I
haven't been able to reproduce this at all with the Valleyview machine
I've got here.
On Fri, 2016-06-17 at 17:58 -0400, Lyude wrote:
> These are a couple of p
Unfortunately, there's two situations where we lose hpd right now:
- Runtime suspend
- When we've shut off all of the power wells on Valleyview/Cherryview
While it would be nice if this didn't cause issues, this has the
ability to get us in some awkward states where a user won't be able to
get the
While VGA hotplugging worked(ish) before, it looks like that was mainly
because we'd unintentionally enable it in
valleyview_crt_detect_hotplug() when we did a force trigger. This
doesn't work reliably enough because whenever the display powerwell on
vlv gets disabled, the values set in VLV_ADPA ge
This lets call intel_crt_reset() in contexts where IRQs are disabled and
as such, can't hold the locks required to work with the connectors.
Cc: stable at vger.kernel.org
Cc: Ville Syrjälä
Cc: Daniel Vetter
Signed-off-by: Lyude
---
drivers/gpu/drm/i915/intel_crt.c | 10 +-
1 file cha
These are a couple of patches intended to fix one of the big problems we have
with a lot of chipsets on i915 right now: in the various forms of suspend we
use in the driver, many of them break HPD while active and can lead to some
seriously confusing situations where they can't get their monitors t
On Fri, Jun 17, 2016 at 01:03:41PM +0100, Jon Hunter wrote:
> The I2C driver core for boards using device-tree assumes any subnode of
> an I2C adapter in the device-tree blob as being a I2C slave device.
> Although this makes complete sense, some I2C adapters may have subnodes
> which are not I2C s
From: Ville Syrjälä
drm_plane_helper_check_update() needs to account for the plane rotation
for correct clipping/scaling calculations. Do so.
There was an earlier attempt [1] to add this into
intel_check_primary_plane() but I requested that it'd be put into the
helper instead. An updated patch
Hi, Christian
We found that if we use RS780 UVD decoding, hpet_readl() will need as
long as 1ms.
But, if attach a U-disk on south bridge (SB700) and read some data
from it, hpet_readl() has no problem.
Could you please give me some suggestions or fix it?
How to reproduce:
1, apply the patch on to
On Fri, Jun 17, 2016 at 05:13:10PM +0300, ville.syrjala at linux.intel.com
wrote:
> From: Ville Syrjälä
>
> drm_plane_helper_check_update() needs to account for the plane rotation
> for correct clipping/scaling calculations. Do so.
>
> There was an earlier attempt [1] to add this into
> intel
Hi,
On 17 June 2016 at 15:23, Daniel Vetter wrote:
> On Fri, Jun 17, 2016 at 10:09:50AM +0800, Xinliang Liu wrote:
>> Hi Daniel,
>>
>> I have tested your David's drm-next branch[1] which including this patch.
>> In most time it is ok. But when switching modes or disable/re-enable
>> mode, it will
On Fri, 17 Jun 2016, Daniel Vetter wrote:
> On Thu, Jun 16, 2016 at 03:42:12PM -0700, James Bottomley wrote:
>> On Thu, 2016-06-16 at 14:29 -0700, James Bottomley wrote:
>> > On Thu, 2016-06-16 at 23:24 +0200, Daniel Vetter wrote:
>> > > I guess we'll need the bisect on this one to make progress.
ed y
and did not think twice, if there even was a problem. I just have a
habit of asking "why". ;-)
After all, using GL with windows and FBOs and stuff you very often find
yourself upside down, and I suspect people have got the habit of just
flipping it if it does not look right the first time. See e.g. the
row-order of data going into glTexImage2D...
If the answer is "oops, well, dmabuf import is semantically y-flipping
when it should not, but we cannot fix it because that would break
everyone", I would be happy with that. I just want confirmation before
flipping the flip flag. :-)
Thanks,
pq
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On Thu, Jun 16, 2016 at 07:09:32PM +0900, Minchan Kim wrote:
> On Thu, Jun 16, 2016 at 05:42:11PM +0900, Sergey Senozhatsky wrote:
> > On (06/16/16 15:47), Minchan Kim wrote:
> > > > [..]
> > > > > > this is what I'm getting with the [zsmalloc: keep first object
> > > > > > offset in struct page]
On Fri, 2016-06-17 at 16:34 +0300, Jani Nikula wrote:
> On Fri, 17 Jun 2016, Daniel Vetter wrote:
> > On Thu, Jun 16, 2016 at 03:42:12PM -0700, James Bottomley wrote:
> > > On Thu, 2016-06-16 at 14:29 -0700, James Bottomley wrote:
> > > > On Thu, 2016-06-16 at 23:24 +0200, Daniel Vetter wrote:
> >
Quoting Maxime Ripard (2016-05-16 05:47:01)
> A fixed factor clock, if it needs to change its rate, by definition do not
> have any choice but to modify its parent rate.
Logically it makes sense to always propagate the rate-change request up
to the parent for a fixed-factor clock if we desire to c
On Fri, Jun 17, 2016 at 12:13:41PM +0200, Lucas Stach wrote:
> Drop the load/unload driver ops, as they are deprecated because of their
> inherent races, with devices being visible to userspace before they are
> fully initialized.
>
> Move this code into the driver bind/unbind routines bracketed b
On Fri, Jun 17, 2016 at 12:13:38PM +0200, Lucas Stach wrote:
> If there is no framebuffer mode that can be restored, all outputs should
> be disabled in order to avoid information leaks.
No, this was a short-term regression that's now fixed again. When a client
closes or calls rmfb, we make sure t
On 06/17/2016 01:55 PM, Chris Wilson wrote:
> Up to now, the recommendation was for drivers to call drm_dev_register()
> followed by drm_connector_register_all(). Now that
> drm_connector_register() is safe against multiple invocations, we can
> move drm_connector_register_all() to drm_dev_regist
On Fri, Jun 17, 2016 at 09:25:17AM +0100, Chris Wilson wrote:
> As the drm_connector is now safe for multiple calls to
> register/unregister, automatically perform a registration on all known
> connectors drm drv_register (and unregister from drm_drv_unregister).
> Drivers can still call drm_connec
On Fri, Jun 17, 2016 at 09:33:18AM +0100, Chris Wilson wrote:
> When trying to split up the initialisation phase and the registration
> phase, one immediate problem encountered is trying to use our own i2c
> devices before registration with userspace (to read EDID during device
> discovery). drm_dp
On Fri, Jun 17, 2016 at 12:04:16PM +0200, Benjamin Gaignard wrote:
> Acked-by: Benjamin Gaignard
Applied to drm-misc.
-Daniel
>
> 2016-06-02 0:07 GMT+02:00 Daniel Vetter :
> > Atomic drivers are supposed to do hw/sw state reset with the
> > drm_mode_config_reset() call right above it.
> >
> > C
On Fri, Jun 17, 2016 at 04:38:06PM +0800, Xinliang Liu wrote:
> Hi,
>
> On 17 June 2016 at 15:23, Daniel Vetter wrote:
> > On Fri, Jun 17, 2016 at 10:09:50AM +0800, Xinliang Liu wrote:
> >> Hi Daniel,
> >>
> >> I have tested your David's drm-next branch[1] which including this patch.
> >> In most
Hi Daniel,
Thank you for the patch.
On Friday 17 Jun 2016 09:33:28 Daniel Vetter wrote:
> Since
>
> commit e112e593b215c394c0303dbf0534db0928e87967
> Author: Nicolas Iooss
> Date: Fri Dec 11 11:20:28 2015 +0100
>
> drm: use dev_name as default unique name in drm_dev_alloc()
>
> we're us
in place first, and at least kick most of the popular apps to have
> >> their code ready, and wait a bit, and wait some more, before we can
> >> nuke the ioctl from the kernel for non-master. It'll probably take 5
> >> years if we're fast :( I do think that we should be ok with breaking
> >> the last few hold-outs, but we definitely need to have an alternate
> >> solution for EGL ready. Hence why I want to know whether there's
> >> anyone who's using this outside of EGL.
> >>
> >> Really this was just drive-by that I spotted while looking around at
> >> stuff for our other discussion around vblanks.
> >> -Daniel
> >> --
> >> Daniel Vetter
> >> Software Engineer, Intel Corporation
> >> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
> >
> >
>
>
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> +41 (0) 79 365 57 48 - http://blog.ffwll.ch
>
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Use drm_dev_alloc() and drm_dev_register() instead of .load()
Since debugfs root is created only when the device is registered
bind sub-components after this step.
Need to be reworked before upstream
Signed-off-by: Benjamin Gaignard
---
drivers/gpu/drm/sti/sti_drv.c | 146 ++
From: Bich Hemon
Compensate delay introduced by AWG IP during DE generation
Signed-off-by: Bich Hemon
Reviewed-by: Vincent ABRIOU
---
drivers/gpu/drm/sti/sti_awg_utils.c | 4 +++-
drivers/gpu/drm/sti/sti_vtg.c | 2 +-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/driver
On 17/06/16 13:03, Jon Hunter wrote:
> The DPAUX pins are shared with an internal I2C controller. To allow
> these pins to be muxed to the I2C controller, register a pinctrl device
> for the DPAUX device. Make Tegra DRM support dependent on PINCTRL to
> avoid any compilation issues.
I forgot to
Add description of ADV7533. Add the required and optional properties that
are specific to it.
Cc: devicetree at vger.kernel.org
Acked-by: Rob Herring
Signed-off-by: Archit Taneja
---
.../bindings/display/bridge/adi,adv7511.txt| 26 +-
1 file changed, 21 insertions(
Lower modes on ADV7533 require lower number of DSI lanes for correct
operation. If ADV7533 is being used with 4 DSI lanes, then switch the
lanes to 3 when the target mode's pixel clock is less than 80 Mhz.
Based on patch by Andy Green
Signed-off-by: Archit Taneja
---
drivers/gpu/drm/bridge/adv
ADV7533 provides an internal timing generator for certain modes that it
can't use the DSI clock directly.
We've observed that HDMI is more stable with the internal timing
generator, especially if there are instabilities in the DSI clock source.
The data spec also seems to recommend the usage of th
In order to pass DSI specific parameters to the DSI host, we need the
driver to create a mipi_dsi_device DSI device that attaches to the
host.
Use of_graph helpers to get the DSI host DT node. Create a MIPI DSI
device using this host. Finally, attach this device to the DSI host.
Populate DT param
ADV7533 is a DSI to HDMI encoder chip. It is a derivative of ADV7511,
with additional blocks to translate input DSI data to parallel RGB
data. Besides the ADV7511 I2C register map, it has additional registers
that require to be configured to activate the DSI Rx block.
Create a new config that enab
When the adv7511 i2c client doesn't have an interrupt line, we observe a
deadlock on caused by trying to lock drm device's mode_config.mutex twice
in the same context.
Here is the sequence that causes it:
ioctl DRM_IOCTL_MODE_GETCONNECTOR from userspace
drm_mode_getconnector (acquires mode_conf
The driver has been converted to use drm_bridge instead of
drm_i2c_slave_encoder. We can now move it to the bridge folder.
Create a separate folder since we already have a couple of files and
expect more when we support audio and ADV7533.
Rename the driver to adv7511_drv.c. This will come in hand
We don't want to use the old i2c slave encoder interface anymore.
Remove that and make the i2c driver create a drm_bridge entity instead.
Converting to bridges helps because the kms drivers don't need to
exract encoder slave ops from this driver and use it within their
own encoder/connector ops.
ADV7533 is a DSI to HDMI encoder chip. It's like ADV7511, but with an
additional DSI RX block that takes in DSI video mode output.
This revision is quite similar to the previous version with some
issues fixed.
Changes in v6:
- v5 changed the adv7511 module name to adv75xx.ko, it was previously
On 06/17/2016 11:50 AM, Mauro Carvalho Chehab wrote:
+
+ CEC_MODE_MONITOR
+ 0xe0
+ Put the file descriptor into monitor mode. Can only be used
in combination
+ with CEC_MODE_NO_INITIATOR, otherwise &EINVAL;
will be
+ returned. I
Add the DPAUX pinctrl states for the DPAUX nodes defining all three
possible states of "aux", "i2c" and "off". Also add the 'i2c-bus'
node for the DPAUX nodes so that the I2C driver core does not attempt
to parse the pinctrl state nodes.
Populate the nodes for the pinctrl clients of the DPAUX pin
Populate the 'sor-safe' clock for DPAUX devices on Tegra210 that require
this clock for operation. Update the compatability string for the DPAUX
instance at address 0x545c to be "nvidia,tegra210-dpaux" to ensure
that the 'sor-safe' clock is enabled for this device.
Signed-off-by: Jon Hunter
-
Add node for SOR power-domain for Tegra210 and populate the SOR
power-domain phandle for SOR and DPAUX nodes that are dependent
on this power-domain.
Please note that although neither the SOR or DPAUX drivers currently
support runtime power-management, by populating the power-domain node
the SOR p
The DPAUX pins are shared with an internal I2C controller. To allow
these pins to be muxed to the I2C controller, register a pinctrl device
for the DPAUX device. Make Tegra DRM support dependent on PINCTRL to
avoid any compilation issues.
Signed-off-by: Jon Hunter
---
drivers/gpu/drm/tegra/Kconf
On Tegra124, Tegra132 and Tegra210 devices the pads used by the Display
Port Auxiliary (DPAUX) channel are multiplexed such that they can also
be used by one of the internal i2c controllers. Note that this is
different from i2c-over-AUX supported by the DPAUX controller. The
register that configure
If the 'i2c-bus' device-tree node is present for an I2C adapter then
parse this subnode for I2C slaves.
Signed-off-by: Jon Hunter
---
drivers/i2c/i2c-core.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/i2c-core.c b/drivers/i2c/i2c-core.c
index 952d2
The I2C driver core for boards using device-tree assumes any subnode of
an I2C adapter in the device-tree blob as being a I2C slave device.
Although this makes complete sense, some I2C adapters may have subnodes
which are not I2C slaves but subnodes presenting other features. For
example some Tegra
The pinconf-generic.h file exposes functions for creating generic mappings
but it does not expose a function for freeing the mappings. Add a function
for freeing generic mappings.
Signed-off-by: Jon Hunter
---
drivers/pinctrl/pinconf-generic.c | 8
include/linux/pinctrl/pinconf-ge
To utilise the DPAUX on Tegra, the SOR power partition must be enabled.
Now that Tegra supports the generic PM domain framework we manage the
SOR power partition via this framework for DPAUX. However, the sequence
for gating/ungating the SOR power partition requires that the DPAUX
reset is asserted
For Tegra210 the 'sor-safe' clock needs to be enabled when using DPAUX.
Add support to the DPAUX driver for enabling this clock on Tegra210.
Signed-off-by: Jon Hunter
---
drivers/gpu/drm/tegra/dpaux.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --gi
Update the DPAUX compatibility string information for Tegra124, Tegra132
and Tegra210. For Tegra210 an additional clock, 'sor-safe' is also
required for DPAUX and so add this clock information as well.
Signed-off-by: Jon Hunter
---
.../devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
In preparation for adding pinctrl support for the DPAUX pads, add
helpers functions for configuring the pads and controlling the power
for the pads.
Please note that although a simple if-statement could be used instead
of a case statement for configuring the pads as there are only two
possible mod
If the probing of the DPAUX fails, then clocks are left enabled and the
DPAUX reset de-asserted. Add code to perform the necessary clean-up on
probe failure by disabling clocks and asserting the reset.
Signed-off-by: Jon Hunter
---
drivers/gpu/drm/tegra/dpaux.c | 22 --
1 fil
The Display Port Auxiliary (DPAUX) channel pads can be shared with an
internal I2C controller. Add pinctrl support for these pads so that the
I2C controller can request and use these pads.
Jon Hunter (13):
drm/tegra: Clean-up if probing DPAUX fails
drm/tegra: Add helper functions for setting u
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The GPU init path now reports any errors which might occur more accurately
than what is possible with the generic "something failed" message.
Remove the generic reporting, so we don't log an error into dmesg anymore
if any of the GPU cores are ignored.
Signed-off-by: Lucas Stach
---
drivers/gpu
Print error messages that mention the exact cause of the failure on
all paths which may fail the GPU init.
Signed-off-by: Lucas Stach
---
drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
b/
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On Thu, Jun 16, 2016 at 4:39 AM, Christian König
wrote:
> Am 16.06.2016 um 10:30 schrieb Dan Carpenter:
>>
>> There is no limit on high "idx" can go. It should be less than
>> ARRAY_SIZE(data.states) which is 16.
>>
>> The "data" variable wasn't declared in that scope so I shifted the code
>> ar
Avoid error print by of_graph_get_next_endpoint() if there is no ports
present.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_external.c | 13 +++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_external.c
b/drivers/gpu/drm/ti
The legacy panel.txt and tfp410.txt bindings are still the only supported
way to connect lcd panel and tfp410 DVI encoder to tilcdc.
Signed-off-by: Jyri Sarha
---
Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/dev
Add drm_crtc_vblank_on() and *_off() calls to start() and stop()
functions, to make sure any vblank waits etc. gets properly cleaned
up.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
Increase time out for waiting frame done interrupt. 50ms is long
enough for the usual display modes (50 Hz or higher refresh rate), but
it may be a bit tight for some unusual mode.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 2 +-
1 file changed, 1 insertion(+), 1 deleti
Move wait queue waiting of LCDC_FRAME_DONE IRQ from tilcdc_crtc_dpms()
into stop() function. This is just a cleanup and enables independent
use of stop() function.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 31 ---
1 file changed, 16 insertio
Reorder the IRQ function so that the write to LCDC_END_OF_INT_IND_REG
is done last. The write to LCDC_END_OF_INT_IND_REG indicates to LCDC
that the interrupt service routine has completed (see section
13.3.6.1.6 in AM335x TRM). This is needed if LCDC's ipgvmodirq module
is configured for pulse inte
Move LCDC_SYNC_LOST handling inside if (ver == 2) statement.
LCDC_SYNC_LOST interrupt status bit is only defined for version 2
silicon.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/d
Move LCDC_SYNC_LOST handling in side if (ver == 2) statement.
LCDC_SYNC_LOST interrupt status bit is only defined for version 2
silicon.
Signed-off-by: Jyri Sarha
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 21 ++---
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/
Restore old dpms state in pm_resume(). The dpms is turned off in
pm_suspend() and it should be restored to its original state in
pm_resume(). Without this patch the display is left blanked after a
suspend/resume cycle.
Fixes commit 614b3cfeb8d2 ("drm/tilcdc: disable the lcd controller/dma
engine w
Some fixes and cleanups that should get merged to tilcdc even if my
atomic changes are still a work in progress.
Yet one more round, sorry for spamming.
Changes since v4:
- Split
"drm/tilcdc: Move LCDC_SYNC_LOST handling inside if (ver == 2) statement"
out of
"drm/tilcdc: Write to LCDC_EN
Instead let drm_mode_config_cleanup() do the work when taking down
the master device. This requires all cleanup functions to be
properly hooked up to the mode object .destroy callback.
Signed-off-by: Lucas Stach
---
drivers/gpu/drm/bridge/dw-hdmi.c | 3 ---
drivers/gpu/drm/imx/imx-drm-core
Drop the load/unload driver ops, as they are deprecated because of their
inherent races, with devices being visible to userspace before they are
fully initialized.
Move this code into the driver bind/unbind routines bracketed by the
proper drm_dev_alloc/register and drm_dev_unregister/unref calls.
Make sure to leave a clean panel state behind and allow to
properly attach to the panel again on a rebind.
Signed-off-by: Lucas Stach
---
drivers/gpu/drm/imx/imx-ldb.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c
index 48166
Check the return code on panel attach. Avoids a kernel crash later
on if the attach failed.
Signed-off-by: Lucas Stach
---
drivers/gpu/drm/imx/imx-ldb.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/imx/imx-ldb.c b/drivers/gpu/drm/imx/imx-ldb.c
index
If there is no framebuffer mode that can be restored, all outputs should
be disabled in order to avoid information leaks.
Signed-off-by: Lucas Stach
---
drivers/gpu/drm/imx/imx-drm-core.c | 14 +-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/imx/imx-d
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