https://bugzilla.kernel.org/show_bug.cgi?id=201439
--- Comment #11 from fin4...@hotmail.com ---
Maybe it is the vsync option in the Xfce Compositor settings that causes the
desktop and system to freeze when the monitor is waking up from standby after
an hour. This seems to work with the latest AMD
https://bugs.freedesktop.org/show_bug.cgi?id=108781
--- Comment #11 from Daniel Vetter ---
>From the logs:
Nov 17 03:24:04 newKvm kernel: [drm:amdgpu_vce_ring_test_ring [amdgpu]] *ERROR*
amdgpu: ring 12 test failed
Nov 17 03:24:04 newKvm kernel: [drm:amdgpu_device_init.cold.14 [amdgpu]]
*ERROR*
https://bugs.freedesktop.org/show_bug.cgi?id=108760
--- Comment #6 from Alex Deucher ---
(In reply to Cheng from comment #5)
> Following on the "upstream drivers for VegaM", what do you mean
> specifically? We find that there are two open source drivers:
>
> 1) https://github.com/GPUOpen-Drivers
On 19.11.2018 10:15, Linus Walleij wrote:
> After adding the hs_rate and lp_rate fields to the DSI device
> we need to populate these accordingly so display drivers can
> respect them.
>
> Cc: Andrzej Hajda
> Cc: Chris Zhong
> Cc: Lin Huang
> Cc: Heiko Stuebner
> Tested-by: Heiko Stuebner
> Si
On 20.11.2018 13:45, Linus Walleij wrote:
> On Tue, Nov 20, 2018 at 12:02 PM Andrzej Hajda wrote:
>
>>> + /*
>>> + * The datasheet (table 39) specifies "limited clock channel speed"
>>> + * for 4 lanes as 550 Mbps for RGB888. As this is 4 bits at the time,
>>> + * the maximum HS
https://bugs.freedesktop.org/show_bug.cgi?id=107955
Ransu changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
https://bugs.freedesktop.org/show_bug.cgi?id=108760
--- Comment #5 from cheng.z...@intel.com ---
Alex,
We've tried the Open Stack, the OpenGL can work. From
https://amdgpu-install.readthedocs.io/en/latest/install-overview.html, the
Vulkan component is not in the "All-Open Stack" component list,
Hi Jordan, Vivek,
On Wed, Nov 21, 2018 at 12:41 AM Jordan Crouse wrote:
>
> On Tue, Nov 20, 2018 at 03:24:37PM +0530, Vivek Gautam wrote:
> > dma_map_sg() expects a DMA domain. However, the drm devices
> > have been traditionally using unmanaged iommu domain which
> > is non-dma type. Using dma m
https://bugs.freedesktop.org/show_bug.cgi?id=105733
--- Comment #50 from russianneuroman...@ya.ru ---
> And this is why I'm thinking that the 1800X has a defective pci-controller.
> And it is also the second part of the "really bad news". Maybe it is
> happening mostly with ryzen processors?
C
While trying to add a chamelium test for short HPD IRQs, I ran into
issues where a hotplug storm would be triggered, but the point at which
it would be reported by the kernel would be after igt actually finished
checking i915_hpd_storm_ctl's status. So, fix this by simply
synchronizing our IRQ work
https://bugs.freedesktop.org/show_bug.cgi?id=108704
--- Comment #6 from Daniel Scharrer ---
Created attachment 142530
--> https://bugs.freedesktop.org/attachment.cgi?id=142530&action=edit
lspci -vvxx output under 4.18.17-gentoo
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https://bugs.freedesktop.org/show_bug.cgi?id=108781
--- Comment #10 from jamespharve...@gmail.com ---
Bisecting results are below.
This is an Asus model STRIX-R9390-DC3OC-8GD5-GAMING.
Don't think is relevant, oter than why someone was looking at this code, but
this commit immediately trails a bu
In preparation for consolidating all ZONE_DEVICE enabling via
devm_memremap_pages(), teach it how to handle the constraints of
MEMORY_DEVICE_PRIVATE ranges.
Reviewed-by: Jérôme Glisse
[jglisse: call move_pfn_range_to_zone for MEMORY_DEVICE_PRIVATE]
Acked-by: Christoph Hellwig
Reported-by: Logan
devm semantics arrange for resources to be torn down when
device-driver-probe fails or when device-driver-release completes.
Similar to devm_memremap_pages() there is no need to support an explicit
remove operation when the users properly adhere to devm semantics.
Note that devm_kzalloc() automati
Given the fact that devm_memremap_pages() requires a percpu_ref that is
torn down by devm_memremap_pages_release() the current support for
mapping RAM is broken.
Support for remapping "System RAM" has been broken since the beginning
and there is no existing user of this this code path, so just kil
Changes since v7 [1]:
* Rebase on next-20181119
[1]: https://lkml.org/lkml/2018/10/12/878
---
At Maintainer Summit, Greg brought up a topic I proposed around
EXPORT_SYMBOL_GPL usage. The motivation was considerations for when
EXPORT_SYMBOL_GPL is warranted and the criteria for taking the
excepti
The routines hmm_devmem_add(), and hmm_devmem_add_resource() duplicated
devm_memremap_pages() and are now simple now wrappers around the core
facility to inject a dev_pagemap instance into the global pgmap_radix
and hook page-idle events. The devm_memremap_pages() interface is base
infrastructure f
Commit e8d513483300 "memremap: change devm_memremap_pages interface to
use struct dev_pagemap" refactored devm_memremap_pages() to allow a
dev_pagemap instance to be supplied. Passing in a dev_pagemap interface
simplifies the design of pgmap type drivers in that they can rely on
container_of() to l
devm_memremap_pages() is a facility that can create struct page entries
for any arbitrary range and give drivers the ability to subvert core
aspects of page management.
Specifically the facility is tightly integrated with the kernel's memory
hotplug functionality. It injects an altmap argument dee
The last step before devm_memremap_pages() returns success is to
allocate a release action, devm_memremap_pages_release(), to tear the
entire setup down. However, the result from devm_add_action() is not
checked.
Checking the error from devm_add_action() is not enough. The api
currently relies on
https://bugs.freedesktop.org/show_bug.cgi?id=108317
John changed:
What|Removed |Added
CC||john.etted...@gmail.com
--- Comment #17 from Joh
Hi,
On Wed, Nov 14, 2018 at 3:56 PM Matthias Kaehlcke wrote:
>
> On Thu, Nov 08, 2018 at 02:04:31PM -0800, Doug Anderson wrote:
> > Hi,
> >
> > On Fri, Nov 2, 2018 at 2:45 PM Matthias Kaehlcke wrote:
> > >
> > > Get the PHY ref clock from the device tree instead of hardcoding
> > > its name and
Hello,
On Tue, Nov 20, 2018 at 10:21:14PM +, Ho, Kenny wrote:
> By this reply, are you suggesting that vendor specific resources
> will never be acceptable to be managed under cgroup? Let say a user
I wouldn't say never but whatever which gets included as a cgroup
controller should have clea
Hi Tejun,
Thanks for the reply. A few clarifying questions:
On Tue, Nov 20, 2018 at 3:21 PM Tejun Heo wrote:
> So, I'm still pretty negative about adding drm controller at this
> point. There isn't enough of common resource model defined yet and
> until that gets sorted out I think it's in the
On 2018-11-07 07:55, Sean Paul wrote:
On Tue, Nov 06, 2018 at 02:36:30PM -0800, Jeykumar Sankaran wrote:
msm maintains a separate structure to define vblank
work definitions and a list to track events submitted
to the workqueue. We can avoid this redundant list
and its protection mechanism, if w
https://bugs.freedesktop.org/show_bug.cgi?id=107209
--- Comment #2 from Mike Lothian ---
It's been 4 months and I'm still getting the warning with the latest git kernel
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dri-d
https://bugs.freedesktop.org/show_bug.cgi?id=107209
Mike Lothian changed:
What|Removed |Added
CC||m...@fireburn.co.uk
--- Comment #1 from
https://bugs.freedesktop.org/show_bug.cgi?id=108709
--- Comment #8 from Lakshmi ---
(In reply to Chris Wilson from comment #7)
> (In reply to Lakshmi from comment #6)
> > Chris, this issue happened today. I believe it's the same as original bug.
> > https://intel-gfx-ci.01.org/tree/drm-tip/CI_DR
https://bugs.freedesktop.org/show_bug.cgi?id=108814
Bug ID: 108814
Summary: VMC page fault on POLARIS&RAVEN
Product: DRI
Version: unspecified
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity:
https://bugs.freedesktop.org/show_bug.cgi?id=108709
--- Comment #7 from Chris Wilson ---
(In reply to Lakshmi from comment #6)
> Chris, this issue happened today. I believe it's the same as original bug.
> https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_5173/fi-icl-y/
> igt@run...@aborted.html
https://bugs.freedesktop.org/show_bug.cgi?id=108709
Lakshmi changed:
What|Removed |Added
CC||lakshminarayana.vudum@intel
Kenny Ho writes:
> Account for the number of command submitted to amdgpu by type on a per
> cgroup basis, for the purpose of profiling/monitoring applications.
For profiling other drivers, I've used perf tracepoints, which let you
get useful timelines of multiple events in the driver. Have you
Kenny Ho writes:
> Account for the total size of buffer object requested to amdgpu by
> buffer type on a per cgroup basis.
>
> x prefix in the control file name x.bo_requested.amd.stat signify
> experimental.
Why is a counting of the size of buffer objects ever allocated useful,
as opposed to th
https://bugs.freedesktop.org/show_bug.cgi?id=107823
--- Comment #18 from Drexler ---
Hi Jan,
was wondering if you were able to review the video i uploaded?
thanks again
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https://bugs.freedesktop.org/show_bug.cgi?id=105733
--- Comment #49 from Allan ---
Haha, I knew I could count with a genuine updated valid segfault (thanks to
ryzen) :
> /var/log/kern.log:Nov 20 13:42:20 desk kernel: [ 9940.857175] Cameras
> IPC[1957]: segfault at 0 ip 55ea219b1cc2 sp 7f
Hello,
On Tue, Nov 20, 2018 at 01:58:11PM -0500, Kenny Ho wrote:
> Since many parts of the DRM subsystem has vendor-specific
> implementations, we introduce mechanisms for vendor to register their
> specific resources and control files to the DRM cgroup subsystem. A
> vendor will register itself
https://bugs.freedesktop.org/show_bug.cgi?id=108781
--- Comment #9 from jamespharve...@gmail.com ---
I have been bisecting. It's really fun that there's hundreds, maybe around a
thousand, of bisection commits that won't compile. See 4eaf317a, which
explains commits between 39b4cbad and itself ar
On 2018-11-20 12:17 p.m., Colin King wrote:
> From: Colin Ian King
>
> Currently there are several instances of pointer fs_params being
> dereferenced before fs_params is being null checked. Fix this by
> only dereferencing fs_params after the null check.
>
> Detected by CoverityScan, CID#147
https://bugs.freedesktop.org/show_bug.cgi?id=108260
--- Comment #9 from tantr...@ya.ru ---
I also have this bug with nvidia driver - no graphic login screen only console
one.
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Change-Id: Ib66c44ac1b1c367659e362a2fc05b6fbb3805876
Signed-off-by: Kenny Ho
---
drivers/gpu/drm/amd/amdgpu/Makefile | 3 ++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 7
drivers/gpu/drm/amd/amdgpu/amdgpu_drmcgrp.c | 37 +
drivers/gpu/drm/amd/amdgpu/amdgpu_dr
Since many parts of the DRM subsystem has vendor-specific
implementations, we introduce mechanisms for vendor to register their
specific resources and control files to the DRM cgroup subsystem. A
vendor will register itself with the DRM cgroup subsystem first before
registering individual DRM devi
Account for the number of command submitted to amdgpu by type on a per
cgroup basis, for the purpose of profiling/monitoring applications.
x prefix in the control file name x.cmd_submitted.amd.stat signify
experimental.
Change-Id: Ibc22e5bda600f54fe820fe0af5400ca348691550
Signed-off-by: Kenny Ho
Account for the total size of buffer object requested to amdgpu by
buffer type on a per cgroup basis.
x prefix in the control file name x.bo_requested.amd.stat signify
experimental.
Change-Id: Ifb680c4bcf3652879a7a659510e25680c2465cf6
Signed-off-by: Kenny Ho
---
drivers/gpu/drm/amd/amdgpu/amdgp
Change-Id: I6830d3990f63f0c13abeba29b1d330cf28882831
Signed-off-by: Kenny Ho
---
include/linux/cgroup_drm.h| 32
include/linux/cgroup_subsys.h | 4 +++
init/Kconfig | 5
kernel/cgroup/Makefile| 1 +
kernel/cgroup/drm.c | 46 +
The purpose of this patch series is to start a discussion for a generic cgroup
controller for the drm subsystem. The design proposed here is a very early one.
We are hoping to engage the community as we develop the idea.
Backgrounds
==
Control Groups/cgroup provide a mechanism for aggreg
From: Anusha Srivatsa
Set the suitable bits in DP_TP_CTL to stop
bit correction when DSC is disabled.
v2:
- rebased.
- Add additional check for compression state. (Gaurav)
v3: rebased.
v4:
- Move the code to the proper spot according to spec (Ville)
- Use proper checks (manasi)
v5: Remove unn
From: Gaurav K Singh
This patches does the following:
1. This patch defines all the DSC parameters as per the VESA
DSC specification. These are stored in the encoder and used
to compute the PPS parameters to be sent to the Sink.
2. Compute all the DSC parameters which are derived from DSC
state
From: Anusha Srivatsa
If the panel supports FEC, the driver has to
set the FEC_READY bit in the dpcd register:
FEC_CONFIGURATION.
This has to happen before link training.
v2: s/intel_dp_set_fec_ready/intel_dp_sink_set_fec_ready
- change commit message. (Gaurav)
v3: rebased. (r-b Manasi)
v4
Display Stream Splitter registers need to be programmed to enable
the joiner if two DSC engines are used and also to enable
the left and the right DSC engines. This happens as part of
the DSC enabling routine in the source in atomic commit.
v4:
* Remove redundant comment (Ville)
v3:
* Use cpu_tran
On Icelake, a separate power well PG2 is created for
VDSC engine used for eDP/MIPI DSI. This patch adds a new
display power domain for Power well 2.
v3:
* Call it POWER_DOMAIN_TRANSCODER_EDP_VDSC (Ville)
* Move it around TRANSCODER power domain defs (Ville)
v2:
* Fix the power well mismatch CI er
A separate power well 2 (PG2) is required for VDSC on eDP transcoder
whereas all other transcoders use the power wells associated with the
transcoders for VDSC.
This patch adds a helper to obtain correct power domain depending on
transcoder being used and enables/disables the power wells during
VDS
If a eDP panel supports both PSR2 and VDSC, our HW cannot
support both at a time. Give priority to PSR2 if a requested
resolution can be supported without compression else enable
VDSC and keep PSR2 disabled.
v4:
Fix the unrealted stuff removed during rebase (Ville)
v3:
* Rebase
v2:
* Add warning f
1. Disable Left/right VDSC branch in DSS Ctrl reg
depending on the number of VDSC engines being used
2. Disable joiner in DSS Ctrl reg
v4:
* Remove encoder, make crtc_state const (Ville)
v3 (From Manasi):
* Add Disable PG2 for VDSC on eDP
v2 (From Manasi):
* Use old_crtc_state to find dsc para
DSC PPS secondary data packet infoframes are filled with
DSC picure parameter set metadata according to the DSC standard.
These infoframes are sent to the sink device and used during DSC
decoding.
v3:
* Rename to intel_dp_write_pps_sdp (Ville)
* Use const intel_crtc_state (Ville)
v2:
* Rebase ond
From: Anusha Srivatsa
If FEC is supported, the corresponding
DP_TP_CTL register bits have to be configured.
The driver has to program the FEC_ENABLE in DP_TP_CTL[30] register
and wait till FEC_STATUS in DP_TP_CTL[28] is 1.
Also add the warn message to make sure that the control
register is alrea
After encoder->pre_enable() hook, after link training sequence is
completed, PPS registers for DSC encoder are configured using the
DSC state parameters in intel_crtc_state as part of DSC enabling
routine in the source. DSC enabling routine is called after
encoder->pre_enable() before enbaling the
This patch defines a new header file for all the DSC 1.2 structures
and creates a structure for PPS infoframe which will be used to send
picture parameter set secondary data packet for display stream compression.
All the PPS infoframe syntax elements are taken from DSC 1.2 specification
from VESA.
From: Anusha Srivatsa
For DP 1.4 and above, Display Stream compression can be
enabled only if Forward Error Correctin can be performed.
Add a crtc state for FEC. Currently, the state
is determined by platform, DP and DSC being
enabled. Moving forward we can use the state
to have error correction
Basic DSC parameters and DSC configuration data needs to be computed
for each of the requested mode during atomic check. This is
required since for certain modes, valid DSC parameters and config
data might not be computed in which case compression cannot be
enabled for that mode.
For that reason we
Infoframes are used to send secondary data packets. This patch
adds support for DSC Picture parameter set secondary data packets
in the existing write_infoframe helpers.
v3:
* Unused variables cleanup (Ville)
v2:
* Rebase on drm-tip (Manasi)
Cc: Jani Nikula
Cc: Ville Syrjala
Cc: Anusha Srivatsa
DSC params like the enable, compressed bpp, slice count and
dsc_split are added to the intel_crtc_state. These parameters
are set based on the requested mode and available link parameters
during the pipe configuration in atomic check phase.
These values are then later used to populate the remaining
According to Display Stream compression spec 1.2, the picture
parameter set metadata is sent from source to sink device
using the DP Secondary data packet. An infoframe is formed
for the PPS SDP header and PPS SDP payload bytes.
This patch adds helpers to fill the PPS SDP header
and PPS SDP payload
This patch series addresses review comments from previous series posted:
https://patchwork.freedesktop.org/series/52461/
Anusha Srivatsa (4):
i915/dp/fec: Add fec_enable to the crtc state.
drm/i915/fec: Set FEC_READY in FEC_CONFIGURATION
i915/dp/fec: Configure the Forward Error Correction bi
From: Gaurav K Singh
This computation of RC params happens in the atomic commit phase
during compute_config() to validate if display stream compression
can be enabled for the requested mode.
v7 (From Manasi):
* Use DRM_DEBUG instead of DRM_ERROR (Ville)
* Use Error numberinstead of -1 (Ville)
v6
DSC specification defines linebuf_depth which contains the
line buffer bit depth used to generate the bitstream.
These values are defined as per Table 4.1 in DSC 1.2 spec
v2 (From Manasi):
* Rename as MAX_LINEBUF_DEPTH for DSC 1.1 and DSC 1.2
Cc: dri-devel@lists.freedesktop.org
Cc: Jani Nikula
C
DSC DPCD color depth register advertises its color depth capabilities
by setting each of the bits that corresponding to a specific color
depth. This patch defines those specific color depths and adds
a helper to return an array of color depth capabilities.
v2:
* Simplify the logic (Ville)
Signed-
From: "Srivatsa, Anusha"
DSC has some Rate Control values that remain constant
across all configurations. These are as per the DSC
standard.
v3:
* Define them in drm_dsc.h as they are
DSC constants (Manasi)
v2:
* Add DP_DSC_ prefix (Jani Nikula)
Cc: dri-devel@lists.freedesktop.org
Cc: Manasi Na
From: Gaurav K Singh
This patch enables decompression support in sink device
before link training and disables the same during the
DDI disabling.
v3 (From manasi):
* Pass bool state to enable/disable (Ville)
v2:(From Manasi)
* Change the enable/disable function to take crtc_state
instead of inte
This defines all the DSC parameters as per the VESA DSC spec
that will be required for DSC encoder/decoder
v6: (From Manasi)
* Add a bit mask for RANGE_BPG_OFFSET for 6 bits(Manasi)
v5 (From Manasi)
* Add the RC constants as per the spec
v4 (From Manasi)
* Add the DSC_MUX_WORD_SIZE constants (Mana
From: Ville Syrjälä
The early return in drm_atomic_set_mode_for_crtc() isn't quite
right. It would mistakenly return and fail to update
crtc_state->enable if someone actually tried to set a zeroed
mode on a currently disabled crtc. I suppose that should never
happen but better safe than sorry.
A
From: Colin Ian King
Currently there are several instances of pointer fs_params being
dereferenced before fs_params is being null checked. Fix this by
only dereferencing fs_params after the null check.
Detected by CoverityScan, CID#1475565 ("Dereference before null check")
Fixes: e1e8a020c6b8
On Mon, Nov 19, 2018 at 10:19:42PM +0200, Ville Syrjälä wrote:
> On Tue, Nov 13, 2018 at 05:52:30PM -0800, Manasi Navare wrote:
> > From: Anusha Srivatsa
> >
> > If the panel supports FEC, the driver has to
> > set the FEC_READY bit in the dpcd register:
> > FEC_CONFIGURATION.
> >
> > This has t
Hi Liam,
I'm missing a bit of context here, but I did read the v1 thread.
Please accept my apologies if I'm re-treading trodden ground.
I do know we're chasing nebulous ion "problems" on our end, which
certainly seem to be related to what you're trying to fix here.
On Thu, Nov 01, 2018 at 03:15:
From: Ville Syrjälä
Add a second table to the cea modes with VIC >= 193.
Cc: Hans Verkuil
Cc: Shashank Sharma
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 151 -
1 file changed, 149 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/d
From: Ville Syrjälä
Fill out our list of cea modes with the new stuff from CTA-861-G.
We only do the modes with VIC < 128 here. Adding the higher
numbered VICs will need some slight code refactoring first.
Cc: Hans Verkuil
Cc: Shashank Sharma
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/
From: Ville Syrjälä
We're going to need two cea mode tables (on for VICs < 128,
another one for VICs >= 193). To that end replace the direct
edid_cea_modes[] lookups with a function call. And we'll rename
the array to edid_cea_modes_0[] to indicathe how it's to be
indexed.
Cc: Hans Verkuil
Cc:
From: Ville Syrjälä
Now that the cea mode handling is not 100% tied to the single
array the dummy VIC 0 mode is pretty much pointles. Throw it
out.
Cc: Hans Verkuil
Cc: Shashank Sharma
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/drm_edid.c | 14 +-
1 file changed, 5 insertio
thanks, it's nice to see a2xx getting some attention upstream.. few
comments inline..
On Wed, Nov 14, 2018 at 5:28 PM Jonathan Marek wrote:
>
> A2XX has its own very simple MMU.
>
> Added a msm_use_mmu() function because we can't rely on iommu_present to
> decide to use MMU or not.
>
> Signed-off
On Mon, Nov 19, 2018 at 10:15:28AM +0100, Linus Walleij wrote:
> After adding the hs_rate and lp_rate fields to the DSI device
> we need to populate these accordingly so display drivers can
> respect them.
>
> Cc: Andrzej Hajda
> Cc: Chris Zhong
> Cc: Lin Huang
> Cc: Heiko Stuebner
> Tested-by
On Tue, Nov 20, 2018 at 06:13:42PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä
>
> Make life easier for drivers by simply passing the connector
> to drm_hdmi_avi_infoframe_from_display_mode() and
> drm_hdmi_avi_infoframe_quant_range(). That way drivers don't
> need to worry about is_hdmi2_s
qxl_bo_unref() is already performing a NULL check.
Signed-off-by: Christophe Fergeau
---
drivers/gpu/drm/qxl/qxl_display.c | 4 +---
drivers/gpu/drm/qxl/qxl_draw.c| 3 +--
drivers/gpu/drm/qxl/qxl_kms.c | 6 ++
3 files changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu
QEMU keeps a vram reference to the last QXLCursorCmd it received.
This QXLCursorCmd command points to a QXLCursor instance (stored in vram
too). However, while the QXLCursorCmd memory is pinned, the QXLCursor
memory is not.
When booting a recent Fedora to its login screen while monitoring the
QXLC
The 'domain' argument to qxl_bo_pin is redundant with 'bo', and
'gpu_addr' is unused, so we can remove both.
Signed-off-by: Christophe Fergeau
---
drivers/gpu/drm/qxl/qxl_display.c | 4 ++--
drivers/gpu/drm/qxl/qxl_fb.c | 2 +-
drivers/gpu/drm/qxl/qxl_object.c | 12
drivers/
From: Ville Syrjälä
Move the CEA-861 QS bit handling entirely into the edid code. No
need to bother the drivers with this.
Cc: Alex Deucher
Cc: "Christian König"
Cc: "David (ChunMing) Zhou"
Cc: amd-...@lists.freedesktop.org
Cc: Eric Anholt (supporter:DRM DRIVERS FOR VC4)
Signed-off-by: Ville
From: Ville Syrjälä
Fill out the AVI infoframe quantization range bits using
drm_hdmi_avi_infoframe_quant_range() for SDVO HDMI encoder as well.
Signed-off-by: Ville Syrjälä
---
drivers/gpu/drm/i915/intel_sdvo.c | 19 ++-
1 file changed, 10 insertions(+), 9 deletions(-)
diff -
From: Ville Syrjälä
Fill out the AVI infoframe quantization range bits using
drm_hdmi_avi_infoframe_quant_range() instead of hand rolling it.
This changes the behaviour slightly as
drm_hdmi_avi_infoframe_quant_range() will set a non-zero Q bit
even when QS==0 iff the Q bit matched the default qu
From: Ville Syrjälä
Make life easier for drivers by simply passing the connector
to drm_hdmi_avi_infoframe_from_display_mode() and
drm_hdmi_avi_infoframe_quant_range(). That way drivers don't
need to worry about is_hdmi2_sink mess.
Cc: Alex Deucher
Cc: "Christian König"
Cc: "David (ChunMing) Z
On Tue, Nov 20, 2018 at 07:06:30PM +0530, Jagan Teki wrote:
> On Tue, Nov 20, 2018 at 6:53 PM Maxime Ripard
> wrote:
> >
> > On Mon, Nov 19, 2018 at 04:28:29PM +0530, Jagan Teki wrote:
> > > On Mon, Nov 19, 2018 at 1:57 PM Maxime Ripard
> > > wrote:
> > > >
> > > > On Fri, Nov 16, 2018 at 10:09
On Thu, Nov 15, 2018 at 11:19:53PM +0530, Jagan Teki wrote:
> On Thu, Nov 15, 2018 at 3:26 PM Maxime Ripard
> wrote:
> >
> > Hi,
> >
> > On Tue, Nov 13, 2018 at 04:46:15PM +0530, Jagan Teki wrote:
> > > The horizontal and vertical back porch calculation in BSP
> > > code is simply following the L
On Tue, Nov 20, 2018 at 05:07:31PM +0530, Sharat Masetty wrote:
> When the userspace tries to read the crashstate dump, the read side
> implementation in the driver currently ascii85 encodes all the binary
> buffers and it does this each time the read system call is called.
> A userspace tool like
On Tue, Nov 20, 2018 at 05:07:30PM +0530, Sharat Masetty wrote:
> The ring substructure in msm_gpu_state is an extension of
> msm_gpu_state_bo, so this patch changes the ring structure
> to reuse the msm_gpu_state_bo as a base class, instead of
> redefining the required variables.
>
> Signed-off-b
On Tue, Nov 20, 2018 at 05:07:29PM +0530, Sharat Masetty wrote:
> The current implementation of ascii85_encode() does not copy the encoded
> buffer 'z' to the output buffer in case the input is zero. This patch
> simply adds this missing piece. This makes it easier to use this
> function to encode
On Mon, Nov 19, 2018 at 04:30:37PM +0530, Jagan Teki wrote:
> On Mon, Nov 19, 2018 at 2:00 PM Maxime Ripard
> wrote:
> >
> > On Fri, Nov 16, 2018 at 10:09:07PM +0530, Jagan Teki wrote:
> > > Burst mode display timings are different from convectional
> > > video mode so update the horizontal and v
On Mon, Nov 19, 2018 at 05:06:32PM +0530, Jagan Teki wrote:
> On Mon, Nov 19, 2018 at 2:08 PM Maxime Ripard
> wrote:
> >
> > On Fri, Nov 16, 2018 at 10:09:10PM +0530, Jagan Teki wrote:
> > > Probe tcon0 during dsi_bind, so-that the tcon attributes like
> > > divider value, clock rate can get when
On Tue, Nov 20, 2018 at 05:07:28PM +0530, Sharat Masetty wrote:
> The ringbuffer data to capture at crashtime can end up being large
> sometimes, and the size can vary from being less than a page to the
> full size of 32KB. So use the kvmalloc variant that perfectly fits the bill.
>
> Signed-off-b
On Tue, Nov 20, 2018 at 03:24:37PM +0530, Vivek Gautam wrote:
> dma_map_sg() expects a DMA domain. However, the drm devices
> have been traditionally using unmanaged iommu domain which
> is non-dma type. Using dma mapping APIs with that domain is bad.
>
> Replace dma_map_sg() calls with dma_sync_s
Hi Uma,
On Wed, Oct 31, 2018 at 05:35:45PM +0530, Uma Shankar wrote:
>This patch adds a colorspace property enabling
>userspace to switch to various supported colorspaces.
>This will help enable BT2020 along with other colorspaces.
>
>v2: Addressed Maarten and Ville's review comments. Enhanced
>th
https://bugs.freedesktop.org/show_bug.cgi?id=108693
--- Comment #4 from Alex Deucher ---
(In reply to Andrey Arapov from comment #3)
> (In reply to Alex Deucher from comment #2)
> > This patchset may help:
> > https://patchwork.freedesktop.org/series/52164/
>
> Thank you, Alex.
>
> I can confir
On Tue, Nov 20, 2018 at 07:52:09PM +0530, Uma Shankar wrote:
> This patch adds a HDMI colorspace property, enabling
> userspace to switch to various supported colorspaces.
> This will help enable BT2020 along with other colorspaces.
>
> v2: Addressed Maarten and Ville's review comments. Enhanced
>
On Tue, Nov 20, 2018 at 02:16:38PM +, Shankar, Uma wrote:
>
>
> >-Original Message-
> >From: Chris Wilson [mailto:ch...@chris-wilson.co.uk]
> >Sent: Tuesday, November 20, 2018 7:41 PM
> >To: Shankar, Uma ; dri-devel@lists.freedesktop.org;
> >intel-...@lists.freedesktop.org
> >Cc: Syrj
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