On 29.08.2019 19:39, Rob Clark wrote:
> On Wed, Aug 28, 2019 at 11:06 PM John Stultz wrote:
>> Since commit 83f35bc3a852 ("drm/bridge: adv7511: Attach to DSI
>> host at probe time") landed in -next the HiKey board would fail
>> to boot, looping:
> No, please revert 83f35bc3a852.. that is going in
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add support for mediatek SOC MT8183
> 1.ovl_2l share driver with ovl
> 2.rdma1 share drive with rdma0, but fifo size is different
> 3.add mt8183 mutex private data, and mmsys
On Thu, Aug 29, 2019 at 11:09 PM Gerd Hoffmann wrote:
> Hi,
>
> > {
> > if (vbuf->resp_size > MAX_INLINE_RESP_SIZE)
> > kfree(vbuf->resp_buf);
> > - kfree(vbuf->data_buf);
> > + kvfree(vbuf->data_buf);
>
> if (is_vmalloc_addr(vbuf->data_buf)) ...
>
> needed here I g
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from RDMA0 to DSI0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4
> 1 file changed, 4 insert
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from DITHER0 to DSI0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
> 1 file changed, 5 ins
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from OVL_2L1 to RDMA1
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 6 ++
> 1 file changed, 6 i
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> this patch add add connection from OVL_2L0 to RDMA0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 14 ++
> 1 file
https://bugs.freedesktop.org/show_bug.cgi?id=103217
--- Comment #9 from jaimeallen ---
Much thanks for the most recent innovation. I'm completely engaged with the
post of https://icasinoreviews.info/1-dollar-deposit-casinos/for the
difficulties. The tip of the composing is devoured by me with res
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from RDMA1 to DSI0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4
> 1 file changed, 4 insert
https://bugs.freedesktop.org/show_bug.cgi?id=103217
jaimeallen changed:
What|Removed |Added
Component|Drivers/DRI/nouveau |Drivers/DRI/i915
Assignee|nouvea
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from RDMA0 to COLOR0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
> 1 file changed, 5 ins
https://bugs.freedesktop.org/show_bug.cgi?id=111524
Samuel Sieb changed:
What|Removed |Added
Summary|GPU doesn't work after |AMD A9 R5 GPU doesn't work
https://bugs.freedesktop.org/show_bug.cgi?id=111524
Bug ID: 111524
Summary: GPU doesn't work after resume
Product: DRI
Version: XOrg git
Hardware: Other
OS: All
Status: NEW
Severity: not set
Prio
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add connection from OVL0 to OVL_2L0
Reviewed-by: CK Hu
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
> 1 file changed, 5 ins
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add clock property check before get it
>
> Signed-off-by: Yongqiang Niu
> ---
> drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 10 ++
> 1 file changed, 6 insertions(+), 4
Hi,
> {
> if (vbuf->resp_size > MAX_INLINE_RESP_SIZE)
> kfree(vbuf->resp_buf);
> - kfree(vbuf->data_buf);
> + kvfree(vbuf->data_buf);
if (is_vmalloc_addr(vbuf->data_buf)) ...
needed here I gues?
> +/* Create sg_table from a vmalloc'd buffer. */
> +static struct sg
Move object release into a separate worker. Releasing objects requires
sending commands to the host. Doing that in the dequeue worker will
cause deadlocks in case the command queue gets filled up, because the
dequeue worker is also the one which will free up slots in the command
queue.
Reported-
On Thu, Aug 29, 2019 at 04:44:49PM -0700, Chia-I Wu wrote:
> The series is
>
> Reviewed-by: Chia-I Wu
Thanks.
> However I ran into a deadlock with one GPU-heavy app. When I exits
> Unigine Valley benchmark with ctrl-c, the entire driver locks up
> probably 8 out of 10 times on my machine. W
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add ovl0/ovl_2l0 usecase
> in ovl->ovl_2l0 direct link usecase:
> 1. the crtc support layer number will 4+2
> 2. ovl_2l0 background color input select ovl0 when crtc init
> an
https://bugs.freedesktop.org/show_bug.cgi?id=107877
--- Comment #30 from Kristy Murphy ---
Thanks for showing this I was also looking for the same. Keep posting and help
people like me. https://www.goassignmenthelp.com.au/assignment-help-melbourne/
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Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel
> rdma only has single output, but no multi output,
> all these rdma->dsi/dpi usecase should move to mtk_ddp_sout_sel
Hi, Yongqiang:
On Fri, 2019-08-30 at 13:27 +0800, CK Hu wrote:
> Hi, Yongqiang:
>
> On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> > From: Yongqiang Niu
> >
> > This patch add mmsys private data for ddp path config
> > all these register offset and value will be differen
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> This patch add mmsys private data for ddp path config
> all these register offset and value will be different in future SOC
> add these define into mmsys private data
> u32 ovl0_mo
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> Here is two modifition in this patch:
> 1.bls->dpi0 and rdma1->dsi are differen usecase,
> Split DISP_REG_CONFIG_DSI_SEL setting into anther usecase
> 2.remove DISP_REG_CONFIG_DPI_SEL se
Hi, Yongqiang:
On Thu, 2019-08-29 at 22:50 +0800, yongqiang@mediatek.com wrote:
> From: Yongqiang Niu
>
> Update device tree binding documention for the display subsystem for
> Mediatek MT8183 SOCs
>
> Signed-off-by: Yongqiang Niu
> ---
> .../bindings/display/mediatek/mediatek,display.txt
Hi Linus,
Nothing too crazy, there's probably more patches than I'd like at this
stage, but they are all pretty self contained.
Dave.
drm-fixes-2019-08-30:
drm fixes for 5.3-rc7
amdgpu:
- Fix GFXOFF regression for PCO and RV2
- Fix missing fence reference
- Fix VG20 power readings on certain SM
On Wed, Jul 17, 2019 at 6:28 PM Tzung-Bi Shih wrote:
>
> On Wed, Jul 17, 2019 at 4:33 PM Cheng-Yi Chiang wrote:
> >
> > This patch series supports HDMI jack reporting on RK3288, which uses
> > DRM dw-hdmi driver and hdmi-codec codec driver.
> >
> > The previous discussion about reporting jack sta
https://bugs.freedesktop.org/show_bug.cgi?id=111241
--- Comment #10 from Dieter Nützel ---
(In reply to Dieter Nützel from comment #9)
> Created attachment 145215 [details]
> Shadertoy-EOT-Grid-scene-2.png
Saw it first @ 2. November 2018
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https://bugs.freedesktop.org/show_bug.cgi?id=111241
--- Comment #9 from Dieter Nützel ---
Created attachment 145215
--> https://bugs.freedesktop.org/attachment.cgi?id=145215&action=edit
Shadertoy-EOT-Grid-scene-2.png
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https://bugs.freedesktop.org/show_bug.cgi?id=111241
--- Comment #8 from Dieter Nützel ---
BTW
Pierre-Eric can you look into this
Shadertoy shader corruption, too?
https://www.shadertoy.com/view/Xt3cWS
I get it with
Konqueror 5.0.97
KDE Frameworks 5.61.0
Qt 5.13.0
And
Firefox 68.0.1
--
You
https://bugs.freedesktop.org/show_bug.cgi?id=111241
--- Comment #7 from Dieter Nützel ---
Works for me with commit #
glsl: replace 'x + (-x)' with constant 0
https://cgit.freedesktop.org/mesa/mesa/commit/?id=47cc660d9c19572e5ef2dce7c8ae1766a2ac9885
Thanks Pierre-Eric!
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The series is
Reviewed-by: Chia-I Wu
However I ran into a deadlock with one GPU-heavy app. When I exits
Unigine Valley benchmark with ctrl-c, the entire driver locks up
probably 8 out of 10 times on my machine. When that happens,
virtio_gpu_dequeue_ctrl_func does not return and is blocked in
On Thu, Aug 29, 2019 at 02:00:01PM -0600, Mathieu Poirier wrote:
From: Jyri Sarha
commit 432973fd3a20102840d5f7e61af9f1a03c217a4c upstream
Register cpufreq notifier after we have initialized the crtc and
unregister it before we remove the ctrc. Receiving a cpufreq notify
without crtc causes a
On Thu, Aug 29, 2019 at 02:00:00PM -0600, Mathieu Poirier wrote:
From: Pedro Sousa
commit ebcb8f8508c5edf428f52525cec74d28edea7bcb upstream
Fix RX_TERMINATION_FORCE_ENABLE define value from 0x0089 to 0x00A9
according to MIPI Alliance MPHY specification.
Fixes: e785060ea3a1 ("ufs: definitions
On Thu, Aug 29, 2019 at 01:59:59PM -0600, Mathieu Poirier wrote:
From: Tomi Valkeinen
commit c08f99c39083ab55a9c93b3e93cef48711294dad upstream
We don't free the edid blob allocated by the call to drm_get_edid(),
causing a memleak. Fix this by calling kfree(edid) at the end of the
get_modes().
Hi,
On Wed, Aug 28, 2019 at 9:30 PM Cheng-Yi Chiang wrote:
>
> In the designware databook, the sequence of enabling audio clock and
> setting format is not clearly specified.
> Currently, audio clock is enabled in the end of hw_param ops after
> setting format.
>
> On some monitors, there is a po
On Sun, Aug 25, 2019 at 10:13:05PM +0800, Hillf Danton wrote:
> Can we try to add the fallback timer manually?
>
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c
> @@ -322,6 +322,10 @@ int amdgpu_fence_wait_empty(struct amdgp
> }
>
https://bugs.freedesktop.org/show_bug.cgi?id=109628
--- Comment #6 from Johannes Hirte ---
seeing similar with a Dell Latitude 5495 with AMD Ryzen 5 PRO 2500U:
kernel is 5.2.10
[ 1795.534761] [ cut here ]
[ 1795.534791] WARNING: CPU: 7 PID: 765 at
drivers/gpu/drm/amd/amd
https://bugs.freedesktop.org/show_bug.cgi?id=111414
Edmondo Tommasina changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
Userspace requested command buffer allocations could be too large
to make as a contiguous allocation. Use vmalloc if necessary to
satisfy those allocations.
Signed-off-by: David Riley
---
drivers/gpu/drm/virtio/virtgpu_ioctl.c | 4 +-
drivers/gpu/drm/virtio/virtgpu_vq.c| 74 +++
https://bugs.freedesktop.org/show_bug.cgi?id=111414
--- Comment #7 from Dieter Nützel ---
@Marek
This one could be CLOSED.
Your commit SOLVED it.
My reported 'mpv' bug is compilation related.
mpv: ../src/gallium/state_trackers/vdpau/vdpau_private.h:138:
FormatYCBCRToPipe: Assertion `0' failed.
On Thu, Aug 29, 2019 at 02:44:15PM -0400, Sean Paul wrote:
On Thu, Aug 29, 2019 at 01:06:58PM -0400, Lyude Paul wrote:
Is it worth actually CCing stable on this? This patch is certainly correct but
I don't think we use this struct for anything quite yet.
Otherwise: Reviewed-by: Lyude Paul
Th
From: Tomi Valkeinen
commit c08f99c39083ab55a9c93b3e93cef48711294dad upstream
We don't free the edid blob allocated by the call to drm_get_edid(),
causing a memleak. Fix this by calling kfree(edid) at the end of the
get_modes().
Signed-off-by: Tomi Valkeinen
Signed-off-by: Andrzej Hajda
Link:
I re-used the same scripted approach taken by Arnd [1] to look at patches
backported to TI's ti-linux-4.19.y tree [2] (the full list can be found
below). Out of the lot about a hundred were considered but most of them
either didn't apply cleanly, involved multiple files or did not compile.
The
From: Pedro Sousa
commit ebcb8f8508c5edf428f52525cec74d28edea7bcb upstream
Fix RX_TERMINATION_FORCE_ENABLE define value from 0x0089 to 0x00A9
according to MIPI Alliance MPHY specification.
Fixes: e785060ea3a1 ("ufs: definitions for phy interface")
Signed-off-by: Pedro Sousa
Signed-off-by: Mart
From: Jyri Sarha
commit 432973fd3a20102840d5f7e61af9f1a03c217a4c upstream
Register cpufreq notifier after we have initialized the crtc and
unregister it before we remove the ctrc. Receiving a cpufreq notify
without crtc causes a crash.
Reported-by: Peter Ujfalusi
Signed-off-by: Jyri Sarha
Sig
On Thu, Aug 29, 2019 at 9:11 AM Jean Delvare wrote:
>
> Hi all,
>
> Since I connected my Dell display on my Radeon R5 240 (Oland) card over
> DisplayPort instead of VGA, I get the following error messages logged at
> every boot:
>
> [drm:dce_v6_0_encoder_mode_set [amdgpu]] *ERROR* Couldn't read S
On Thu, Aug 29, 2019 at 01:06:58PM -0400, Lyude Paul wrote:
> Is it worth actually CCing stable on this? This patch is certainly correct but
> I don't think we use this struct for anything quite yet.
>
> Otherwise: Reviewed-by: Lyude Paul
Thanks for the review! I've stripped the cc stable tag an
From: Alexandre Courbot
[ Upstream commit 07098e820b9a89c570b91b1f21762f62b288 ]
This driver requires imported PRIME buffers to appear contiguously in
its IO address space. Make sure this is the case by setting the maximum
DMA segment size to a more suitable value than the default 64KB.
Sig
From: Alexandre Courbot
[ Upstream commit 4c6f3196e6ea111c456c6086dc3f57d4706b0b2d ]
PRIME buffers should be imported using the DMA device. To this end, use
a custom import function that mimics drm_gem_prime_import_dev(), but
passes the correct device.
Fixes: 119f5173628aa ("drm/mediatek: Add D
From: Alexandre Courbot
[ Upstream commit 07098e820b9a89c570b91b1f21762f62b288 ]
This driver requires imported PRIME buffers to appear contiguously in
its IO address space. Make sure this is the case by setting the maximum
DMA segment size to a more suitable value than the default 64KB.
Sig
From: Alexandre Courbot
[ Upstream commit 4c6f3196e6ea111c456c6086dc3f57d4706b0b2d ]
PRIME buffers should be imported using the DMA device. To this end, use
a custom import function that mimics drm_gem_prime_import_dev(), but
passes the correct device.
Fixes: 119f5173628aa ("drm/mediatek: Add D
From: Nicolai Hähnle
[ Upstream commit 1a701ea924815b0518733aa8d5d05c1f6fa87062 ]
Error out if the AMDGPU_CS ioctl is called with multiple SYNCOBJ_OUT and/or
TIMELINE_SIGNAL chunks, since otherwise the last chunk wins while the
allocated array as well as the reference counts of sync objects are
From: Alexandre Courbot
[ Upstream commit 07098e820b9a89c570b91b1f21762f62b288 ]
This driver requires imported PRIME buffers to appear contiguously in
its IO address space. Make sure this is the case by setting the maximum
DMA segment size to a more suitable value than the default 64KB.
Sig
From: Alexandre Courbot
[ Upstream commit 4c6f3196e6ea111c456c6086dc3f57d4706b0b2d ]
PRIME buffers should be imported using the DMA device. To this end, use
a custom import function that mimics drm_gem_prime_import_dev(), but
passes the correct device.
Fixes: 119f5173628aa ("drm/mediatek: Add D
From: Rob Clark
This reverts commit 83f35bc3a852f1c3892c7474998c5cec707c7ba3.
This commit the wrong direction, we should really be changing panel
framework to attach dsi host after probe, rather than introducing
the same probe-order problem that panels already have to bridges.
The reason is, th
On Wed, Aug 28, 2019 at 11:06 PM John Stultz wrote:
>
> Since commit 83f35bc3a852 ("drm/bridge: adv7511: Attach to DSI
> host at probe time") landed in -next the HiKey board would fail
> to boot, looping:
No, please revert 83f35bc3a852.. that is going in the *complete* wrong
direction. We actual
On Fri, Aug 23, 2019 at 05:16:36AM -0700, Brian Masney wrote:
> The files a3xx_gpu.c and a4xx_gpu.c have ifdefs for the OCMEM support
> that was missing upstream. Add two new functions (adreno_gpu_ocmem_init
> and adreno_gpu_ocmem_cleanup) that removes some duplicated code.
Reviewed-by: Jordan Cro
From: Rob Clark
This was useful for debugging fps drops. I suspect it will be useful
again.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/msm_atomic.c | 24 +++-
drivers/gpu/drm/msm/msm_atomic_trace.h | 110 ++
From: Rob Clark
In addition, moving to kms->flush_commit() lets us drop the only user
of kms->commit().
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 13 --
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 5
From: Rob Clark
Now that flush/wait/complete is decoupled from the "synchronous" part of
atomic commit_tail(), add support to defer flush to a timer that expires
shortly before vblank for async commits. In this way, multiple atomic
commits (for example, cursor updates) can be coalesced into a si
Is it worth actually CCing stable on this? This patch is certainly correct but
I don't think we use this struct for anything quite yet.
Otherwise: Reviewed-by: Lyude Paul
On Thu, 2019-08-29 at 12:52 -0400, Sean Paul wrote:
> From: Sean Paul
>
> Spec says[1] Allocated_PBN is 16 bits
>
> [1]- D
From: Rob Clark
With atomic commit, ->prepare_commit() and ->complete_commit() may not
be evenly balanced (although ->complete_commit() will complete each
crtc that had been previously prepared). So these will no longer be
a good place to enable/disable clocks needed for hw access.
Signed-off-b
From: Rob Clark
Add ->flush_commit(crtc_mask). Currently a no-op, but kms backends
should migrate writing flush registers to this hook, so we can decouple
pushing updates to hardware, and flushing the updates.
Once we add async commit support, the hw updates will be pushed down to
the hw synchr
From: Rob Clark
Prep work for async commits, in which case this will be called after we
no longer have the atomic state object.
This drops some wait_for_vblanks(), but those should be unnecessary, as
we call this after waiting for flush to complete.
Signed-off-by: Rob Clark
---
drivers/gpu/dr
From: Rob Clark
First step in re-working the atomic related internal API to prepare for
async updates pending.. ->wait_flush() is intended to block until there
is no in-progress flush.
A crtc_mask is used, rather than an atomic state object, as this will
later be used for async flush after the a
From: Rob Clark
Previously the callback was called from whoever called wait_for_vblank(),
but that isn't a great plan when wait_for_vblank() stops getting called,
and results in frame_done_timer expiring.
Signed-off-by: Rob Clark
Reviewed-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_cr
From: Rob Clark
Just waiting for next vblank isn't ideal.. we should really be looking
at the hw FLUSH register value to know if there is still an in-progress
flush without stalling unnecessarily when there is no pending flush.
Signed-off-by: Rob Clark
Reviewed-by: Sean Paul
---
.../drm/msm/d
From: Sean Paul
Spec says[1] Allocated_PBN is 16 bits
[1]- DisplayPort 1.2 Spec, Section 2.11.9.8, Table 2-98
Fixes: ad7f8a1f9ced ("drm/helper: add Displayport multi-stream helper (v0.6)")
Cc: Lyude Paul
Cc: Todd Previte
Cc: Dave Airlie
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Sean Paul
From: Rob Clark
It attempted to avoid fps drops in the presence of cursor updates. But
it is racing, and can result in hw updates after flush before vblank,
which leads to underruns.
Signed-off-by: Rob Clark
Reviewed-by: Sean Paul
---
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c| 41
"unlikely(WARN_ON(x))" is excessive. WARN_ON() already uses unlikely()
internally.
Signed-off-by: Denis Efremov
Cc: Rob Clark
Cc: Sean Paul
Cc: Joe Perches
Cc: Andrew Morton
Cc: linux-arm-...@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
---
drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c | 4
IS_ERR(), IS_ERR_OR_NULL(), IS_ERR_VALUE() and WARN*() already contain
unlikely() optimization internally. Thus, there is no point in calling
these functions and defines under likely()/unlikely().
This check is based on the coccinelle rule developed by Enrico Weigelt
https://lore.kernel.org/lkml/1
On 26.08.2019 18:27, Laurent Pinchart wrote:
> Hi Andrzej,
>
> On Thu, Aug 22, 2019 at 02:17:16PM +0200, Andrzej Hajda wrote:
>> On 20.08.2019 00:45, Laurent Pinchart wrote:
>>> On Mon, Aug 19, 2019 at 10:38:35AM +0200, Andrzej Hajda wrote:
On 14.08.2019 14:40, Daniel Vetter wrote:
> On We
From: Rob Clark
Currently the dpu backend attempts to handle async commits. But it
is racey and could result in flushing multiple times in a frame, or
modifying hw state (such as scanout address or cursor position) after
the previous flush, but before vblank, causing underflows (which
manifest a
https://bugs.freedesktop.org/show_bug.cgi?id=111482
Robert changed:
What|Removed |Added
Priority|not set |medium
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On Wed, Aug 28, 2019 at 1:36 PM Fabrizio Castro
wrote:
>
> Dear All,
>
> this series adds support for dual-LVDS panel IDK-2121WR
> from Advantech:
> https://buy.advantech.eu/Displays/Embedded-LCD-Kits-High-Brightness/model-IDK-2121WR-K2FHA2E.htm
>
> V3 approaches the problem in a completely differ
On 2019-08-28 3:52 p.m., Siqueira, Rodrigo wrote:
> DP 1.4a specification defines Link Training Tunable PHY Repeater (LTTPR)
> which is required to add support for systems with Thunderbolt or other
> repeater devices.
>
> Changes since V2:
> - Drop the kernel-doc comment
> - Reorder LTTPR accordin
On 29.08.2019 08:05, John Stultz wrote:
> Since commit 83f35bc3a852 ("drm/bridge: adv7511: Attach to DSI
> host at probe time") landed in -next the HiKey board would fail
> to boot, looping:
>
> adv7511 2-0039: failed to find dsi host
>
> messages over and over. Andrzej Hajda suggested this is du
From: Yongqiang Niu
Update device tree binding documention for the display subsystem for
Mediatek MT8183 SOCs
Signed-off-by: Yongqiang Niu
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
a/Doc
From: Yongqiang Niu
mutex sof register offset will be private data of ddp
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 13 ++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/dri
From: Yongqiang Niu
Here is two modifition in this patch:
1.bls->dpi0 and rdma1->dsi are differen usecase,
Split DISP_REG_CONFIG_DSI_SEL setting into anther usecase
2.remove DISP_REG_CONFIG_DPI_SEL setting, DPI_SEL_IN_BLS is 0 and
this is same with hardware defautl setting,
Signed-off-by: Yongqi
From: Yongqiang Niu
Update device tree binding documention for the display subsystem for
Mediatek MT8183 SOCs
Signed-off-by: Yongqiang Niu
---
.../bindings/display/mediatek/mediatek,display.txt | 21 +
1 file changed, 21 insertions(+)
create mode 100644
Documentation/dev
From: Yongqiang Niu
mutex mod register offset will be private data of ddp.
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_
From: Yongqiang Niu
This patch add commponent OVL_2L0
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 ++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp
From: Yongqiang Niu
mutex sof will be ddp private data
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 43 +++---
1 file changed, 35 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/d
From: Yongqiang Niu
This patch add component DITHER
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 32 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
2 files changed, 34 insertions(+)
diff --git a/drivers/
From: Yongqiang Niu
This patch add function to background color input select for ovl/ovl_2l direct
link
for ovl/ovl_2l direct link usecase, we need set background color
input select for these hardware.
this is preparation patch for ovl/ovl_2l usecase
Signed-off-by: Yongqiang Niu
Reviewed-by: C
From: Yongqiang Niu
This patch add mmsys private data for ddp path config
all these register offset and value will be different in future SOC
add these define into mmsys private data
u32 ovl0_mout_en;
u32 rdma1_sout_sel_in;
u32 rdma1_sout_dsi0;
u32 dpi0_sel_in;
From: Yongqiang Niu
This patch add gmc_bits for ovl private data
GMC register was set RDMA ultra and pre-ultra threshold.
10bit GMC register define is different with other SOC, gmc_thrshd_l not
used.
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c |
From: Yongqiang Niu
This patch add connection from OVL_2L1 to RDMA1
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 943e114..
From: Yongqiang Niu
This patch add connection from RDMA0 to DSI0
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index fd38658..6a7cb
From: Yongqiang Niu
This patch add component OVL_2L1
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_co
From: Yongqiang Niu
This patch add ovl0/ovl_2l0 usecase
in ovl->ovl_2l0 direct link usecase:
1. the crtc support layer number will 4+2
2. ovl_2l0 background color input select ovl0 when crtc init
and disable it when crtc finish
3. config ovl_2l0 layer, if crtc config layer number is
bigger than o
From: Yongqiang Niu
this patch add add connection from OVL_2L0 to RDMA0
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
i
From: Yongqiang Niu
This patch add support for mediatek SOC MT8183
1.ovl_2l share driver with ovl
2.rdma1 share drive with rdma0, but fifo size is different
3.add mt8183 mutex private data, and mmsys private data
4.add mt8183 main and external path module for crtc create
Signed-off-by: Yongqiang
From: Yongqiang Niu
This patch add connection from RDMA1 to DSI0
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 03a46ec..aa617
From: Yongqiang Niu
distinguish ovl and ovl_2l by layer_nr when get comp
id
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
b/drive
From: Yongqiang Niu
This patch add connection from RDMA0 to COLOR0
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 42a130a..03
From: Yongqiang Niu
This patch add connection from OVL0 to OVL_2L0
Signed-off-by: Yongqiang Niu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index effc24a..42
From: Yongqiang Niu
This patch add ddp component CCORR
Signed-off-by: Yongqiang Niu
Reviewed-by: CK Hu
---
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 32 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 2 ++
2 files changed, 34 insertions(+)
diff --git a/drive
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