Hi Linus,
Xmas eve pull request present. Just some fixes that trickled in this
past week. Mostly amdgpu fixes, with a dma-buf/mips build fix and some
misc komeda fixes.
Hope you have a good holiday season,
Dave.
drm-next-2020-12-24:
drm fixes for 5.11-rc1
dma-buf:
- fix build on mips
komeda:
[AMD Public Use]
Nice catch and the patch is:
Reviewed-by: Guchun Chen
Regards,
Guchun
-Original Message-
From: amd-gfx On Behalf Of Chenyang Li
Sent: Wednesday, December 23, 2020 9:19 AM
To: Deucher, Alexander ;
amd-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org
Hi, Chunfeng:
Chunfeng Yun 於 2020年12月16日 週三 下午5:30寫道：
>
> Convert MIPI DSI PHY binding to YAML schema mediatek,dsi-phy.yaml
>
Reviewed-by: Chun-Kuang Hu
> Cc: Chun-Kuang Hu
> Cc: Philipp Zabel
> Signed-off-by: Chunfeng Yun
> ---
> v4:
> 1. add maintainer Philipp add support mt8183
Hi, Chunfeng:
Chunfeng Yun 於 2020年12月16日 週三 下午5:30寫道：
>
> Convert HDMI PHY binding to YAML schema mediatek,hdmi-phy.yaml
>
Reviewed-by: Chun-Kuang Hu
> Cc: Chun-Kuang Hu
> Cc: Philipp Zabel
> Signed-off-by: Chunfeng Yun
> Reviewed-by: Rob Herring
> ---
> v4: add maintainer Philipp
> v3:
FWIW this is something I added, hoping it was going to get used at
some point, but I never followed up with support in xf86-video-nouveau
for Xv. At this point, I'm not sure I ever will. I encoded the
"enabled" part into the value with a high bit (1<<24) -- not sure that
was such a great idea. All
nouveau already has something for colorkey:
https://drmdb.emersion.fr/properties/4008636142/colorkey
I know this is marked "not for merge", but it would be nice to discuss
with them and come up with a standardized property.
___
dri-devel mailing list
Signed-off-by: Paul Kocialkowski
---
drivers/gpu/drm/logicvc/logicvc_drm.h | 3 +
drivers/gpu/drm/logicvc/logicvc_layer.c | 150 +++-
drivers/gpu/drm/logicvc/logicvc_layer.h | 7 ++
3 files changed, 154 insertions(+), 6 deletions(-)
diff --git
The LogiCVC multi-function device has a display part which is now
described in its binding. Add a patternProperties match for it.
Signed-off-by: Paul Kocialkowski
---
Documentation/devicetree/bindings/mfd/xylon,logicvc.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git
Introduces a driver for the LogiCVC display controller, a programmable
logic controller optimized for use in Xilinx Zynq-7000 SoCs and other
Xilinx FPGAs. The controller is mostly configured at logic synthesis
time so only a subset of configuration is left for the driver to
handle.
The following
The Xylon LogiCVC is a display controller implemented as programmable
logic in Xilinx FPGAs.
Signed-off-by: Paul Kocialkowski
Acked-by: Rob Herring
---
.../display/xylon,logicvc-display.yaml| 313 ++
1 file changed, 313 insertions(+)
create mode 100644
This series introduces support for the LogiCVC display controller.
The controller is a bit unusual since it is usually loaded as
programmable logic on Xilinx FPGAs or Zynq-7000 SoCs.
More details are presented on the main commit for the driver.
More information about the controller is available
Hi Dave, Daniel,
Fixes for 5.11.
The following changes since commit 6ae09fa49147e557eb6aebbb5b2059b63706d454:
drm/amdgpu/disply: fix documentation warnings in display manager (2020-12-16
13:27:17 -0500)
are available in the Git repository at:
git://people.freedesktop.org/~agd5f/linux
This converts the v3d bindings to yaml format.
Signed-off-by: Stefan Wahren
---
.../devicetree/bindings/gpu/brcm,bcm-v3d.txt | 33 --
.../devicetree/bindings/gpu/brcm,bcm-v3d.yaml | 76 ++
2 files changed, 76 insertions(+), 33 deletions(-)
delete mode
This small series of v3d patches is a preparation for the upcoming bcm2711
support. The bcm2711 support will be send separate, because it involves
bigger changes.
I'm not sure that the schema conversion patch is sufficient.
Patch 2,3 are directly taken from Raspberry Pi 4 vendor tree.
Nicolas
From: Phil Elwell
MMU exception conditions are reported in the V3D_MMU_CTRL register as
write-1-to-clear (W1C) bits. The MMU interrupt handling code clears any
exceptions, but does so by masking out any other bits and writing the
result back. There are some important control bits in that
From: Phil Elwell
Both coherent_dma_mask and dma_mask act as constraints on allocations
and bounce buffer usage, so be sure to set dma_mask to the appropriate
value otherwise the effective mask could be incorrect.
Signed-off-by: Phil Elwell
---
drivers/gpu/drm/v3d/v3d_drv.c | 4 ++--
1 file
From: Nicolas Saenz Julienne
Aside from being more correct, the non optional version of the function
prints an error when failing to find the IRQ.
Signed-off-by: Nicolas Saenz Julienne
---
drivers/gpu/drm/v3d/v3d_irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
This converts the v3d bindings to yaml format.
Signed-off-by: Stefan Wahren
---
.../devicetree/bindings/gpu/brcm,bcm-v3d.txt | 33 --
.../devicetree/bindings/gpu/brcm,bcm-v3d.yaml | 76 ++
2 files changed, 76 insertions(+), 33 deletions(-)
delete mode
This small series of v3d patches is a preparation for the upcoming bcm2711
support. The bcm2711 support will be send separate, because it involves
bigger changes.
I'm not sure that the schema conversion patch is sufficient.
Patch 2,3 are directly taken from Raspberry Pi 4 vendor tree.
Changes
From: Phil Elwell
Both coherent_dma_mask and dma_mask act as constraints on allocations
and bounce buffer usage, so be sure to set dma_mask to the appropriate
value otherwise the effective mask could be incorrect.
Signed-off-by: Phil Elwell
Signed-off-by: Stefan Wahren
---
From: Phil Elwell
MMU exception conditions are reported in the V3D_MMU_CTRL register as
write-1-to-clear (W1C) bits. The MMU interrupt handling code clears any
exceptions, but does so by masking out any other bits and writing the
result back. There are some important control bits in that
From: Nicolas Saenz Julienne
Aside from being more correct, the non optional version of the function
prints an error when failing to find the IRQ.
Signed-off-by: Nicolas Saenz Julienne
Signed-off-by: Stefan Wahren
---
drivers/gpu/drm/v3d/v3d_irq.c | 2 +-
1 file changed, 1 insertion(+), 1
tree: git://anongit.freedesktop.org/drm-intel topic/core-for-CI
head: 86ba40501c85c1275aa841768b5dbd56ce993aac
commit: 2a010f39b156cdc856dd7460992789c2e1e578ee [18/26] Revert "drm/i915:
Don't select BROKEN"
config: powerpc64-randconfig-r016-20201221 (attached as .config)
compiler: clang
Hi Rob,
> > With one comment below,
> > Acked-by: Sam Ravnborg
> >
> > > ---
> > > diff --git a/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> > > b/Documentation/devicetree/bindings/usb/renesas,usbhs.yaml
> > > index 737c1f47b7de..54c361d4a7af 100644
> > > ---
Adding the missing property power-domains to the bcm2835-vec schema to fix
the following dtbs_check issue:
vec@7e806000: 'power-domains' does not match any of the regexes: ...
Signed-off-by: Stefan Wahren
---
Documentation/devicetree/bindings/display/brcm,bcm2835-vec.yaml | 3 +++
1 file
Hi "Isaac,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on iommu/next]
[also build test WARNING on soc/for-next xlnx/master linus/master v5.10
next-20201223]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patc
https://bugzilla.kernel.org/show_bug.cgi?id=210849
--- Comment #4 from xrootw...@gmail.com ---
Have new error messages linkied with it, i think
drm failed to load unicode id
amdgpu: RAP: optional rap ta ucode is not available
kernel 5.10.2
--
You may reply to this email to add a comment.
You
https://bugzilla.kernel.org/show_bug.cgi?id=209457
xrootw...@gmail.com changed:
What|Removed |Added
CC||xrootw...@gmail.com
--- Comment
On Wed, Dec 23, 2020 at 10:54:26AM -0700, Rob Herring wrote:
> On Mon, Dec 21, 2020 at 11:39 PM Sam Ravnborg wrote:
> >
> > Hi Rob,
> >
> > On Mon, Dec 21, 2020 at 09:06:45PM -0700, Rob Herring wrote:
> > > 'maxItems' equal to the 'items' list length is redundant. 'maxItems' is
> > > preferred
On Mon, Dec 21, 2020 at 11:39 PM Sam Ravnborg wrote:
>
> Hi Rob,
>
> On Mon, Dec 21, 2020 at 09:06:45PM -0700, Rob Herring wrote:
> > 'maxItems' equal to the 'items' list length is redundant. 'maxItems' is
> > preferred for a single entry while greater than 1 should have an 'items'
> > list.
> >
On Fri, 04 Dec 2020, Lyude Paul wrote:
> Since we now support controlling panel backlights through DPCD using
> both the standard VESA interface, and Intel's proprietary HDR backlight
> interface, we should allow the user to be able to explicitly choose
> between one or the other in the event
On Fri, 04 Dec 2020, Lyude Paul wrote:
> So-recently a bunch of laptops on the market have started using DPCD
> backlight controls instead of the traditional DDI backlight controls.
> Originally we thought we had this handled by adding VESA backlight
> control support to i915, but the story ended
On Fri, 04 Dec 2020, Lyude Paul wrote:
> Currently, every different type of backlight hook that i915 supports is
> pretty straight forward - you have a backlight, probably through PWM
> (but maybe DPCD), with a single set of platform-specific hooks that are
> used for controlling it.
>
> HDR
On Fri, 04 Dec 2020, Lyude Paul wrote:
> A while ago we ran into issues while trying to enable the eDP backlight
> control interface as defined by VESA, in order to make the DPCD
> backlight controls on newer laptop panels work. The issue ended up being
> much more complicated however, as we also
Hi, Yongqiang:
Yongqiang Niu 於 2020年12月23日 週三 上午9:37寫道：
>
> On Tue, 2020-12-15 at 07:40 +0800, Chun-Kuang Hu wrote:
> > Hi, Yongqiang:
> >
> > Yongqiang Niu 於 2020年12月12日 週六 下午12:13寫道：
> > >
> > > fix gamma size config
> >
> > I would like you to provide more information. The original code
Hi John,
Just a couple nits, otherwise looks sane to me.
On Thu, Dec 17, 2020 at 3:06 PM John Stultz wrote:
>
> This patch provides infrastructure for deferring buffer frees.
>
> This is a feature ION provided which when used with some form
> of a page pool, provides a nice performance boost in
On Tue, Dec 22, 2020 at 09:55:28AM +0100, Daniel Vetter wrote:
> On Fri, Dec 11, 2020 at 05:11:13PM +0100, Daniel Vetter wrote:
> > I tried to fix this for real, but it's very sprawling and lots of
> > drivers get this mildly wrong one way or the other.
> >
> > Signed-off-by: Daniel Vetter
> >
On 2020-12-22 19:54, isa...@codeaurora.org wrote:
On 2020-12-22 11:27, Robin Murphy wrote:
On 2020-12-22 00:44, Isaac J. Manjarres wrote:
The io-pgtable code constructs an array of init functions for each
page table format at compile time. This is not ideal, as this
increases the footprint of
On 2020-12-22 19:49, isa...@codeaurora.org wrote:
On 2020-12-22 11:27, Robin Murphy wrote:
On 2020-12-22 00:44, Isaac J. Manjarres wrote:
The SMMU driver depends on the availability of the ARM LPAE and
ARM V7S io-pgtable format code to work properly. In preparation
Nit: we don't really
On 22-12-20, 22:15, Dmitry Osipenko wrote:
> 22.12.2020 09:42, Viresh Kumar пишет:
> > On 17-12-20, 21:06, Dmitry Osipenko wrote:
> >> Add a ceil version of the dev_pm_opp_find_level(). It's handy to have if
> >> levels don't start from 0 in OPP table and zero usually means a minimal
> >> level.
>
On Tue, 2020-12-15 at 22:49 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
>
> Yongqiang Niu 於 2020年12月12日 週六 下午12:12寫道：
> >
> > add description for postmask
>
> What is postmask? I google it and find a postmask ECO. So it is postmask ECO?
>
> Regards,
> Chun-Kuang.
>
it is used control round
On Sun, 2020-12-13 at 09:15 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
>
> Yongqiang Niu 於 2020年12月12日 週六 下午12:12寫道：
> >
> > This patch add component OVL_2L2
>
> Break drm part and soc part into different patches.
>
> Regards,
> Chun-Kuang.
will be fixed in next version
>
> >
> >
On Mon, Dec 21, 2020 at 10:10 PM Rob Herring wrote:
>
> 'maxItems' equal to the 'items' list length is redundant. 'maxItems' is
> preferred for a single entry while greater than 1 should have an 'items'
> list.
>
> A meta-schema check for this is pending once these existing cases are
> fixed.
>
>
On 17-12-20, 21:06, Dmitry Osipenko wrote:
> Support set_opp() customization without requiring to use regulators. This
> is needed by drivers which want to use dev_pm_opp_set_rate() for changing
> rates of a multiple clocks and don't need to touch regulator.
>
> One example is NVIDIA Tegra30/114
Don't open-code DIV_ROUND_UP() kernel macro.
Signed-off-by: Zheng Yongjun
---
drivers/gpu/drm/radeon/r600_cs.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 390a9621604a..a3aea5329712 100644
---
On Tue, 2020-12-15 at 21:37 +0800, Nicolas Boichat wrote:
> On Sat, Dec 12, 2020 at 12:12 PM Yongqiang Niu
> wrote:
> >
> > there are 2 more clock need enable for display.
> > parser these clock when mutex device probe,
> > enable and disable when mutex on/off
> >
> > Signed-off-by: Yongqiang Niu
In line 24 "_AMDGPU_TRACE_H" is missing an underscore.
Signed-off-by: Chenyang Li
---
drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index
Add address shift when compose jump instruction
to compatible with 35bit format.
Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform")
Signed-off-by: Yongqiang Niu
Reviewed-by: Nicolas Boichat
---
drivers/mailbox/mtk-cmdq-mailbox.c | 3 ++-
1 file changed, 2
22.12.2020 22:21, Dmitry Osipenko пишет:
>>> + if (IS_ERR(opp)) {
>>> + dev_err(>dev, "failed to find OPP for level %u: %pe\n",
>>> + level, opp);
>>> + return PTR_ERR(opp);
>>> + }
>>> +
>>> + err = dev_pm_opp_set_voltage(>dev, opp);
>> IIUC, you
On 22-12-20, 22:19, Dmitry Osipenko wrote:
> 22.12.2020 12:12, Viresh Kumar пишет:
> > On 17-12-20, 21:06, Dmitry Osipenko wrote:
> >> Fix adding OPP entries in a wrong (opposite) order if OPP rate is
> >> unavailable. The OPP comparison is erroneously skipped if OPP rate is
> >> missing, thus
On Wed, 2020-12-16 at 23:17 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
>
> Yongqiang Niu 於 2020年12月12日 週六 下午12:12寫道：
> >
> > add CLK_MM_DISP_CONFIG control description for mt8192 displa
>
> display
>
> >
> > Signed-off-by: Yongqiang Niu
> > ---
> >
On Tue, 2020-12-15 at 21:42 +0800, Nicolas Boichat wrote:
> On Sat, Dec 12, 2020 at 12:13 PM Yongqiang Niu
> wrote:
> >
> > Use function call for setting mmsys ovl mout register
> >
> > Signed-off-by: Yongqiang Niu
> > ---
> > drivers/soc/mediatek/mmsys/mtk-mmsys.c | 18 ++
> >
22.12.2020 12:01, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> Support set_opp() customization without requiring to use regulators. This
>> is needed by drivers which want to use dev_pm_opp_set_rate() for changing
>> rates of a multiple clocks and don't need to touch
22.12.2020 12:15, Viresh Kumar пишет:
> On 18-12-20, 16:51, Dmitry Osipenko wrote:
>> Alright, although I haven't pretended that v2 patches should be merged
>> right away since they are fundamentally different from v1, and thus, all
>> patches need to be reviewed first.
>
> I agree. I have done
kref_put() can be outside of mutex_lock(),and use amdgpu_ctx_put()
instead of kref_put().
Signed-off-by: Yejune Deng
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c
Add the callback functions of drm_driver structure member functions
load and unload, no need to call load in the hibmc_pci_probe function
and unload in the hibmc_pci_remove function.
Signed-off-by: Tian Tao
---
drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 17 +++--
1 file
On 2020-12-22 11:27, Robin Murphy wrote:
On 2020-12-22 00:44, Isaac J. Manjarres wrote:
The io-pgtable code constructs an array of init functions for each
page table format at compile time. This is not ideal, as this
increases the footprint of the io-pgtable code, as well as prevents
io-pgtable
22.12.2020 09:42, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> Add a ceil version of the dev_pm_opp_find_level(). It's handy to have if
>> levels don't start from 0 in OPP table and zero usually means a minimal
>> level.
>>
>> Signed-off-by: Dmitry Osipenko
>
> Why doesn't
On 22-12-20, 22:39, Dmitry Osipenko wrote:
> 22.12.2020 22:21, Dmitry Osipenko пишет:
> >>> + if (IS_ERR(opp)) {
> >>> + dev_err(>dev, "failed to find OPP for level %u: %pe\n",
> >>> + level, opp);
> >>> + return PTR_ERR(opp);
> >>> + }
> >>> +
> >>> + err =
22.12.2020 08:47, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> diff --git a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
>> b/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
>> index b84afecea154..7e015cdfbc55 100644
>> --- a/arch/arm/boot/dts/tegra20-peripherals-opp.dtsi
On Mon, 2020-12-21 at 15:29 -0700, Rob Herring wrote:
> On Thu, Dec 17, 2020 at 05:59:26PM +0800, Liu Ying wrote:
> > This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
> > The pixel link forms a standard asynchronous linkage between
> > pixel sources(display controller or
On 18-12-20, 16:51, Dmitry Osipenko wrote:
> Alright, although I haven't pretended that v2 patches should be merged
> right away since they are fundamentally different from v1, and thus, all
> patches need to be reviewed first.
I agree. I have done some basic review for the stuff.
> If the
22.12.2020 03:14, Rob Herring пишет:
> On Thu, Dec 17, 2020 at 09:05:56PM +0300, Dmitry Osipenko wrote:
>> Document "clocks" sub-node which describes Tegra SoC clocks that require
>> a higher voltage of the core power domain in order to operate properly on
>> a higher rates.
>
> Seems like an odd
Hi Laurent Pinchart
Thanks for reply.
-Original Message-
From: Laurent Pinchart [mailto:laurent.pinch...@ideasonboard.com]
Sent: Wednesday, December 23, 2020 12:20 AM
To: Allen Chen (陳柏宇)
Cc: Jau-Chih Tseng (曾昭智); Hermes Wu (吳佳宏); Kenneth Hung (洪家倫);
pih...@chromium.org;
Hibmc use the devm_drm_dev_alloc function in hibmc_pci_probe, if
hibmc_pci_probe returns non-zero, devm_drm_dev_alloc will call
devm_drm_dev_init, which will call devm_drm_dev_init_release to
release drm_dev_put. There is no need for hibmc to call
drm_dev_put separately.
Signed-off-by: Tian Tao
On Tue, 2020-12-15 at 07:40 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
>
> Yongqiang Niu 於 2020年12月12日 週六 下午12:13寫道：
> >
> > fix gamma size config
>
> I would like you to provide more information. The original code works
> in mt8173, why do you modify this? The description may be something
>
22.12.2020 01:54, Rob Herring пишет:
> On Thu, Dec 17, 2020 at 09:05:52PM +0300, Dmitry Osipenko wrote:
>> Power domain fits much better than a voltage regulator in regards to
>> a proper hardware description and from a software perspective as well.
>> Hence replace the core regulator with the
On 2020-12-22 11:27, Robin Murphy wrote:
On 2020-12-22 00:44, Isaac J. Manjarres wrote:
The SMMU driver depends on the availability of the ARM LPAE and
ARM V7S io-pgtable format code to work properly. In preparation
Nit: we don't really depend on v7s - we *can* use it if it's
available,
22.12.2020 12:14, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
>> b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
>> index cbe84d25e726..983db1a06682 100644
>> --- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
On Wed, 2020-12-16 at 23:10 +0800, Chun-Kuang Hu wrote:
> Hi, Yongqiang:
>
> Yongqiang Niu 於 2020年12月12日 週六 下午12:22寫道：
> >
> > fix aal size config
> >
> > Fixes: 0664d1392c26 (drm/mediatek: Add AAL engine basic function)
> > Signed-off-by: Yongqiang Niu
> > ---
> >
22.12.2020 09:40, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> +++ b/drivers/soc/tegra/core-power-domain.c
>> @@ -0,0 +1,125 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * NVIDIA Tegra SoC Core Power Domain Driver
>> + */
>> +
>> +#include
>> +#include
>>
On Thu, 2020-12-17 at 17:59 +0800, Liu Ying wrote:
> This patch adds a drm bridge driver for i.MX8qxp LVDS display bridge(LDB).
> The LDB has two channels. Each of them supports up to 24bpp parallel
> input color format and can map the input to VESA or JEIDA standards.
> The two channels cannot
Hi,
On Tue, 2020-12-22 at 09:09 +0200, Laurent Pinchart wrote:
> Hi Liu,
>
> Thank you for the patch.
>
> On Thu, Dec 17, 2020 at 05:59:25PM +0800, Liu Ying wrote:
> > This patch adds bindings for i.MX8qm/qxp display pixel link.
> >
> > Signed-off-by: Liu Ying
> > ---
> >
22.12.2020 11:59, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> A required OPP may not be available, and thus, all OPPs which are using
>> this required OPP should be unavailable too.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> drivers/opp/core.c | 11 ++-
>> 1
22.12.2020 11:55, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> Add resource-managed versions of OPP API functions. This removes a need
>> from drivers to store and manage OPP table pointers.
>>
>> Signed-off-by: Dmitry Osipenko
>> ---
>> drivers/opp/core.c | 173
On 22-12-20, 22:17, Dmitry Osipenko wrote:
> 22.12.2020 11:59, Viresh Kumar пишет:
> > On 17-12-20, 21:06, Dmitry Osipenko wrote:
> >> A required OPP may not be available, and thus, all OPPs which are using
> >> this required OPP should be unavailable too.
> >>
> >> Signed-off-by: Dmitry Osipenko
22.12.2020 12:12, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> Fix adding OPP entries in a wrong (opposite) order if OPP rate is
>> unavailable. The OPP comparison is erroneously skipped if OPP rate is
>> missing, thus OPPs are left unsorted.
>>
>> Signed-off-by: Dmitry
On Thu, 2020-12-17 at 14:04 +0800, Hsin-Yi Wang wrote:
> On Wed, Dec 9, 2020 at 9:32 AM Yongqiang Niu
> wrote:
> >
> > Actually, setting the registers for routing, use multiple 'if-else' for
> > different
> > routes, but this code would be more and more complicated while we
> > support more and
Hi
It has been about two weeks since I posted v6 and haven't heard anything.
Consider this a gentle ping.
Just wondering if the set needs additional work and I will fix and upstream
again.
Thanks.
-Original Message-
From: Allen Chen (陳柏宇)
Sent: Tuesday, December 08, 2020 6:58 PM
Cc:
On 17-12-20, 21:06, Dmitry Osipenko wrote:
> diff --git a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
> b/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
> index cbe84d25e726..983db1a06682 100644
> --- a/arch/arm/boot/dts/tegra30-peripherals-opp.dtsi
> +++
Change since v1:
-move out from mt8192 seri series
Yongqiang Niu (1):
soc: mediatek: cmdq: add address shift in jump
drivers/mailbox/mtk-cmdq-mailbox.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
--
1.8.1.1.dirty
___
dri-devel mailing
Am 21.12.20 um 09:57 schrieb Chen Li:
When using e8860(gcn1) on arm64, the kernel crashed on drm/radeon:
[ 11.240414] pc : __memset+0x4c/0x188
[ 11.244101] lr : radeon_uvd_get_create_msg+0x114/0x1d0 [radeon]
[ 11.249995] sp : 0d7eb700
[ 11.253295] x29: 0d7eb700 x28:
Am 21.12.20 um 10:05 schrieb Chen Li:
On modern gpus, GTT (system memory) works as well here, and this may
also be a workaround for platforms which cannot map vram correctly.
Signed-off-by: chenli
Reviewed-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 4 ++--
1 file
Hi Maarten, Maxime, and Thomas -
Here's the DP-HDMI2.1 PCON support topic pull consisting of the series
[1]. The series is split roughly 50-50 between drm helpers and i915, so
a topic branch seemed to be the right way to go.
I'll also pull this to drm-intel-next once you've merged to
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