https://bugzilla.kernel.org/show_bug.cgi?id=216359
--- Comment #1 from Shlomo (shl...@fastmail.com) ---
Reposted on GitLab:
https://gitlab.freedesktop.org/drm/amd/-/issues/2124
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On 8/15/2022 4:35 PM, Christian König wrote:
Am 12.08.22 um 15:30 schrieb Arunpravin Paneer Selvam:
We are adding two new callbacks to ttm resource manager
function to handle intersection and compatibility of
placement and resources.
v2: move the amdgpu and ttm_range_manager changes to
Hi dee Ho Mark, Laurent, Stephen, all
On 8/16/22 01:55, Mark Brown wrote:
On Tue, Aug 16, 2022 at 12:17:17AM +0300, Laurent Pinchart wrote:
On Mon, Aug 15, 2022 at 01:58:55PM -0700, Stephen Boyd wrote:
You will very quickly see drivers doing this (either directly or
indirectly):
probe()
On mobile workstations like HP ZBook Fury G8, iGFX's DP-IN can switch to
dGFX so external monitors are routed to dGFX, and more monitors can be
supported as result.
To switch the DP-IN to dGFX, the driver needs to invoke _DSM function 20
on intel_dsm_guid2. This method is described in Intel
Some additional MMIO tuning settings have appeared in the bspec's
performance tuning guide section.
One of the tuning settings here is also documented as formal workaround
Wa_22012654132 for some steppings of DG2. However the tuning setting
applies to all DG2 variants and steppings, making it a
Host Turbo operates at efficient frequency when GT is not idle unless
the user or workload has forced it to a higher level. Replicate the same
behavior in SLPC by allowing the algorithm to use efficient frequency.
We had disabled it during boot due to concerns that it might break
kernel ABI for
On Tue, Aug 16, 2022 at 12:17:17AM +0300, Laurent Pinchart wrote:
> On Mon, Aug 15, 2022 at 01:58:55PM -0700, Stephen Boyd wrote:
> > The basic idea is that drivers should be focused on what they're
> > driving, not navigating the (sometimes) complex integration that's
> > taking place around
On 8/11/2022 14:08, Daniele Ceraolo Spurio wrote:
If the GuC CTs are full and we need to stall the request submission
while waiting for space, we save the stalled request and where the stall
occurred; when the CTs have space again we pick up the request submission
from where we left off.
If a
On Mon, Aug 15, 2022 at 01:58:55PM -0700, Stephen Boyd wrote:
> Quoting Laurent Pinchart (2022-08-15 11:52:36)
> > On Mon, Aug 15, 2022 at 05:33:06PM +0100, Mark Brown wrote:
> > > On Mon, Aug 15, 2022 at 06:54:45PM +0300, Laurent Pinchart wrote:
> > > > - With devres, you don't have full control
Hi Stephan,
On Mon, Aug 15, 2022 at 01:58:55PM -0700, Stephen Boyd wrote:
> Quoting Laurent Pinchart (2022-08-15 11:52:36)
> > On Mon, Aug 15, 2022 at 05:33:06PM +0100, Mark Brown wrote:
> > > On Mon, Aug 15, 2022 at 06:54:45PM +0300, Laurent Pinchart wrote:
> > >
> > > > - With devres, you
From: Rob Clark
Signed-off-by: Rob Clark
---
drivers/gpu/drm/msm/msm_gem.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 1dee0d18abbb..1db53545ac40 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++
From: Rob Clark
Just plumbing the thing thru an extra layer.
Signed-off-by: Rob Clark
---
drivers/gpu/drm/drm_prime.c | 3 +++
include/drm/drm_gem.h | 11 +++
2 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c
index
From: Rob Clark
This is a fairly narrowly focused interface, providing a way for a VMM
in userspace to tell the guest kernel what pgprot settings to use when
mapping a buffer to guest userspace.
For buffers that get mapped into guest userspace, virglrenderer returns
a dma-buf fd to the VMM
From: Rob Clark
See 1/3 for motivation.
Rob Clark (3):
dma-buf: Add ioctl to query mmap coherency/cache info
drm/prime: Wire up mmap_info support
drm/msm/prime: Add mmap_info support
drivers/dma-buf/dma-buf.c | 63 ++--
drivers/gpu/drm/drm_prime.c | 3
Le 15/08/2022 à 17:56, Wei Liu a écrit :
All that said, the fix looks good, so
Reviewed-by: Michael Kelley
I made the two changes listed above and applied this patch to
hyperv-fixes.
Thanks a lot, that saves me a v2.
CJ
Thanks,
Wei.
Quoting Laurent Pinchart (2022-08-15 11:52:36)
> Hi Mark,
>
> On Mon, Aug 15, 2022 at 05:33:06PM +0100, Mark Brown wrote:
> > On Mon, Aug 15, 2022 at 06:54:45PM +0300, Laurent Pinchart wrote:
> >
> > > - With devres, you don't have full control over the order in which
> > > resources will be
Applied the series. Thanks!
Alex
On Wed, Aug 10, 2022 at 7:30 PM André Almeida wrote:
>
> Add comments to document gfx_off related members of struct amdgpu_gfx.
>
> Signed-off-by: André Almeida
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 12 ++--
> 1 file changed, 6
Applied. Thanks!
On Sat, Aug 13, 2022 at 11:35 AM min tang wrote:
>
> There is no semicolon after '}' in line 510.
>
> Signed-off-by: min tang
> ---
> drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
Applied. Thanks!
On Sat, Aug 13, 2022 at 11:13 AM min tang wrote:
>
> The double `aligned' is duplicated in line 1070, remove one.
>
> Signed-off-by: min tang
> ---
> drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git
Applied. Thanks!
On Fri, Aug 12, 2022 at 7:13 AM Christian König
wrote:
>
> @Alex was that one already picked up?
>
> Am 25.07.22 um 18:40 schrieb Andrey Grodzovsky:
> > Reviewed-by: Andrey Grodzovsky
> >
> > Andrey
> >
> > On 2022-07-19 06:39, Andrey Strachuk wrote:
> >> Local variable 'rq'
From: Thomas Zimmermann
[ Upstream commit 5913ab941d6ea782e841234c76958c6872ea752d ]
DDC operation conflicts with concurrent mode setting. Acquire the
driver's I/O lock in get_modes to prevent this. This change should
have been part of commit 931e3f3a0e99 ("drm/mgag200: Protect
concurrent
From: Marek Vasut
[ Upstream commit 16c8d76abe83d75b578d72ee22d25a52c764e14a ]
Add missing reg and reg-names properties for both 'LDB_CTRL'
and 'LVDS_CTRL' registers.
Fixes: 463db5c2ed4ae ("drm: bridge: ldb: Implement simple Freescale i.MX8MP LDB
bridge")
Signed-off-by: Marek Vasut
Cc:
From: Thomas Zimmermann
commit 009a3a52791f31c57d755a73f6bc66fbdd8bd76c upstream.
Fix a number of compile errors by including the correct header
files. Examples are shown below.
../drivers/gpu/drm/hyperv/hyperv_drm_modeset.c: In function
'hyperv_blit_to_vram_rect':
Allows submitting jobs as gang which needs to run on multiple
engines at the same time.
Basic idea is that we have a global gang submit fence representing when the
gang leader is finally pushed to run on the hardware last.
Jobs submitted as gang are never re-submitted in case of a GPU reset
Move setting the job resources into amdgpu_job.c
Signed-off-by: Christian König
Reviewed-by: Andrey Grodzovsky
Reviewed-by: Luben Tuikov
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 21 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 17 +
We should not have any different CS constrains based
on the execution environment.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
This reverts commit 250195ff744f260c169f5427422b6f39c58cb883.
The job should now be initialized when we reach the parser functions.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 17 ++---
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git
Similar to what we did for VCN3 use the job instead of the parser
entity. Cleanup the coding style quite a bit as well.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 46 +++
1 file changed, 25 insertions(+), 21 deletions(-)
diff --git
Allows submitting jobs as gang which needs to run on multiple engines at the
same time.
All members of the gang get the same implicit, explicit and VM dependencies. So
no gang member will start running until everything else is ready.
The last job is considered the gang leader (usually a
We already discussed that the call to drm_sched_entity_select_rq() needs
to move to drm_sched_job_arm() to be able to set a new scheduler list
between _init() and _arm(). This was just not applied for some reason.
Signed-off-by: Christian König
Reviewed-by: Andrey Grodzovsky
---
This reverts commit 94f4c4965e5513ba624488f4b601d6b385635aec.
We found that the bo_list is missing a protection for its list entries.
Since that is fixed now this workaround can be removed again.
Signed-off-by: Christian König
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 21
So I think we can push this now. Alex, can you take a look the the
remaining patches which don't have any rb yet.
Thanks,
Christian.
From: Thomas Zimmermann
commit 009a3a52791f31c57d755a73f6bc66fbdd8bd76c upstream.
Fix a number of compile errors by including the correct header
files. Examples are shown below.
../drivers/gpu/drm/hyperv/hyperv_drm_modeset.c: In function
'hyperv_blit_to_vram_rect':
Hi Mark,
On Mon, Aug 15, 2022 at 05:33:06PM +0100, Mark Brown wrote:
> On Mon, Aug 15, 2022 at 06:54:45PM +0300, Laurent Pinchart wrote:
>
> > - With devres, you don't have full control over the order in which
> > resources will be released, which means that you can't control the
> > power
This patchset introduces a Linux Kernel driver (QAIC - Qualcomm AIC) for the
Qualcomm Cloud AI 100 product (AIC100).
Qualcomm Cloud AI 100 is a PCIe adapter card that hosts a dedicated machine
learning inference accelerator. Tons of documentation in the first patch of
the series.
The driver was
A QAIC device has a number of attributes like thermal limits which can be
read and in some cases, controlled from the host. Expose these attributes
via hwmon. Use the pre-defined interface where possible, but define
custom interfaces where it is not possible.
Change-Id:
Add debugfs entries that dump information about the dma_bridge fifo state
and also the SBL boot log.
Change-Id: Ib46b84c07c25afcf0ac2c73304cf6275689d002e
Signed-off-by: Jeffrey Hugo
---
drivers/gpu/drm/qaic/qaic_debugfs.c | 335
Add the control path component that talks to the management processor to
load workloads onto the qaic device. This implements the driver portion
of the NNC protocol.
Change-Id: Ic9c0be41a91532843b78e49b32cf1fcf39faeb9f
Signed-off-by: Jeffrey Hugo
---
drivers/gpu/drm/qaic/qaic_control.c | 1788
Add MAINTAINERS entry for the Qualcomm Cloud AI 100 driver.
Change-Id: I149dbe34f1dbaeeca449b4ebf97f274c7484ed27
Signed-off-by: Jeffrey Hugo
---
MAINTAINERS | 7 +++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index cd0f68d..695654c 100644
--- a/MAINTAINERS
+++
Add QAIC specific tracepoints which can be useful in debugging issues.
Change-Id: I8cde015990d5a3482dbba142cf0a4bbb4512cb02
Signed-off-by: Jeffrey Hugo
---
drivers/gpu/drm/qaic/qaic_trace.h | 493 ++
1 file changed, 493 insertions(+)
create mode 100644
A QAIC device supports the concept of subsystem restart (ssr). If a
processing unit for a workload crashes, it is possible to reset that unit
instead of crashing the device. Since such an error is likely related to
the workload code that was running, it is possible to collect a crashdump
of the
Add the infrastructure that allows the QAIC driver to be built.
Change-Id: I5b609b2e91b6a99939bdac35849813263ad874af
Signed-off-by: Jeffrey Hugo
---
drivers/gpu/drm/Kconfig | 2 ++
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/qaic/Kconfig | 33 +
A QAIC device contains a MHI interface with a number of different channels
for controlling different aspects of the device. The MHI controller works
with the MHI bus to enable and drive that interface.
Change-Id: I77363193b1a2dece7abab287a6acef3cac1b4e1b
Signed-off-by: Jeffrey Hugo
---
Add the QAIC driver uapi file and core driver file that binds to the PCIe
device. The core driver file also creates the drm device and manages all
the interconnections between the different parts of the driver.
Change-Id: I28854e8a5dacda217439be2f65a4ab67d4dccd1e
Signed-off-by: Jeffrey Hugo
---
The QAIC driver can advertise the state of individual dma_bridge channels
to userspace. Userspace can use this information to manage userspace
state when a channel crashes.
Change-Id: Ifc7435c53cec6aa326bdcd9bfcb77ea7f2a63bab
Signed-off-by: Jeffrey Hugo
---
drivers/gpu/drm/qaic/qaic_sysfs.c |
Add documentation covering both the QAIC driver, and the device that it
drives.
Change-Id: Iee519cc0a276249c4e8684507d27ae2c33e29aeb
Signed-off-by: Jeffrey Hugo
---
Documentation/gpu/drivers.rst | 1 +
Documentation/gpu/qaic.rst| 567 ++
2 files
[AMD Official Use Only - General]
This patch is
Reviewed-by: Ruijing Dong
Thanks,
Ruijing
-Original Message-
From: Khalid Masum
Sent: Monday, August 15, 2022 2:34 PM
To: Dong, Ruijing ; amd-...@lists.freedesktop.org;
dri-devel@lists.freedesktop.org; linux-ker...@vger.kernel.org
Cc:
There is no point in returning an int here. It only returns 0 which
the caller never uses. Therefore return void and remove the unnecessary
assignment.
Addresses-Coverity: 1504988 ("Unused value")
Fixes: 8da1170a16e4 ("drm/amdgpu: add VCN4 ip block support")
Suggested-by: Ruijing Dong
On 8/15/22 22:00, Dong, Ruijing wrote:
[AMD Official Use Only - General]
Then please update commit message, this change is due to "value r is never used, and
remove unnecessary assignment", that makes sense to me.
Thanks
Ruijing
Greg also pointed out that the function vcn_v4_0_stop_dpg_mode
From: Thomas Zimmermann
commit 009a3a52791f31c57d755a73f6bc66fbdd8bd76c upstream.
Fix a number of compile errors by including the correct header
files. Examples are shown below.
../drivers/gpu/drm/hyperv/hyperv_drm_modeset.c: In function
'hyperv_blit_to_vram_rect':
On Mon, 15 Aug 2022, Geert Uytterhoeven wrote:
Below is the list of build error/warning regressions/improvements in
v6.0-rc1[1] compared to v5.19[2].
Summarized:
- build errors: +26/-15
+ /kisskb/src/arch/parisc/kernel/vdso32/restart_syscall.S: Error: .cfi_endproc
without corresponding
Whenever we are not able to get enough timeslots
for required PBN, let's try to allocate those
using DSC, just same way as we do for SST.
v2: Removed intel_dp_mst_dsc_compute_config and refactored
intel_dp_dsc_compute_config to support timeslots as a
parameter(Ville Syrjälä)
v3: -
Currently we have only DSC support for DP SST.
Stanislav Lisovskiy (2):
drm: Add missing DP DSC extended capability definitions.
drm/i915: Add DSC support to MST path
drivers/gpu/drm/i915/display/intel_dp.c | 76 --
drivers/gpu/drm/i915/display/intel_dp.h | 17 +++
Adding DP DSC register definitions, we might need for further
DSC implementation, supporting MST and DP branch pass-through mode.
v2: - Fixed checkpatch comment warning
v3: - Removed function which is not yet used(Jani Nikula)
Signed-off-by: Stanislav Lisovskiy
---
include/drm/display/drm_dp.h
On Sun, Aug 14, 2022 at 04:46:54PM -0700, Vinay Belgaumkar wrote:
> Host Turbo operates at efficient frequency when GT is not idle unless
> the user or workload has forced it to a higher level. Replicate the same
> behavior in SLPC by allowing the algorithm to use efficient frequency.
> We had
This makes the code look cleaner and easier to read.
Signed-off-by: Beniamin Sandu
---
drivers/gpu/drm/nouveau/nouveau_hwmon.c | 85 +
1 file changed, 17 insertions(+), 68 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_hwmon.c
Quoting Kuogee Hsieh (2022-08-11 08:20:01)
>
> On 8/10/2022 6:00 PM, Abhinav Kumar wrote:
> >
> > Even then, you do have a valid point. DRM framework should not have
> > caused the disable path to happen without an enable.
> >
> > I went through the stack mentioned in the issue.
> >
> > Lets see
This patch adds the initial DRM driver for Imagination Technologies PowerVR
GPUs, starting with those based on our Rogue architecture. It's worth pointing
out that this is a new driver, written from the ground up, rather than a
refactored version of our existing downstream driver (pvrsrvkm).
This
On 8/15/22 22:12, Greg KH wrote:
On Mon, Aug 15, 2022 at 09:11:18PM +0600, Khalid Masum wrote:
On 8/15/22 20:15, Dong, Ruijing wrote:
[AMD Official Use Only - General]
Sorry, which "r" value was overwritten? I didn't see the point of making this
change.
Thanks
Ruijing
-Original
On 8/15/2022 9:51 AM, Rodrigo Vivi wrote:
On Tue, Aug 09, 2022 at 05:03:06PM -0700, Vinay Belgaumkar wrote:
Host Turbo operates at efficient frequency when GT is not idle unless
the user or workload has forced it to a higher level. Replicate the same
behavior in SLPC by allowing the algorithm
On 8/15/22 07:12, Maxime Ripard wrote:
On Wed, Aug 10, 2022 at 10:33:48PM +0200, Stefan Wahren wrote:
Hi Florian,
Am 09.08.22 um 21:02 schrieb Florian Fainelli:
On 8/4/22 16:11, Florian Fainelli wrote:
On 6/13/22 07:47, Maxime Ripard wrote:
From: Dave Stevenson
The BCM2835-37 found in the
On Tue, Aug 09, 2022 at 05:03:06PM -0700, Vinay Belgaumkar wrote:
> Host Turbo operates at efficient frequency when GT is not idle unless
> the user or workload has forced it to a higher level. Replicate the same
> behavior in SLPC by allowing the algorithm to use efficient frequency.
> We had
On Mon, Aug 15, 2022 at 09:11:18PM +0600, Khalid Masum wrote:
> On 8/15/22 20:15, Dong, Ruijing wrote:
> > [AMD Official Use Only - General]
> >
> > Sorry, which "r" value was overwritten? I didn't see the point of making
> > this change.
> >
> > Thanks
> > Ruijing
> >
> > -Original
[AMD Official Use Only - General]
Then please update commit message, this change is due to "value r is never
used, and remove unnecessary assignment", that makes sense to me.
Thanks
Ruijing
-Original Message-
From: Khalid Masum
Sent: Monday, August 15, 2022 11:54 AM
To: Dong, Ruijing
On Fri, Aug 05, 2022 at 06:35:01PM +, Michael Kelley (LINUX) wrote:
> From: Christophe JAILLET Sent: Sunday, July
> 31, 2022 1:02 PM
> >
> > hyperv_setup_vram() calls vmbus_allocate_mmio().
> > This must be undone in the error handling path of the probe, as already
> > done in the remove
On Mon, Aug 15, 2022 at 04:44:44PM +0100, Mark Brown wrote:
> On Fri, 12 Aug 2022 13:08:17 +0300, Matti Vaittinen wrote:
> > Devm helpers for regulator get and enable
> >
> > First patch in the series is actually just a simple documentation fix
> > which could be taken in as it is now.
> >
> > A
On 8/15/22 17:57, Dmitry Osipenko wrote:
> On 8/15/22 16:53, Christian König wrote:
>> Am 15.08.22 um 15:45 schrieb Dmitry Osipenko:
>>> [SNIP]
Well that comment sounds like KVM is doing the right thing, so I'm
wondering what exactly is going on here.
>>> KVM actually doesn't hold the
On 8/15/22 21:17, Dong, Ruijing wrote:
[AMD Official Use Only - General]
If the condition was met and it came to execute vcn_4_0_stop_dpg_mode, then it
would never have a chance to go for /*wait for vcn idle*/, isn't it?
Hypothetically, some other thread might set adev->pg_flags NULL and in
On Wed, 10 Aug 2022 16:13:11 +0300, Krzysztof Kozlowski wrote:
> The spi-3wire property is device specific and should be accepted only if
> device really needs them. Drop it from common spi-peripheral-props.yaml
> schema, mention in few panel drivers which use it and include instead in
> the SPI
On Fri, 12 Aug 2022 13:08:17 +0300, Matti Vaittinen wrote:
> Devm helpers for regulator get and enable
>
> First patch in the series is actually just a simple documentation fix
> which could be taken in as it is now.
>
> A few* drivers seem to use pattern demonstrated by pseudocode:
>
> [...]
Following the clock rate range improvements to the clock framework,
trying to set a disjoint range on a clock will now result in an error.
Thus, we can't set a minimum rate higher than the maximum reported by
the firmware, or clk_set_min_rate() will fail.
Thus we need to clamp the rate we are
In order to support higher HDMI frequencies, users have to set the
hdmi_enable_4kp60 parameter in their config.txt file.
This will have the side-effect of raising the maximum of the core clock,
tied to the HVS, and managed by the HVS driver.
However, we are querying this in the HDMI driver by
From: Dom Cobley
At least the 4096x2160@60Hz mode requires some overclocking that isn't
available by default, even if hdmi_enable_4kp60 is enabled.
Let's add some logic to detect whether we can satisfy the core clock
requirements for that mode, and prevent it from being used otherwise.
In order to support higher HDMI frequencies, users have to set the
hdmi_enable_4kp60 parameter in their config.txt file.
We were detecting this so far by calling clk_round_rate() on the core
clock with the frequency we're supposed to run at when one of those
modes is enabled. Whether or not the
The RaspberryPi firmware can be configured by the end user using the
config.txt file.
Some of these options will affect the kernel capabilities, and we thus
need to be able to detect it to operate reliably.
One of such parameters is the hdmi_enable_4kp60 parameter that will
setup the clocks in a
The RaspberryPi firmware can be configured by the end user using the
config.txt file.
Some of these options will affect the kernel capabilities, and we thus
need to be able to detect it to operate reliably.
One of such parameters is the core_clock parameter that allows users to
setup the clocks
The RaspberryPi firmware clocks driver uses in several instances a
container_of to retrieve the struct raspberrypi_clk_data from a pointer
to struct clk_hw. Let's create a small function to avoid duplicating it
all over the place.
Signed-off-by: Maxime Ripard
diff --git
drivers/gpu/drm/vc4/vc4_hvs.c| 13 ++
drivers/gpu/drm/vc4/vc4_kms.c| 17 +---
include/soc/bcm2835/raspberrypi-clocks.h | 21 +
7 files changed, 138 insertions(+), 33 deletions(-)
---
base-commit: 568035b01cfb107af8d2e4bd2fb9aea22cf5b868
change-id: 20220815
[AMD Official Use Only - General]
If the condition was met and it came to execute vcn_4_0_stop_dpg_mode, then it
would never have a chance to go for /*wait for vcn idle*/, isn't it?
I still didn't see obvious purpose of this change.
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
On 8/15/22 20:15, Dong, Ruijing wrote:
[AMD Official Use Only - General]
Sorry, which "r" value was overwritten? I didn't see the point of making this
change.
Thanks
Ruijing
-Original Message-
From: Khalid Masum
Sent: Monday, August 15, 2022 3:01 AM
To:
On 8/15/22 16:53, Christian König wrote:
> Am 15.08.22 um 15:45 schrieb Dmitry Osipenko:
>> [SNIP]
>>> Well that comment sounds like KVM is doing the right thing, so I'm
>>> wondering what exactly is going on here.
>> KVM actually doesn't hold the page reference, it takes the temporal
>> reference
On 08/15, Maíra Canal wrote:
> If amdgpu_cs_vm_handling returns r != 0, then it will unlock the
> bo_list_mutex inside the function amdgpu_cs_vm_handling and again on
> amdgpu_cs_parser_fini. This problem results in the following
> use-after-free problem:
>
> [ 220.280990] [ cut here
[AMD Official Use Only - General]
Sorry, which "r" value was overwritten? I didn't see the point of making this
change.
Thanks
Ruijing
-Original Message-
From: Khalid Masum
Sent: Monday, August 15, 2022 3:01 AM
To: amd-...@lists.freedesktop.org; dri-devel@lists.freedesktop.org;
https://bugzilla.kernel.org/show_bug.cgi?id=216143
--- Comment #11 from Erhard F. (erhar...@mailbox.org) ---
Created attachment 301574
--> https://bugzilla.kernel.org/attachment.cgi?id=301574=edit
kernel .config (kernel 6.0-rc1, AMD Ryzen 9 5950X)
--
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https://bugzilla.kernel.org/show_bug.cgi?id=216143
--- Comment #10 from Erhard F. (erhar...@mailbox.org) ---
Created attachment 301573
--> https://bugzilla.kernel.org/attachment.cgi?id=301573=edit
kernel dmesg (kernel 6.0-rc1, AMD Ryzen 9 5950X)
No change with v6-0-rc1.
[...]
Am 15.08.22 um 15:45 schrieb Dmitry Osipenko:
[SNIP]
Well that comment sounds like KVM is doing the right thing, so I'm
wondering what exactly is going on here.
KVM actually doesn't hold the page reference, it takes the temporal
reference during page fault and then drops the reference once
On 8/15/22 16:06, Christian König wrote:
> Am 15.08.22 um 13:50 schrieb Dmitry Osipenko:
>> On 8/15/22 14:28, Christian König wrote:
>> Maybe it was discussed privately? In this case I will be happy to get
>> more info from you about the root of the problem so I could start to
>> look
The hsync/vsync polarities were not honoured for the eDP and HDMI ports.
Add the register settings to configure the polarities as requested by the
DRM_MODE_FLAG_PHSYNC/DRM_MODE_FLAG_PVSYNC flags.
Signed-off-by: Sascha Hauer
---
drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 4
1 file
Am 15.08.22 um 09:34 schrieb 李真能:
在 2022/8/12 18:55, Christian König 写道:
Am 11.08.22 um 09:25 schrieb Zhenneng Li:
Although radeon card fence and wait for gpu to finish processing
current batch rings,
there is still a corner case that radeon lockup work queue may not
be fully flushed,
and
TTM owns the pages it uses for backing buffer objects with system
memory. Because of this it is absolutely illegal to mess around with
the reference count of those pages.
So make sure that nobody ever tries to grab an extra reference on
pages allocated through the page pool.
Signed-off-by:
Am 15.08.22 um 13:50 schrieb Dmitry Osipenko:
On 8/15/22 14:28, Christian König wrote:
Maybe it was discussed privately? In this case I will be happy to get
more info from you about the root of the problem so I could start to
look at how to fix it properly. It's not apparent where the problem
Am 15.08.22 um 13:39 schrieb Maíra Canal:
If amdgpu_cs_vm_handling returns r != 0, then it will unlock the
bo_list_mutex inside the function amdgpu_cs_vm_handling and again on
amdgpu_cs_parser_fini. This problem results in the following
use-after-free problem:
[ 220.280990] [ cut
Hi ChiaEn,
On 8/15/22 12:01, ChiaEn Wu wrote:
From: ChiaEn Wu
Add linear_range_idx macro for declaring the linear_range struct simply.
Signed-off-by: ChiaEn Wu
---
include/linux/linear_range.h | 8
1 file changed, 8 insertions(+)
diff --git a/include/linux/linear_range.h
On 8/15/22 14:28, Christian König wrote:
Maybe it was discussed privately? In this case I will be happy to get
more info from you about the root of the problem so I could start to
look at how to fix it properly. It's not apparent where the problem is
to a TTM newbie like me.
If amdgpu_cs_vm_handling returns r != 0, then it will unlock the
bo_list_mutex inside the function amdgpu_cs_vm_handling and again on
amdgpu_cs_parser_fini. This problem results in the following
use-after-free problem:
[ 220.280990] [ cut here ]
[ 220.281000] refcount_t:
Am 15.08.22 um 13:19 schrieb Dmitry Osipenko:
[SNIP]
I'll try to dig out the older discussions, thank you for the quick
reply!
Are you sure it was really discussed in public previously? All I can
find is yours two answers to a similar patches where you're saying that
this it's a wrong solution
On 8/15/22 13:51, Christian König wrote:
> Am 15.08.22 um 12:47 schrieb Dmitry Osipenko:
>> On 8/15/22 13:18, Dmitry Osipenko wrote:
>>> On 8/15/22 13:14, Christian König wrote:
Am 15.08.22 um 12:11 schrieb Christian König:
> Am 15.08.22 um 12:09 schrieb Dmitry Osipenko:
>> On 8/15/22
Am 12.08.22 um 15:30 schrieb Arunpravin Paneer Selvam:
We are adding two new callbacks to ttm resource manager
function to handle intersection and compatibility of
placement and resources.
v2: move the amdgpu and ttm_range_manager changes to
separate patches (Christian)
v3: rename
Am 15.08.22 um 12:55 schrieb Melissa Wen:
On 08/14, Maíra Canal wrote:
Hi Mikhail
Looks like this use-after-free problem was introduced on
90af0ca047f3049c4b46e902f432ad6ef1e2ded6. Checking this patch it seems
like: if amdgpu_cs_vm_handling return r != 0, then it will unlock
bo_list_mutex
On 08/14, Maíra Canal wrote:
> Hi Mikhail
>
> Looks like this use-after-free problem was introduced on
> 90af0ca047f3049c4b46e902f432ad6ef1e2ded6. Checking this patch it seems
> like: if amdgpu_cs_vm_handling return r != 0, then it will unlock
> bo_list_mutex inside the function
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