If construction of the array of work queues to handle hpd_rx_irq offload
work fails, we need to unwind. Destroy all the created workqueues and
the allocated memory for the hpd_rx_irq_offload_work_queue struct array.
Fixes: 8e794421bc98 ("drm/amd/display: Fork thread to offload work of
Hi, there is a divide error bug in framebuffer_check in
drivers/gpu/drm/drm_framebuffer.c in the latest kernel.
we can trigger it via drm_mode_addfb2 IOCTL.
The call trace is drm_mode_addfb2 -> drm_internal_framebuffer_create
-> framebuffer_check.
let us see code below:
```
static int
The variable ret is being initialized with a value that is never
read, it is being updated later on. The assignment is redundant and
can be removed.
Signed-off-by: Jingyu Wang
---
drivers/gpu/drm/drm_writeback.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: allen chen
Add properties to restrict dp output data-lanes and clock.
Signed-off-by: Pin-Yen Lin
Signed-off-by: Allen Chen
---
.../devicetree/bindings/display/bridge/ite,it6505.yaml | 10 ++
1 file changed, 10 insertions(+)
diff --git
Hi all,
Today's linux-next merge of the drm-intel tree got a conflict in:
drivers/gpu/drm/i915/i915_drv.h
between commit:
3bb6a44251b4 ("drm/i915: Rename ggtt_view as gtt_view")
from the drm tree and commit:
5fd5cc73e449 ("drm/i915: split out i915_gem.c declarations to i915_gem.h")
Hi Johan,
I love your patch! Yet something to improve:
[auto build test ERROR on next-20220912]
[also build test ERROR on v6.0-rc5]
[cannot apply to drm-misc/drm-misc-next drm/drm-next drm-intel/for-linux-next
drm-tip/drm-tip linus/master v6.0-rc5 v6.0-rc4 v6.0-rc3]
[If your patch is applied
From: John Harrison
A patch was merged to remove the GuC log size override module
parameters. That patch was broken and caused kernel error messages on
boot in non CONFIG_DEBUG_GUC|GEM builds:
[ 12.085121] i915 :00:02.0: [drm] *ERROR* Zero GuC log crash dump size!
[ 12.092035] i915
From: John Harrison
The patch 'remove log size module parameters' broke loading the kernel
when not compiling for debug. Fix it.
Signed-off-by: John Harrison
John Harrison (1):
drm/i915/guc: Fix release build bug in 'remove log size module
parameters'
Wait on the fence to be signalled to avoid the submissions finding HuC
not yet loaded.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Tony Ye
Reviewed-by: Alan Previn
Acked-by: Tony Ye
---
drivers/gpu/drm/i915/gt/uc/intel_huc.h | 6 ++
drivers/gpu/drm/i915/i915_request.c| 24
From: Tomas Winkler
Add support for loading HuC via a pxp stream command.
V4:
1. Remove unnecessary include in intel_pxp_huc.h (Jani)
2. Adjust copyright year to 2022
Signed-off-by: Tomas Winkler
Signed-off-by: Vitaly Lubart
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
From: Tomas Winkler
With on-boards graphics card, both i915 and MEI
are in the same device hierarchy with the same parent,
while for discrete gfx card the MEI is its child device.
Adjust the match function for that scenario
by matching MEI parent device with i915.
Signed-off-by: Tomas Winkler
From: Vitaly Lubart
Command to be sent via the stream interface are written to a local
memory page, whose address is then provided to the GSC.
The interface supports providing a full sg with multiple pages for both
input and output messages, but since for now we only aim to support short
and
The fw name is different and we need to record the fact that the blob is
gsc-loaded, so add a new macro to help.
Note: A-step DG2 G10 does not support HuC loading via GSC and would
require a separate firmware to be loaded the legacy way, but that's
not a production stepping so we're not going to
The current HuC status getparam return values are a bit confusing in
regards to what happens in some scenarios. In particular, most of the
error cases cause the ioctl to return an error, but a couple of them,
INIT_FAIL and LOAD_FAIL, are not explicitly handled and neither is
their expected return
The GSC will perform both the load and the authentication, so we just
need to check the auth bit after the GSC has replied.
Since we require the PXP module to load the HuC, the earliest we can
trigger the load is during the pxp_bind operation.
Note that GSC-loaded HuC survives GT reset, so we
Both are required for HuC loading.
Signed-off-by: Daniele Ceraolo Spurio
---
drivers/gpu/drm/i915/Kconfig.debug | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/Kconfig.debug
b/drivers/gpu/drm/i915/Kconfig.debug
index e7fd3e76f8a2..a6576ffbc4dc 100644
---
Given that HuC load is delayed on DG2, this patch adds support for a fence
that can be used to wait for load completion. No waiters are added in this
patch (they're coming up in the next one), to keep the focus of the
patch on the tracking logic.
The full HuC loading flow on boot DG2 is as
From: Vitaly Lubart
The discrete graphics card with GSC firmware
using command streamer API hence it requires to enhance
pxp module with the new gsc_command() handler.
The handler is implemented via mei_pxp_gsc_command() which is
just a thin wrapper around mei_cldev_send_gsc_command()
From: Vitaly Lubart
Add mei bus API for sending gsc commands: mei_cldev_send_gsc_command()
The GSC commands are originated in the graphics stack
and are in form of SGL DMA buffers.
The GSC commands are synchronous, the response is received
in the same call on the out sg list buffers.
The
The mei_pxp module is required to send the command to load authenticate
the HuC to the GSC even if pxp is not in use for protected content
management.
Signed-off-by: Daniele Ceraolo Spurio
Cc: Alan Previn
Reviewed-by: Alan Previn
---
drivers/gpu/drm/i915/Makefile| 10 +++---
From: Tomas Winkler
GSC command is and extended header containing a scatter gather
list and without a data buffer. Using MEI_CL_IO_SGL flag,
the caller send the GSC command as a data and the function internally
moves it to the extended header.
Signed-off-by: Tomas Winkler
Signed-off-by:
From: Tomas Winkler
Fix kdoc for struct mei_ext_hdr and mei_ext_begin().
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Greg Kroah-Hartman
---
V4: New in the series
V5: Rebase
drivers/misc/mei/hw.h | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff
From: Tomas Winkler
GSC extend header is of variable size and data
is provided in a sgl list inside the header
and not in the data buffers, need to enable the path.
Signed-off-by: Tomas Winkler
Signed-off-by: Daniele Ceraolo Spurio
Cc: Vitaly Lubart
Cc: Greg Kroah-Hartman
---
V2-3: Rebase
On DG2, HuC loading is performed by the GSC, via a PXP command. The load
operation itself is relatively simple (just send a message to the GSC
with the physical address of the HuC in LMEM), but there are timing
changes that requires special attention. In particular, to send a PXP
command we need
From: John Harrison
The earlier update to support reduced versioning of firmware files
introduced an issue with the firmware override module parameter. If an
invalid file was specified then an infinite loop could occur trying to
find a backup firmware.
The fix is that if an explicit override
From: John Harrison
The earlier patch to support firmware files with reduced versioning
introduced an issue with the firmware override module parameter. So
fix that.
Signed-off-by: John Harrison
John Harrison (1):
drm/i915/uc: Fix issues with overriding firmware files
On 9/12/2022 00:12, Joonas Lahtinen wrote:
Quoting Joonas Lahtinen (2022-08-26 09:23:08)
Quoting John Harrison (2022-08-25 19:31:39)
On 8/25/2022 00:15, Joonas Lahtinen wrote:
Quoting John Harrison (2022-08-24 21:45:09)
We also don't want to tie the GuC logging buffer size to the DRM
Hi Fabien
Thanks for the patch.
I believe this issue should get resolved with
https://patchwork.freedesktop.org/patch/490326/ as this avoids the override.
I have acked that change and will pick it up for the next fixes.
Thanks
Abhinav
On 9/9/2022 8:28 AM, Fabien Parent wrote:
The kernel
Hi, Allen:
Allen-KH Cheng 於 2022年9月8日 週四 晚上10:12寫道：
>
> The width and height arguments in the cmdq packet for mtk_dither_config()
> are inverted. We fix the incorrect width and height for dither settings
> in mtk_dither_config().
Applied to mediatek-drm-fixes [1], thanks.
[1]
Have we checked that this actually fixes the Mesa build? If so, R-b.
> Commit 730c2bf4ad39 ("drm/panfrost: Add support for devcoredump")
> introduces one such union, breaking the Mesa build.
>
> Give it a name, and also rename pan_reg_hdr structure because it will
> always be prefixed by the
tree/branch:
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git master
branch HEAD: 044b771be9c5de9d817dfafb829d2f049c71c3b4 Add linux-next specific
files for 20220912
Error/Warning reports:
https://lore.kernel.org/linux-media/202209020437.exeodmfe-...@intel.com
https
On Mon, Sep 12, 2022 at 2:17 PM Jason Baron wrote:
>
>
>
> On 9/9/22 16:44, jim.cro...@gmail.com wrote:
> > On Wed, Sep 7, 2022 at 12:19 PM Jason Baron wrote:
> >>
> >>
> >>
> >> On 9/4/22 17:40, Jim Cromie wrote:
> >>> Add module-to-class validation:
> >>>
> >>> #> echo class DRM_UT_KMS +p >
Hi Rodrigo,
On Mon, Sep 12, 2022 at 05:50:31PM -0400, Rodrigo Siqueira Jordao wrote:
>
>
> On 2022-08-30 16:34, Nathan Chancellor wrote:
> > Hi all,
> >
> > This series aims to address the following warnings, which are visible
> > when building x86_64 allmodconfig with clang after commit
> From: Saurabh Sengar
> Sent: Monday, September 12, 2022 8:33 AM
> ...
> Existing code is causing a race condition where dirt_needed value is
> already set by the host and gets overwritten with default value. Remove
> this default setting of dirt_needed, to avoid overwriting the value
>
On 9/12/22 1:10 PM, Dmitry Baryshkov wrote:
On 12/09/2022 18:40, Johan Hovold wrote:
Device-managed resources allocated post component bind must be tied to
the lifetime of the aggregate DRM device or they will not necessarily be
released when binding of the aggregate device is deferred.
This
On 2022-08-30 16:34, Nathan Chancellor wrote:
Hi all,
This series aims to address the following warnings, which are visible
when building x86_64 allmodconfig with clang after commit 3876a8b5e241
("drm/amd/display: Enable building new display engine with KCOV
enabled").
On Thu, Sep 08, 2022 at 08:42:35PM -0500, Rob Herring wrote:
> On Wed, Sep 07, 2022 at 08:35:13AM -0500, Chris Morgan wrote:
> > On Wed, Sep 07, 2022 at 02:53:56PM +0200, Krzysztof Kozlowski wrote:
> > > On 06/09/2022 20:52, Chris Morgan wrote:
> > > > From: Chris Morgan
> > > >
> > > > Add
On Mon, Sep 12, 2022 at 01:38:54PM +0200, Robert Foss wrote:
> After applying the "chrontel-ch7033: Add byteswap order option" series,
> Laurent reported an issues with the approach. Since no fix has been submitted
> for the issues outlined in time for the next kernel release, I'd like to
> revert
On Mon, Sep 12, 2022 at 10:12:57PM +0200, Andi Shyti wrote:
Hi Lucas,
On Mon, Sep 12, 2022 at 11:12:47AM -0700, Lucas De Marchi wrote:
On Mon, Sep 12, 2022 at 06:59:53PM +0200, Andi Shyti wrote:
> Hi Lucas,
>
> On Mon, Sep 12, 2022 at 09:19:38AM -0700, Lucas De Marchi wrote:
> > Support for
On Mon, Sep 12, 2022 at 4:29 AM Jani Nikula wrote:
>
> On Sun, 11 Sep 2022, Jim Cromie wrote:
> > Use DECLARE_DYNDBG_CLASSMAP across DRM:
> >
> > - in .c files, since macro defines/initializes a record
> >
> > - in drivers, $mod_{drv,drm,param}.c
> >ie where param setup is done, since a
On Wed, 07 Sep 2022 11:38:43 +0300, Mikko Perttunen wrote:
> From: Mikko Perttunen
>
> Add defines for stream IDs used for Host1x context isolation
> on Tegra234. The same stream IDs are used for both NISO0 and
> NISO1 SMMUs since Host1x's stream ID protection tables don't
> make a distinction
On 9/9/22 16:44, jim.cro...@gmail.com wrote:
> On Wed, Sep 7, 2022 at 12:19 PM Jason Baron wrote:
>>
>>
>>
>> On 9/4/22 17:40, Jim Cromie wrote:
>>> Add module-to-class validation:
>>>
>>> #> echo class DRM_UT_KMS +p > /proc/dynamic_debug/control
>>>
>>> If a query has "class FOO", then
Hi Lucas,
On Mon, Sep 12, 2022 at 11:12:47AM -0700, Lucas De Marchi wrote:
> On Mon, Sep 12, 2022 at 06:59:53PM +0200, Andi Shyti wrote:
> > Hi Lucas,
> >
> > On Mon, Sep 12, 2022 at 09:19:38AM -0700, Lucas De Marchi wrote:
> > > Support for reading the fuses to check what are the Link Copy
Hi Liviu,
Thanks for having a look!
This is not about this patch, it's about patch 3/7 "drm/arm/hdlcd: crtc:
use drmm_crtc_init_with_planes()".
And there it's the other way around. When using
drmm_crtc_init_with_planes() we shouldn't have a destroy hook in place,
that's the whole purpose
On 9/12/2022 11:37 AM, Dmitry Baryshkov wrote:
On 12/09/2022 19:23, Kuogee Hsieh wrote:
Bring sink out of D3 (power down) mode into D0 (normal operation) mode
by setting DP_SET_POWER_D0 bit to DP_SET_POWER dpcd register. This
patch will retry 3 times if written to DP_SET_POWER register
On 12/09/2022 22:21, Kuogee Hsieh wrote:
On 9/12/2022 11:39 AM, Dmitry Baryshkov wrote:
On 12/09/2022 19:23, Kuogee Hsieh wrote:
DOWNSPREAD_CTRL (0x107) shall be cleared to 0 upon power-on reset or an
upstream device disconnect. This patch will enforce this rule by always
cleared
On 9/12/2022 11:39 AM, Dmitry Baryshkov wrote:
On 12/09/2022 19:23, Kuogee Hsieh wrote:
DOWNSPREAD_CTRL (0x107) shall be cleared to 0 upon power-on reset or an
upstream device disconnect. This patch will enforce this rule by always
cleared DOWNSPREAD_CTRL register to 0 before start link
Hi Dave,
On Thu, 8 Sept 2022 at 20:33, Dave Stevenson
wrote:
>
> Hi Jagan
>
> On Thu, 8 Sept 2022 at 15:00, Jagan Teki wrote:
> >
> > Jadard JD9365DA-H3 is WUXGA MIPI DSI panel and it support TFT
> > dot matrix LCD with 800RGBx1280 dots at maximum.
Look like I wrapped the wrong text, maybe
On 12.09.2022 18:19, Lucas De Marchi wrote:
Support for reading the fuses to check what are the Link Copy engines
was added in commit ad5f74f34201 ("drm/i915/pvc: read fuses for link
copy engines"). However they were added unconditionally because the
FUSE3 register is present since graphics
On Thu, Aug 25, 2022 at 11:06 AM Brian Norris wrote:
> On Thu, Aug 25, 2022 at 10:37 AM Doug Anderson wrote:
> > Given that this is _not_ an area that I'm an expert in nor is it an
> > area where the consequences are super easy to analyze, I'm a little
> > hesitant to apply this to drm-misc-next
On 12/09/2022 19:23, Kuogee Hsieh wrote:
DOWNSPREAD_CTRL (0x107) shall be cleared to 0 upon power-on reset or an
upstream device disconnect. This patch will enforce this rule by always
cleared DOWNSPREAD_CTRL register to 0 before start link training. At rare
case that DP MSA timing parameters
On 12/09/2022 19:23, Kuogee Hsieh wrote:
Bring sink out of D3 (power down) mode into D0 (normal operation) mode
by setting DP_SET_POWER_D0 bit to DP_SET_POWER dpcd register. This
patch will retry 3 times if written to DP_SET_POWER register failed.
Could you please elaborate this change? Can
On 12/09/2022 19:23, Kuogee Hsieh wrote:
drm_dp_dpcd_readb() will return 1 to indicate one byte had been read
successfully. This patch replace variable "err" with "len" have more
correct meaning.
changes in v5:
-- split into 3 patches
Signed-off-by: Kuogee Hsieh
Reviewed-by: Dmitry
On 01/09/2022 23:34, Jessica Zhang wrote:
Add support for HDR color formats.
XR30 linear/compressed format has been validated with null_platform_test
on SC7180, and P010 linear has been validated with plane_test (also on
SC7180).
Are they supported on sdm845? On msm8998?
Jessica Zhang (2):
On Thu, Sep 1, 2022 at 1:34 PM Jessica Zhang wrote:
>
> Add support for P010 color format. This adds support for both linear and
> compressed formats.
>
> Signed-off-by: Jessica Zhang
Reviewed-by: Rob Clark
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c| 17 -
>
On Thu, Sep 1, 2022 at 1:34 PM Jessica Zhang wrote:
>
> Add support for XR30 color format. This supports both linear and
> compressed formats.
>
> Signed-off-by: Jessica Zhang
Reviewed-by: Rob Clark
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_formats.c| 7 +++
>
On Mon, Sep 12, 2022 at 06:59:53PM +0200, Andi Shyti wrote:
Hi Lucas,
On Mon, Sep 12, 2022 at 09:19:38AM -0700, Lucas De Marchi wrote:
Support for reading the fuses to check what are the Link Copy engines
was added in commit ad5f74f34201 ("drm/i915/pvc: read fuses for link
copy engines").
On 12/09/2022 18:40, Johan Hovold wrote:
Device-managed resources allocated post component bind must be tied to
the lifetime of the aggregate DRM device or they will not necessarily be
released when binding of the aggregate device is deferred.
This can lead resource leaks or failure to bind the
On 12/09/2022 18:40, Johan Hovold wrote:
Device-managed resources allocated post component bind must be tied to
the lifetime of the aggregate DRM device or they will not necessarily be
released when binding of the aggregate device is deferred.
This can lead resource leaks or failure to bind the
On 12/09/2022 18:40, Johan Hovold wrote:
Device-managed resources allocated post component bind must be tied to
the lifetime of the aggregate DRM device or they will not necessarily be
released when binding of the aggregate device is deferred.
This is specifically true for the DP IRQ, which
On 12/09/2022 18:40, Johan Hovold wrote:
Drop the overly defensive modeset sanity checks of function parameters
which have already been checked or used by the callers.
Signed-off-by: Johan Hovold
Again, please split into dp and dsi patches. After that:
Reviewed-by: Dmitry Baryshkov
---
On 12/09/2022 20:34, Kuogee Hsieh wrote:
DRM commit_tails() will disable downstream crtc/encoder/bridge if
both disable crtc is required and crtc->active is set before pushing
a new frame downstream.
There is a rare case that user space display manager issue an extra
screen update immediately
From: Chris Morgan
If I use more than one VP to output on an RK3566 based device I
receive the following error (and then everything freezes):
[0.838375] Unable to handle kernel NULL pointer dereference at virtual
address 0250
[0.839191] Mem abort info:
[0.839442] ESR
On 12/09/2022 18:40, Johan Hovold wrote:
Device-managed resources allocated post component bind must be tied to
the lifetime of the aggregate DRM device or they will not necessarily be
released when binding of the aggregate device is deferred.
This is specifically true for the HDMI IRQ, which
On 12/09/2022 18:40, Johan Hovold wrote:
Add the missing sanity checks on the bridge counter to avoid corrupting
data beyond the fixed-sized bridge array in case there are ever more
than eight bridges.
a3376e3ec81c ("drm/msm: convert to drm_bridge")
ab5b0107ccf3 ("drm/msm: Initial add eDP
On 12/09/2022 18:40, Johan Hovold wrote:
The bridge counter was never reset when tearing down the DRM device so
that stale pointers to deallocated structures would be accessed on the
next tear down (e.g. after a second late bind deferral).
Given enough bridges and a few probe deferrals this
Hi Danilo,
I have applied your patch series for HDLCD on top of drm-next (commit
213cb76ddc8b)
and on start up I get a warning:
[ 12.882554] hdlcd 7ff5.hdlcd: drm_WARN_ON(funcs && funcs->destroy)
[ 12.882596] WARNING: CPU: 1 PID: 211 at drivers/gpu/drm/drm_crtc.c:393
DRM commit_tails() will disable downstream crtc/encoder/bridge if
both disable crtc is required and crtc->active is set before pushing
a new frame downstream.
There is a rare case that user space display manager issue an extra
screen update immediately followed by close DRM device while down
On Mon, Sep 12, 2022 at 06:47:56PM +0200, Mauro Carvalho Chehab wrote:
> Hi Matt,
>
> Em Mon, 12 Sep 2022 08:09:57 -0700
> Matt Roper escreveu:
>
> > > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > > +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
> >
> > Several of the
On Mon, Sep 12, 2022 at 04:22:49PM +0200, Thomas Zimmermann wrote:
> Hi
>
> Am 12.09.22 um 14:34 schrieb Ville Syrjälä:
> > On Mon, Sep 12, 2022 at 02:05:36PM +0200, Thomas Zimmermann wrote:
> >> Hi
> >>
> >> Am 12.09.22 um 13:18 schrieb Ville Syrjälä:
> >>> On Mon, Sep 12, 2022 at 01:05:45PM
Adding kuogee to this series
Hi Johan
Thanks for posting this.
We will take a look at this, re-validate and give our reviews/tested-bys.
Thanks
Abhinav
On 9/12/2022 8:40 AM, Johan Hovold wrote:
The MSM DRM is currently broken in multiple ways with respect to probe
deferral. Not only does
On 9/9/2022 10:16 AM, Kuogee Hsieh wrote:
DRM commit_tails() will disable downstream crtc/encoder/bridge if
both disable crtc is required and crtc->active is set before pushing
a new frame downstream.
There is a rare case that user space display manager issue an extra
screen update
https://bugzilla.kernel.org/show_bug.cgi?id=213145
nvaert1986 (nvaert1...@hotmail.com) changed:
What|Removed |Added
CC|
Hi Lucas,
On Mon, Sep 12, 2022 at 09:19:38AM -0700, Lucas De Marchi wrote:
> Support for reading the fuses to check what are the Link Copy engines
> was added in commit ad5f74f34201 ("drm/i915/pvc: read fuses for link
> copy engines"). However they were added unconditionally because the
> FUSE3
On Mon, Sep 12, 2022 at 02:48:54PM +0200, Thomas Hellström wrote:
> On Mon, 2022-09-12 at 15:43 +0300, Ville Syrjälä wrote:
> > On Mon, Sep 12, 2022 at 02:19:57PM +0200, Thomas Hellström wrote:
> > > Commit 39a2bd34c933 ("drm/i915: Use the vma resource as argument
> > > for gtt
> > > binding /
Hi Matt,
Em Mon, 12 Sep 2022 08:09:57 -0700
Matt Roper escreveu:
> > --- a/drivers/gpu/drm/i915/gt/intel_context_types.h
> > +++ b/drivers/gpu/drm/i915/gt/intel_context_types.h
>
> Several of the comments in this file do appear to be kerneldoc (in fact
> kerneldoc that was specifically
Building Mesa's Perfetto requires including the panfrost drm uAPI header in
C++ code, but the C++ compiler requires anonymous unions to have only
public non-static data members.
Commit 730c2bf4ad39 ("drm/panfrost: Add support for devcoredump")
introduces one such union, breaking the Mesa build.
cleared DP_DOWNSPREAD_CTRL register before start link training
Kuogee Hsieh (3):
drm/msm/dp: cleared DP_DOWNSPREAD_CTRL register before start link
training
drm/msm/dp: replace variable err with len at dp_aux_link_power_up()
drm/msm/dp: retry 3 times if set sink to D0 poweer state failed
Bring sink out of D3 (power down) mode into D0 (normal operation) mode
by setting DP_SET_POWER_D0 bit to DP_SET_POWER dpcd register. This
patch will retry 3 times if written to DP_SET_POWER register failed.
Changes in v5:
-- split into two patches
Signed-off-by: Kuogee Hsieh
---
Hi,
Sorry for late reply.
How do you propose to go then?
Can we still use a persistent platform device to load the firmware and
cache it? But, in this case the system will still crash in case the
user change drm.edid_firmware then, without replugging the device, he
suspends and resumes the
drm_dp_dpcd_readb() will return 1 to indicate one byte had been read
successfully. This patch replace variable "err" with "len" have more
correct meaning.
changes in v5:
-- split into 3 patches
Signed-off-by: Kuogee Hsieh
---
drivers/gpu/drm/msm/dp/dp_link.c | 14 +++---
1 file
DOWNSPREAD_CTRL (0x107) shall be cleared to 0 upon power-on reset or an
upstream device disconnect. This patch will enforce this rule by always
cleared DOWNSPREAD_CTRL register to 0 before start link training. At rare
case that DP MSA timing parameters may be mis-interpreted by the sink
which
Support for reading the fuses to check what are the Link Copy engines
was added in commit ad5f74f34201 ("drm/i915/pvc: read fuses for link
copy engines"). However they were added unconditionally because the
FUSE3 register is present since graphics version 10.
However the bitfield with meml3 fuses
: 088771790e5d121c70c358468abbebb4710eb02f
change-id: 20220912-copy-engine-526db816b088
Best regards,
--
Lucas De Marchi
On Fri, Sep 09, 2022 at 04:18:14PM -0700, Lucas De Marchi wrote:
Update fuse handling for media to future-proof it.
Signed-off-by: Lucas De Marchi
Thanks Matt Roper and Andrzej for the review. Applied.
Lucas De Marchi
Explain how to run the KUnit tests present in the AMDGPU's Display
Core and clarify which architectures and tools can be used to run
the tests. Moreover, explains how to add new tests to the existing
tests.
Signed-off-by: Maíra Canal
---
.../gpu/amdgpu/display/display-test.rst | 88
Add unit test to the SubVP feature in order to avoid possible
regressions and assure the code robustness.
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/amd/display/Kconfig | 13 +
drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 4 +
.../gpu/drm/amd/display/tests/.kunitconfig|
The display_mode_vba_20 deals with hundreds of display parameters for
the DCN20 and sometimes does it in odd ways. The addition of unit tests
intends to assure the quality of the code delivered by HW engineers and,
also make it possible to refactor the code decreasing concerns about adding
bugs to
From: Magali Lemes
This commit adds unit tests to the functions dcn20_cap_soc_clocks and
dcn21_update_bw_bounding_box from dcn20/dcn20_fpu.
Signed-off-by: Magali Lemes
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/amd/display/tests/Makefile| 3 +-
The display_mode_vba library deals with hundreds of display parameters
and sometimes does it in odd ways. The addition of unit tests intends to
assure the quality of the code delivered by HW engineers and, also make
it possible to refactor the code decreasing concerns about adding bugs
to the
From: Isabella Basso
This adds tests to the bit encoding format verification functions on the
file. They're meant to be simpler so as to provide a proof of concept on
testing DML code.
Signed-off-by: Isabella Basso
Signed-off-by: Maíra Canal
---
drivers/gpu/drm/amd/display/Kconfig
KUnit unifies the test structure and provides helper tools that simplify
the development of tests. Basic use case allows running tests as regular
processes, which makes easier to run unit tests on a development machine
and to integrate the tests in a CI system.
This commit introduces a unit test
From: Tales Aparecida
The fixed31_32 library performs a lot of the mathematical operations
involving fixed-point arithmetic and the conversion of integers to
fixed-point representation.
This unit tests intend to assure the proper functioning of the basic
mathematical operations of fixed-point
Hello,
This series is version 3 of the introduction of unit testing to the
AMDPGU driver [1].
Our main goal is to bring unit testing to the AMD display driver; in
particular, we'll focus on the Display Mode Library (DML) for DCN2.0,
DMUB, and some of the DCE functions. This implementation
Device-managed resources allocated post component bind must be tied to
the lifetime of the aggregate DRM device or they will not necessarily be
released when binding of the aggregate device is deferred.
This is specifically true for the DP IRQ, which will otherwise remain
requested so that the
Drop the overly defensive modeset sanity checks of function parameters
which have already been checked or used by the callers.
Signed-off-by: Johan Hovold
---
drivers/gpu/drm/msm/dp/dp_display.c | 7 +--
drivers/gpu/drm/msm/dsi/dsi.c | 7 +--
2 files changed, 2 insertions(+), 12
Add the missing sanity checks on the bridge counter to avoid corrupting
data beyond the fixed-sized bridge array in case there are ever more
than eight bridges.
a3376e3ec81c ("drm/msm: convert to drm_bridge")
ab5b0107ccf3 ("drm/msm: Initial add eDP support in msm drm driver (v5)")
a689554ba6ed
The bridge counter was never reset when tearing down the DRM device so
that stale pointers to deallocated structures would be accessed on the
next tear down (e.g. after a second late bind deferral).
Given enough bridges and a few probe deferrals this could currently also
lead to data beyond the
Device-managed resources allocated post component bind must be tied to
the lifetime of the aggregate DRM device or they will not necessarily be
released when binding of the aggregate device is deferred.
This can lead resource leaks or failure to bind the aggregate device
when binding is later
Device-managed resources allocated post component bind must be tied to
the lifetime of the aggregate DRM device or they will not necessarily be
released when binding of the aggregate device is deferred.
This is specifically true for the HDMI IRQ, which will otherwise remain
requested so that the
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