On Mon, Aug 17, 2020 at 09:10:46PM +0530, Akhil P Oommen wrote:
> On 8/14/2020 8:11 AM, Rob Clark wrote:
> >From: Jordan Crouse
> >
> >Add support for using per-instance pagetables if all the dependencies are
> >available.
> >
> >Signed-off-by: Jor
esn't manage to
> overwrite the seqno before we look at it.
>
> This can show up with hang recovery if one of the submits after the
> crashing submit also hangs after it is replayed.
Reviewed-by: Jordan Crouse
> Fixes: f97decac5f4c ("drm/msm: Support multiple
On Thu, Aug 13, 2020 at 07:49:24AM +0100, Chris Wilson wrote:
> Quoting Jordan Crouse (2020-08-13 00:55:44)
> > This is an RFC because I'm still trying to grok the correct behavior.
> >
> > Consider a dma_fence_array created two two fence and signal_on_any i
uite sure the intent of
clearing it only after getting to the irq worker.
Signed-off-by: Jordan Crouse
---
drivers/dma-buf/dma-fence-array.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/dma-buf/dma-fence-array.c
b/drivers/dma-buf/dma-fence-array.c
index d3f
efault.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 3 ++-
> drivers/gpu/drm/msm/adreno/adreno_device.c | 4
> drivers/gpu/drm/msm/adreno/adreno_gpu.h | 2 ++
> 3 files changed, 8 insertions(+), 1 deletio
a/-/merge_requests/6242
Reviewed-by: Jordan Crouse
> Fixes: 1707add81551 ("drm/msm/a6xx: Add a6xx gpu state")
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/dr
Add support for using per-instance pagetables if all the dependencies are
available.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 70 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
3 files
Add support for allocating private address space instances. Targets that
support per-context pagetables should implement their own function to
allocate private address spaces.
The default will return a pointer to the global address space.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm
Add support to create a io-pgtable for use by targets that support
per-instance pagetables. In order to support per-instance pagetables the
GPU SMMU device needs to have the qcom,adreno-smmu compatible string and
split pagetables enabled.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm
/pipermail/iommu/2020-June/045653.html
[2] https://lists.linuxfoundation.org/pipermail/iommu/2020-June/045659.html
Jordan Crouse (13):
iommu/arm-smmu: Pass io-pgtable config to implementation specific
function
iommu/arm-smmu: Add support for split pagetables
iommu/arm-smmu: Prepare for the
function to
function.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 ++---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 ++---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +--
drivers/gpu/drm/msm/msm_drv.c
Use the aperture settings from the IOMMU domain to set up the virtual
address range for the GPU. This allows us to transparently deal with
IOMMU side features (like split pagetables).
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++--
drivers/gpu/drm
Add support for using per-instance pagetables if all the dependencies are
available.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 53 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
3 files
Add support to create a io-pgtable for use by targets that support
per-instance pagetables. In order to support per-instance pagetables the
GPU SMMU device needs to have the qcom,adreno-smmu compatible string and
split pagetables enabled.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm
function to
function.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 ++---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 ++---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +--
drivers/gpu/drm/msm/msm_drv.c
Add support for allocating private address space instances. Targets that
support per-context pagetables should implement their own function to
allocate private address spaces.
The default will return a pointer to the global address space.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm
://lists.linuxfoundation.org/pipermail/iommu/2020-June/045653.html
[2] https://lists.linuxfoundation.org/pipermail/iommu/2020-June/045659.html
Jordan Crouse (12):
iommu/arm-smmu: Pass io-pgtable config to implementation specific
function
iommu/arm-smmu: Add support for split pagetables
iommu/arm-smmu
Use the aperture settings from the IOMMU domain to set up the virtual
address range for the GPU. This allows us to transparently deal with
IOMMU side features (like split pagetables).
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++--
drivers/gpu/drm
Add support for using per-instance pagetables if all the dependencies are
available.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 53 +++
drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 1 +
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
3 files
://lists.linuxfoundation.org/pipermail/iommu/2020-June/045659.html
Jordan Crouse (13):
iommu/arm-smmu: Pass io-pgtable config to implementation specific
function
iommu/arm-smmu: Add support for split pagetables
iommu/arm-smmu: Add implementation hooks to configure contexts
iommu/arm-smmu-qcom: Add
Add support for allocating private address space instances. Targets that
support per-context pagetables should implement their own function to
allocate private address spaces.
The default will return a pointer to the global address space.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm
Use the aperture settings from the IOMMU domain to set up the virtual
address range for the GPU. This allows us to transparently deal with
IOMMU side features (like split pagetables).
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++--
drivers/gpu/drm
function to
function.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 12 +---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 5 ++---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 5 ++---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 3 +--
drivers/gpu/drm/msm/msm_drv.c
Add support to create a io-pgtable for use by targets that support
per-instance pagetables. In order to support per-instance pagetables the
GPU SMMU device needs to have the qcom,adreno-smmu compatible string and
split pagetables enabled.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm
at for you.
Reviewed-by: Jordan Crouse
> ---
> Changes from v1:
> - Reworded the commit text
> - Added Reported-by & Tested-by tags
>
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 18 ++
> 1 file changed, 10 insertions(+), 8 deletions(-)
>
> diff --git a
>
> - gpu->ocmem_icc_path = of_icc_get(dev, "ocmem");
> if (IS_ERR(gpu->ocmem_icc_path)) {
> ret = PTR_ERR(gpu->ocmem_icc_path);
> gpu->ocmem_icc_path = NULL;
> @@ -1026,6 +1027,7 @@ int adreno_gpu_init(struct drm_device
On Tue, Jul 14, 2020 at 06:55:30PM +0530, Akhil P Oommen wrote:
> On targets where GMU is available, GMU takes over the ownership of GX GDSC
> during its initialization. So, take a refcount on the GX PD on behalf of
> GMU before we initialize it. This makes sure that nobody can collapse the
> GX GD
or 3xx and 4xx where you could be a bit more demanding that the
ocmem path actually exist.
Reviewed-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 65 +++--
> 1 file changed, 38 insertions(+), 27 deletions(-)
>
On Mon, Jul 13, 2020 at 06:53:41PM -0400, Jonathan Marek wrote:
> These never get set back to 0 when probing fails, so an attempt to probe
> again results in broken behavior. Fix the problem by setting thse to zero
> before they are used.
Reviewed-by: Jordan Crouse
> Signed-off-
On Mon, Jul 13, 2020 at 06:53:40PM -0400, Jonathan Marek wrote:
> adreno_gpu_init calls pm_runtime_enable, so adreno_gpu_cleanup needs to
> call pm_runtime_disable.
Reviewed-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c |
On Mon, Jul 13, 2020 at 06:24:26PM +0300, Georgi Djakov wrote:
> On 7/1/20 07:25, Jonathan Marek wrote:
> > The a6xx GMU can vote for ddr and cnoc bandwidth, but it needs to be able
> > to query the interconnect driver for bcm addresses and commands.
>
> It's not very clear to me how the GMU firmw
On Tue, Jul 07, 2020 at 01:35:00PM -0700, Rob Clark wrote:
> From: Rob Clark
Might need a commit log here, but otherwise makes sense.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 5 +++--
> drivers/gpu/drm/msm/adreno/
ly the bw table should be filled by querying the interconnect
> driver for each BW in the dts, but use these dummy tables for now.
Reviewed-by: Jordan Crouse
And yes, I agree that we need to move this into the generic API sooner rather
than later, but this should be good enough to get a working
On Mon, Jun 29, 2020 at 08:10:06PM -0400, Jonathan Marek wrote:
> A650 has a separate RSCC region, so dump RSCC registers separately, reading
> them from the RSCC base. Without this change a GPU hang will cause a system
> reset if CONFIG_DEV_COREDUMP is enabled.
Reviewed-by: Jord
On Fri, Jul 03, 2020 at 09:04:49AM -0700, Rob Clark wrote:
> On Fri, Jul 3, 2020 at 7:53 AM Sai Prakash Ranjan
> wrote:
> >
> > Hi Will,
> >
> > On 2020-07-03 19:07, Will Deacon wrote:
> > > On Mon, Jun 29, 2020 at 09:22:50PM +0530, Sai Prakash Ranjan wrote:
> > >> diff --git a/drivers/gpu/drm/msm
On Tue, Jul 07, 2020 at 12:36:42PM +0100, Robin Murphy wrote:
> On 2020-06-26 21:04, Jordan Crouse wrote:
> >Add support to create a io-pgtable for use by targets that support
> >per-instance pagetables. In order to support per-instance pagetables the
> >GPU SMMU device n
On Wed, Jul 01, 2020 at 12:25:25AM -0400, Jonathan Marek wrote:
> The a6xx GMU can vote for ddr and cnoc bandwidth, but it needs to be able
> to query the interconnect driver for bcm addresses and commands.
>
> I'm not sure what is the best way to go about implementing this, this is
> what I came
On Sat, Jun 27, 2020 at 01:11:14PM -0700, Rob Clark wrote:
> On Sat, Jun 27, 2020 at 12:56 PM Rob Clark wrote:
> >
> > On Fri, Jun 26, 2020 at 1:04 PM Jordan Crouse
> > wrote:
> > >
> > > Add support for using per-instance pagetables if a
On Sat, Jun 27, 2020 at 10:10:14AM -0700, Rob Clark wrote:
> On Fri, Jun 26, 2020 at 1:01 PM Jordan Crouse wrote:
> >
> > Use the aperture settings from the IOMMU domain to set up the virtual
> > address range for the GPU. This allows us to transparently deal with
> >
Add support for using per-instance pagetables if all the dependencies are
available.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 43 +++
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
2 files changed, 44 insertions(+)
diff --git a/drivers
Add support for allocating an address space instance. Targets that support
per-instance pagetables should implement their own function to allocate a
new instance. The default will return the existing generic address space.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 15
://patchwork.kernel.org/patch/11628543/
v2: Remove unneeded cruft in the a6xx page switch sequence
Jordan Crouse (6):
iommu/arm-smmu: Add auxiliary domain support for arm-smmuv2
iommu/io-pgtable: Allow a pgtable implementation to skip TLB
operations
iommu/arm-smmu: Add a domain attribute to pass the
-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_gpummu.c | 2 +-
drivers/gpu/drm/msm/msm_iommu.c | 180 ++-
drivers/gpu/drm/msm/msm_mmu.h| 16 ++-
3 files changed, 195 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gpummu.c b/drivers/gpu/drm
Use the aperture settings from the IOMMU domain to set up the virtual
address range for the GPU. This allows us to transparently deal with
IOMMU side features (like split pagetables).
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++--
drivers/gpu/drm
82591/
Jordan Crouse (7):
iommu/arm-smmu: Pass io-pgtable config to implementation specific
function
iommu/arm-smmu: Add support for split pagetables
dt-bindings: arm-smmu: Add compatible string for Adreno GPU SMMU
iommu/arm-smmu: Add a pointer to the attached device to smmu_domain
iommu/arm
space initialization")
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c| 2 +-
drivers/gpu/drm/msm/adreno/a6xx_gmu.c| 2 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +-
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 2 +-
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c
On Wed, Jun 17, 2020 at 07:39:08PM -0700, Rob Clark wrote:
> On Wed, Jun 17, 2020 at 1:53 PM Eric Anholt wrote:
> >
> > Previously the address space went from 16M to ~0u, but with the
> > refactor one of the 'f's was dropped, limiting us to 256MB.
> > Additionally, the new interface takes a start
On Thu, Jun 11, 2020 at 08:22:29PM -0700, Rob Clark wrote:
> On Thu, Jun 11, 2020 at 3:29 PM Jordan Crouse wrote:
> >
> > Add support for using per-instance pagetables if all the dependencies are
> > available.
> >
> > Signed-off-by: Jordan Crouse
> >
-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_gpummu.c | 2 +-
drivers/gpu/drm/msm/msm_iommu.c | 180 ++-
drivers/gpu/drm/msm/msm_mmu.h| 16 ++-
3 files changed, 195 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/msm_gpummu.c b/drivers/gpu/drm
://patchwork.kernel.org/patch/11600949/
Jordan Crouse (6):
iommu/arm-smmu: Add auxiliary domain support for arm-smmuv2
iommu/io-pgtable: Allow a pgtable implementation to skip TLB
operations
iommu/arm-smmu: Add a domain attribute to pass the pagetable config
drm/msm: Add support to create a local
Add support for using per-instance pagetables if all the dependencies are
available.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 69 ++-
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
2 files changed, 69 insertions(+), 1 deletion(-)
diff
Add support for allocating an address space instance. Targets that support
per-instance pagetables should implement their own function to allocate a
new instance. The default will return the existing generic address space.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 15
g the hardware would be less confusing when debugging a hang.
v8: Pass the attached device in the smmu_domain to the implementation
specific functions
[1] https://lists.linuxfoundation.org/pipermail/iommu/2020-May/044537.html
[2] https://patchwork.kernel.org/patch/11482591/
Jordan Crouse (7):
iomm
Use the aperture settings from the IOMMU domain to set up the virtual
address range for the GPU. This allows us to transparently deal with
IOMMU side features (like split pagetables).
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++--
drivers/gpu/drm
Use the aperture settings from the IOMMU domain to set up the virtual
address range for the GPU. This allows us to transparently deal with
IOMMU side features (like split pagetables).
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++--
drivers/gpu/drm
dware would be less confusing when debugging a hang.
[1] https://lists.linuxfoundation.org/pipermail/iommu/2020-May/044537.html
[2] https://patchwork.kernel.org/patch/11482591/
Jordan Crouse (6):
iommu/arm-smmu: Pass io-pgtable config to implementation specific
function
iommu/arm-smmu
On Wed, May 27, 2020 at 08:38:47AM -0700, Rob Clark wrote:
> On Wed, May 27, 2020 at 1:47 AM Sharat Masetty
> wrote:
> >
> > + more folks
> >
> > On 5/18/2020 9:55 PM, Rob Clark wrote:
> > > On Mon, May 18, 2020 at 7:23 AM Jordan Crouse
> > >
sp_ncmode = FIELD_PREP(REG_A6XX_TPL1_NC_MODE_HBB, 3);
sp_ncmode |= FIELD_PREP(REG_A6XX_TPL1_NC_MODE_UAVFLAGPRD_INV, 2);
uchemode = FIELD_PREP(REG_A6XX_UCHE_MODE_CNTL_HBB, 2);
}
I'm not sure if that is any clearer or not. Perhaps this is a problem for the
next person to add a new target. Regardle
s as a -fix if it didn't.
Reviewed-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> b/
On Mon, May 18, 2020 at 11:07:33PM -0400, Jonathan Marek wrote:
> This fixes changing the frequency in sysfs while suspended, for example
> when doing something like this:
>
> cat devfreq/3d0.gpu/max_freq > devfreq/3d0.gpu/min_freq
A patch landed to fix this [1] but it crossed paths in th
://patchwork.kernel.org/patch/11355255/
[2] https://patchwork.kernel.org/patch/11355259/
Jordan Crouse (3):
drm/msm: Attach the IOMMU device during initialization
drm/msm: Refactor address space initialization
drm/msm: Update the MMU helper function APIs
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
functions to create the address space so a2xx can do its own thing in its
own space. For all the other targets use a generic helper to initialize
IOMMU but leave the door open for newer targets to use customization
if they need it.
Reviewed-by: Rob Clark
Signed-off-by: Jordan Crouse
---
drivers/gpu
aggressive cleanups that follow.
Reviewed-by: Rob Clark
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 4
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 ---
drivers/gpu/drm/msm/msm_gem_vma.c
Instead of using a bare unsigned type for the length value for map/unmap
functions pass in a size_t to more correctly match up with the underlying
APIs.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_gpummu.c | 4 ++--
drivers/gpu/drm/msm/msm_iommu.c | 4 ++--
drivers/gpu/drm/msm
t; RSCC_TCS2_DRV0_STATUS
> RSCC_TCS3_DRV0_STATUS
>
> Based on the values in msm-4.14 and msm-4.19 kernels.
>
> v3: replaced adreno_is_a650 around ->rscc with checks for "rscc" resource
This is one of the most frustrating bits about the different GMU flavors. There
is simply no
On Thu, Apr 23, 2020 at 05:09:21PM -0400, Jonathan Marek wrote:
> Adreno 640 and 650 GPUs need some registers set differently.
As before, make sure you send the XML updates up so the database stays current.
Reviewed-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> dri
but don't forget to do that
so we don't accidentally lose the registers if we do a refresh.
Reviewed-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 138 +++---
> drivers/gpu/drm/msm/adreno/a6xx_gm
On Thu, Apr 23, 2020 at 05:09:13PM -0400, Jonathan Marek wrote:
> This function allows pinning iova to a specific page range (for a6xx GMU).
Reviewed-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/msm_drv.h | 6 +-
> drivers/gpu/dr
x27;s why it gets changed to adreno_is_a4xx(), while a420 is not
> tested though.
This looks good to me and if it boots then that's the best test of all.
Reviewed-by: Jordan Crouse
> Signed-off-by: Shawn Guo
> ---
> drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 29 +-
5() works only after adreno_gpu_init() gets called, the
> assignments get moved down after adreno_gpu_init().
Reviewed-by: Jordan Crouse
> Signed-off-by: Shawn Guo
> ---
> drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 53 +--
> 1 file changed, 50 insertions(+), 3 deletions(-
On Thu, May 14, 2020 at 04:24:18PM +0530, Sharat Masetty wrote:
> This patches replaces the previously used static DDR vote and uses
> dev_pm_opp_set_bw() to scale GPU->DDR bandwidth along with scaling
> GPU frequency.
>
> Signed-off-by: Sharat Masetty
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu
g
Reviewed-by: Eric Anholt
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 6 ++
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +++
3 files changed, 21 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
the GPU driver.
Call pm_runtime_get_if_in_use() in the gpu_busy() and gpu_set_freq()
callbacks to skip the hardware access if it isn't active.
v2: Use pm_runtime_get_if_in_use() per Eric Anholt
Cc: sta...@vger.kernel.org
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a
the GPU driver.
Check the power state in the gpu_busy() and gpu_set_freq() callbacks for
a5xx and a6xx to make sure that the hardware is active before trying to
access it.
Cc: sta...@vger.kernel.org
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4
drivers/gpu
On Thu, Apr 30, 2020 at 09:29:47AM +0530, Sharat Masetty wrote:
> This patch adds a new compatible string for sc7180 and also an
> additional clock listing needed to power the TBUs and the TCU.
>
> Signed-off-by: Sharat Masetty
> ---
> v2: Addressed review comments from Doug
>
> Documentation/d
On Tue, Apr 21, 2020 at 07:41:23PM -0400, Jonathan Marek wrote:
> Add HFI v2 code paths required by Adreno 640 and 650 GPUs.
I still feel like there is a chance for optimization here but the perfect is the
enemy of the good and that would be a good follow on for the future.
Reviewed-by: Jor
On Tue, Apr 21, 2020 at 07:41:26PM -0400, Jonathan Marek wrote:
> This is required for a650 to work.
Reviewed-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 15 +++
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h |
On Tue, Apr 21, 2020 at 07:41:24PM -0400, Jonathan Marek wrote:
> Newer GPUs have different GMU firmware path.
>
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 135 +++---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 11 ++
> drivers/gpu/drm
On Tue, Apr 21, 2020 at 07:41:25PM -0400, Jonathan Marek wrote:
> Update the gmu_pdc registers for A640 and A650.
>
> Some of the RSCC registers on A650 are in a separate region.
>
> Note this also changes the address of these registers:
>
> RSCC_TCS1_DRV0_STATUS
> RSCC_TCS2_DRV0_STATUS
> RSCC_T
On Tue, Apr 21, 2020 at 07:41:22PM -0400, Jonathan Marek wrote:
> Add Adreno 640 and 650 GPU info to the gpulist.
>
Reviewed-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 24 ++
> drivers/
On Tue, Apr 21, 2020 at 07:41:21PM -0400, Jonathan Marek wrote:
> This gives more fine-grained control over how memory is allocated over the
> DMA api. In particular, it allows using an address range or pinning to
> a fixed address.
Reviewed-by: Jordan Crouse
> Signed-off-by: Jo
e
global buffers as privileged so people can't go out and overwrite the memstore
any more.
Reviewed-by: Jordan Crouse
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/msm_gem.c | 3 +++
> drivers/gpu/drm/msm/msm_gem.h | 1 +
> 2 files changed, 4 insertions(+)
>
>
On Mon, Apr 20, 2020 at 10:03:13AM -0400, Jonathan Marek wrote:
> Adreno 640 and 650 GPUs need some registers set differently.
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/a6xx.xml.h | 14 +++
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56 ++-
> 2
On Mon, Apr 20, 2020 at 10:03:12AM -0400, Jonathan Marek wrote:
> This is required for a650 to work.
>
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 16
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 1 +
> drivers/gpu/drm/msm/adreno/a6xx_gm
On Mon, Apr 20, 2020 at 10:03:11AM -0400, Jonathan Marek wrote:
> Signed-off-by: Jonathan Marek
I was wondering where this was. I don't think there is any reason to not squash
this into the previous patch since the GMU won't be operational without it.
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gm
On Mon, Apr 20, 2020 at 10:03:08AM -0400, Jonathan Marek wrote:
> Signed-off-by: Jonathan Marek
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 68 ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 7 ++
> drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +-
> drivers/gpu/drm/msm/adreno/a6x
functions to create the address space so a2xx can do its own thing in its
own space. For all the other targets use a generic helper to initialize
IOMMU but leave the door open for newer targets to use customization
if they need it.
Reviewed-by: Rob Clark
Signed-off-by: Jordan Crouse
---
drivers/gpu
will be
enabled later when an auxiliary domain is attached
v3: Remove the implementation specific and make split pagetable support
part of the generic configuration
[1] https://lists.linuxfoundation.org/pipermail/iommu/2020-January/041373.html
Jordan Crouse (5):
iommu: Add
start swapping TTBR0 for context-specific pagetables.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 52 ++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno
aggressive cleanups that follow.
Reviewed-by: Rob Clark
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 4
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 ---
drivers/gpu/drm/msm/msm_gem_vma.c
On Tue, Mar 31, 2020 at 01:25:51PM +0530, Sharat Masetty wrote:
> This patch adds support to parse the OPP tables attached the GPU device,
> the main opp table and the DDR bandwidth opp table. Additionally, vote
> for the GPU->DDR bandwidth when setting the GPU frequency by querying
> the linked DD
stack and CC
stable?
Reviewed-by: Jordan Crouse
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 489d9b6..81b8559 1
DMA region is not
set up.
[1] https://patchwork.freedesktop.org/patch/356869/?series=74446&rev=1
Jordan Crouse (2):
dt-bindings: display: msm: Convert GMU bindings to YAML
drm/msm/a6xx: Use the DMA API for GMU memory objects
.../devicetree/bindings/display/msm/gmu.txt | 65 -
.
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
text bindings. The 'sram' text from the old binding never applied to
the GMU so it was not converted but all the other properties were correct.
Acked-by: Sam Ravnborg
Reviewed-by: Rob Herring
Signed-off-by: Jor
correctly and use dma_addr_t for the iova type
v2: Pass force_dma false to of_dma_configure to require that the DMA
region be set up and return error from of_dma_configure to fail probe.
Reviewed-by: Michael J. Ruhl
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 115
force_dma false to of_dma_configure to require that the DMA
region be set up and return error from of_dma_configure to fail probe.
Reviewed-by: Michael J. Ruhl
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 113 --
drivers/gpu/drm/msm
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
text bindings.
Acked-by: Sam Ravnborg
Reviewed-by: Rob Herring
Signed-off-by: Jordan Crouse
---
.../devicetree/bindings/display/msm/gmu.txt| 65 ---
.../devicetree/bindings/display/msm/gmu.yaml
in the GMU device. Convert the iova type to a dma_attr_t to
make it 32 bit friendly.
v2: Fix the example bindings for dma-ranges - the third item is the size
Pass false to of_dma_configure so that it fails probe if the DMA region is not
set up.
[1] https://patchwork.freedesktop.org/patch/3568
property
> description to mention that this property is only valid for a3xx and
> a4xx GPUs. The a3xx/a4xx example in the GPU is replaced with what was
> in the GMU.
Thank you kindly! I'll re-submit my stack on top of this.
Acked-by: Jordan Crouse
> Signed-off-by: Brian Masney
&g
On Tue, Mar 03, 2020 at 10:54:05AM -0500, Brian Masney wrote:
> On Tue, Mar 03, 2020 at 08:50:28AM -0700, Jeffrey Hugo wrote:
> > On Tue, Mar 3, 2020 at 8:43 AM Jordan Crouse wrote:
> > >
> > > On Mon, Mar 02, 2020 at 09:49:06PM +0100, Sam Ravnborg wrote:
> > >
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