On Mon, Mar 02, 2020 at 09:49:06PM +0100, Sam Ravnborg wrote:
> Hi Jordan.
>
> On Mon, Mar 02, 2020 at 11:23:43AM -0700, Jordan Crouse wrote:
> > Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
> > text bindings.
> >
>
the example bindings for dma-ranges - the third item is the size
Pass false to of_dma_configure so that it fails probe if the DMA region is not
set up.
Jordan Crouse (2):
dt-bindings: display: msm: Convert GMU bindings to YAML
drm/msm/a6xx: Use the DMA API for GMU memory objects
.../devicetree
force_dma false to of_dma_configure to require that the DMA
region be set up and return error from of_dma_configure to fail probe.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 113 --
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 6 +-
2
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
text bindings.
Signed-off-by: Jordan Crouse
---
.../devicetree/bindings/display/msm/gmu.txt| 116 ---
.../devicetree/bindings/display/msm/gmu.yaml | 123 +
2 files changed
On Mon, Mar 02, 2020 at 06:56:47PM +, Ruhl, Michael J wrote:
> >-Original Message-
> >From: dri-devel On Behalf Of
> >Jordan Crouse
> >Sent: Monday, March 2, 2020 1:24 PM
> >To: linux-arm-...@vger.kernel.org
> >Cc: David Airlie ; freed
for dma-ranges - the third item is the size
Pass false to of_dma_configure so that it fails probe if the DMA region is not
set up.
Jordan Crouse (2):
dt-bindings: display: msm: Convert GMU bindings to YAML
drm/msm/a6xx: Use the DMA API for GMU memory objects
.../devicetree/bindings/display/msm
to of_dma_configure to require that the DMA
region be set up and return error from of_dma_configure to fail probe.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 115 --
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 7 +--
2 files changed, 15
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
text bindings.
Signed-off-by: Jordan Crouse
---
.../devicetree/bindings/display/msm/gmu.txt| 116 ---
.../devicetree/bindings/display/msm/gmu.yaml | 123 +
2 files changed
On Mon, Mar 02, 2020 at 02:17:16PM +0530, Sharat Masetty wrote:
> This patch disables interrupts in the GPU RBBM hang detect fault handler
> before going to recovery.
Okay, but why? What were you seeing? A little bit of extra description would
make it easier to understand this change in the
On Tue, Jan 28, 2020 at 03:00:14PM -0700, Jordan Crouse wrote:
> This is another iteration for the split pagetable support based on the
> suggestions from Robin and Will [1].
>
> Background: In order to support per-context pagetables the GPU needs to enable
> split tables so th
On Thu, Feb 20, 2020 at 10:00:09AM -0800, Rob Clark wrote:
> From: Rob Clark
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drive
from of_dma_configure to fail probe.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 112 +++---
drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 5 +-
2 files changed, 11 insertions(+), 106 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
text bindings.
Signed-off-by: Jordan Crouse
---
.../devicetree/bindings/display/msm/gmu.txt| 116 --
.../devicetree/bindings/display/msm/gmu.yaml | 130 +
2 files changed
be the size.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/display/msm/gmu.yaml | 10 ++
1 file changed, 10 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml
b/Documentation/devicetree/bindings/display/msm/gmu.yaml
index 776ff92
to of_dma_configure so that it fails probe if the DMA region is not
set up.
Jordan Crouse (4):
dt-bindings: display: msm: Convert GMU bindings to YAML
dt-bindings: display: msm: Add required dma-range property
arm64: dts: sdm845: Set the virtual address range for GMU allocations
drm/msm/a6xx: Use
The GMU has very few memory allocations and uses a flat memory space so
there is no good reason to go out of our way to bypass the DMA APIs which
were basically designed for this exact secnario.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 107
Convert display/msm/gmu.txt to display/msm/gmu.yaml and remove the old
text bindings.
Signed-off-by: Jordan Crouse
---
.../devicetree/bindings/display/msm/gmu.txt| 116 --
.../devicetree/bindings/display/msm/gmu.yaml | 130 +
2 files changed
The GMU node now requires a specific dma-range property so that the driver
can use the DMA API to do the few memory allocations required by the GMU.
This sets the IOMMU iova allocadtor to match the 'uncached' part of the
GMU virtual address space.
Signed-off-by: Jordan Crouse
---
Documentation
we've not yet converted the GMU bindings over to
YAML two patches quickly turn into four but at the end of it we have at least
one bindings file converted to YAML and 99 less lines of code to worry about.
Jordan Crouse (4):
dt-bindings: display: msm: Convert GMU bindings to YAML
dt-bindings
cmdstream
> buffers.
>
> v2: add missing 'inline'
I should have checked my inbox before responding to v1.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_gem.h | 10 ++
> drivers/gpu/drm/msm/msm_gpu.c | 28 +
mdstream
> buffers.
One nit, but with that:
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_gem.h | 10 ++
> drivers/gpu/drm/msm/msm_gpu.c | 28 +++-
> drivers/gpu/drm/msm/msm_rd.c | 8 +---
>
ix a small memory leak
and free the buffer allocated by nvmem_cell_read().
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/g
On Thu, Feb 06, 2020 at 05:43:52PM +0100, Bas Nieuwenhuizen wrote:
> Hi,
>
> I'd appreciate if you could take a look at this patch. I believe I
> have accommodated the earlier review comments.
Sorry, it was sitting on my todo list. Looks good.
> Thank you,
> Bas
>
> On Fri, Jan 24, 2020 at
on introduced in v2
> - Reworked to use ERR_PTR/PTR_ERR
> - Simplified failure gotos.
Reviewed-by: Jordan Crouse
> Signed-off-by: Bas Nieuwenhuizen
> ---
> drivers/gpu/drm/msm/msm_drv.c| 6 +-
> drivers/gpu/drm/msm/msm_gem_submit.c | 232 ++-
iate place in the shutdown routine and remove the redundant
idle call.
v2: Remove newly unused variable that was triggering a warning
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 37 +-
drivers/gpu/drm/msm/adreno/a6xx_
Fixup the GMU bus table values for the sc7180 target.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 85 ---
1 file changed, 60 insertions(+), 25 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c
b/drivers/gpu/drm/msm
we didn't need to unhalt the GBIF in this path
since the stop function already takes care of that after executing a flush
but before turning off the headswitch. We should be confident that the
GBIF is open for business when we restart the hardware.
Signed-off-by: Jordan Crouse
---
drivers/g
On Mon, Feb 03, 2020 at 04:40:40PM -0800, Rob Clark wrote:
> On Mon, Feb 3, 2020 at 4:21 PM John Stultz wrote:
> >
> > On Wed, Jan 22, 2020 at 11:19 PM Sharat Masetty
> > wrote:
> > >
> > > This patch adds support for enabling Graphics Bus Interface(GBIF)
> > > used in multiple A6xx series
On Fri, Jan 31, 2020 at 08:08:09AM -0800, Doug Anderson wrote:
> Hi,
>
> On Fri, Jan 31, 2020 at 4:16 AM wrote:
> >
> > >> + reg = <0 0x0506a000 0 0x31000>, <0 0x0b29
> > >> 0 0x1>,
> > >> + <0 0x0b49 0 0x1>;
> > >> +
Targets that support per-instance pagetable switching will have to keep
track of which pagetable belongs to each instance to be able to recover
for preemption.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
[2] https://patchwork.freedesktop.org/series/57441/
Jordan Crouse (6):
iommu: Add DOMAIN_ATTR_PTBASE
arm/smmu: Add auxiliary domain support for arm-smmuv2
drm/msm/adreno: ADd support for IOMMU auxiliary domains
drm/msm: Add support to create target specific address spaces
drm/msm/gpu: Add ttbr0 to the memptrs
Add support for creating a auxiliary domain from the IOMMU device to
implement per-instance pagetables. Also add a helper function to
return the pagetable base address (ttbr) and asid to the caller so
that the GPU target code can set up the pagetable switch.
Signed-off-by: Jordan Crouse
Add support to create a GPU target specific address space for
a context. For those targets that support per-instance
pagetables they will return a new address space set up for
the instance if possible otherwise just use the global
device pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu
Add support for per-instance pagetables for a6xx targets. Add support
to handle split pagetables and create a new instance if the needed
IOMMU support exists and insert the necessary PM4 commands to trigger
a pagetable switch at the beginning of a user command.
Signed-off-by: Jordan Crouse
v3: Remove the implementation specific and make split pagetable support
part of the generic configuration
[1] https://lists.linuxfoundation.org/pipermail/iommu/2020-January/041373.html
Jordan Crouse (5):
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm-smmu: Add support for TTBR1
drm/msm: Attach
functions to create the address space so a2xx can do its own thing in its
own space. For all the other targets use a generic helper to initialize
IOMMU but leave the door open for newer targets to use customization
if they need it.
Reviewed-by: Rob Clark
Signed-off-by: Jordan Crouse
---
drivers/gpu
to start swapping TTBR0 for context-specific pagetables.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 52 ++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno
aggressive cleanups that follow.
Reviewed-by: Rob Clark
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 4
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 ---
drivers/gpu/drm/msm/msm_gem_vma.c
On Mon, Jan 27, 2020 at 02:29:53PM -0800, Doug Anderson wrote:
> Hi,
>
> On Mon, Jan 27, 2020 at 1:30 AM Sharat Masetty
> wrote:
> >
> > This patch adds the required dt nodes and properties
> > to enabled A618 GPU.
> >
> > Signed-off-by: Sharat Masetty
> > ---
> >
On Fri, Jan 24, 2020 at 05:50:11PM +0530, Akhil P Oommen wrote:
> Highest bank bit configuration is different for a618 gpu. Update
> it with the correct configuration which is the reset value incidentally.
>
> Signed-off-by: Akhil P Oommen
> Signed-off-by: Sharat Masetty
> ---
>
iate place in the shutdown routine and remove the redundant
idle call.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 36 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 43 ---
2 files changed, 31 insertions(+), 48
On Thu, Jan 23, 2020 at 12:49:03PM +0530, Sharat Masetty wrote:
> This patch adds Adreno 618 entry and its associated properties
> to the gpulist entries.
>
> Signed-off-by: Sharat Masetty
I'm extremely confused - these have been in linux-next for weeks. Why are you
sending them out again?
On Fri, Jan 17, 2020 at 07:32:27PM +0100, Bas Nieuwenhuizen wrote:
> On Fri, Jan 17, 2020 at 7:17 PM Jordan Crouse wrote:
> >
> > On Fri, Jan 17, 2020 at 12:04:17AM +0100, Bas Nieuwenhuizen wrote:
> > > This
> > >
> > > 1) Enables core DRM syncobj suppor
On Fri, Jan 17, 2020 at 12:04:17AM +0100, Bas Nieuwenhuizen wrote:
> This
>
> 1) Enables core DRM syncobj support.
> 2) Adds options to the submission ioctl to wait/signal syncobjs.
>
> Just like the wait fence fd, this does inline waits. Using the
> scheduler would be nice but I believe it is
On Tue, Jan 14, 2020 at 09:30:00AM -0800, Kristian Kristensen wrote:
> On Tue, Jan 14, 2020 at 9:23 AM Jordan Crouse wrote:
> >
> > On Tue, Jan 14, 2020 at 08:52:43AM -0800, Rob Clark wrote:
> > > On Mon, Jan 13, 2020 at 9:51 AM Jordan Crouse
> > > wrote:
>
On Tue, Jan 14, 2020 at 08:41:05AM -0800, Rob Clark wrote:
> On Tue, Jan 14, 2020 at 7:58 AM Jordan Crouse wrote:
> >
> > On Tue, Jan 14, 2020 at 01:40:11AM +0100, Bas Nieuwenhuizen wrote:
> > > On Tue, Jan 14, 2020 at 12:41 AM Jordan Crouse
> > > wrote:
>
On Tue, Jan 14, 2020 at 08:52:43AM -0800, Rob Clark wrote:
> On Mon, Jan 13, 2020 at 9:51 AM Jordan Crouse wrote:
> >
> > On Mon, Jan 13, 2020 at 10:36:05AM -0500, Brian Ho wrote:
> > > +
> > > + vaddr = base_vaddr + args->offset;
> > > +
> &g
s
Reviewed-by: Jordan Crouse
> Fixes: 6a0dea02c2c4 ("drm/msm: support firmware-name for zap fw (v2)")
> Signed-off-by: Douglas Anderson
> ---
>
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --g
On Tue, Jan 14, 2020 at 01:40:11AM +0100, Bas Nieuwenhuizen wrote:
> On Tue, Jan 14, 2020 at 12:41 AM Jordan Crouse wrote:
> >
> > On Mon, Jan 13, 2020 at 09:25:57PM +0100, Bas Nieuwenhuizen wrote:
> > > This
> > >
> > > 1) Enables core DRM syncobj suppor
On Mon, Jan 13, 2020 at 09:25:57PM +0100, Bas Nieuwenhuizen wrote:
> This
>
> 1) Enables core DRM syncobj support.
> 2) Adds options to the submission ioctl to wait/signal syncobjs.
>
> Just like the wait fence fd, this does inline waits. Using the
> scheduler would be nice but I believe it is
On Mon, Jan 13, 2020 at 10:36:04AM -0500, Brian Ho wrote:
> This wait queue is signaled on all IRQs for a given GPU and will be
> used as part of the new MSM_WAIT_IOVA ioctl so userspace can sleep
> until the value at a given iova reaches a certain condition.
>
> Signed-off-by: Brian Ho
> ---
>
On Mon, Jan 13, 2020 at 10:36:05AM -0500, Brian Ho wrote:
> Implements an ioctl to wait until a value at a given iova is greater
> than or equal to a supplied value.
>
> This will initially be used by turnip (open-source Vulkan driver for
> QC in mesa) for occlusion queries where the userspace
On Sun, Jan 12, 2020 at 11:53:58AM -0800, Rob Clark wrote:
> From: Rob Clark
>
> For newer devices we want to require the path to come from the
> firmware-name property in the zap-shader dt node.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drive
y need a single error msg when we can't load from firmware-name
> specified path, and fix comment [Bjorn A.]
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/adreno_gpu.c | 30 ++---
> 1 file changed, 27 insertion
On Tue, Jan 07, 2020 at 05:38:42PM -0800, Rob Clark wrote:
> From: Rob Clark
>
> Since zap firmware can be device specific, allow for a firmware-name
> property in the zap node to specify which firmware to load, similarly to
> the scheme used for dsp/wifi/etc.
>
> Signed-off-by: Rob Clark
>
On Mon, Dec 16, 2019 at 09:37:50AM -0700, Jordan Crouse wrote:
> Refactor how address space initialization works. Instead of having the
> address space function create the MMU object (and thus require separate but
> equal functions for gpummu and iommu) use a single function and pass
On Tue, Dec 24, 2019 at 08:27:28AM +0530, smase...@codeaurora.org wrote:
> On 2019-12-16 22:07, Jordan Crouse wrote:
> >Attempt to enable split pagetables if the arm-smmu driver supports it.
> >This will move the default address space from the default region to
> >the a
On Fri, Dec 20, 2019 at 03:40:59PM +0530, smase...@codeaurora.org wrote:
> On 2019-12-20 01:28, Jordan Crouse wrote:
> >On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote:
> >>The last level system cache can be partitioned to 32 different slices
> >>
On Thu, Dec 19, 2019 at 12:58:15PM -0700, Jordan Crouse wrote:
> On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote:
> > +
> > + /*
> > +* CNTL1 is used to specify SCID for (CP, TP, VFD, CCU and UBWC
> > +* FLAG cache) GPU blocks. This
On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote:
> The last level system cache can be partitioned to 32 different slices
> of which GPU has two slices preallocated. One slice is used for caching GPU
> buffers and the other slice is used for caching the GPU SMMU pagetables.
> This
On Thu, Dec 19, 2019 at 06:44:45PM +0530, Sharat Masetty wrote:
> Allow different Adreno targets the ability to pass
> specific mmu features to the generic layers. This will
> help conditionally configure certain iommu features for
> certain Adreno targets.
>
> Also Add a few simple support
aggressive cleanups that follow.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 4
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 ---
drivers/gpu/drm/msm/msm_gem_vma.c| 23
to start swapping TTBR0 for context-specific pagetables.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 52 ++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno
to create the address space so a2xx can do its own thing in its
own space. For all the other targets use a generic helper to initialize
IOMMU but leave the door open for newer targets to use customization
if they need it.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
/pipermail/iommu/2019-October/039718.html
[2] https://lists.linuxfoundation.org/pipermail/iommu/2019-October/039719.html
[3] https://lists.linuxfoundation.org/pipermail/iommu/2019-October/039720.html
Jordan Crouse (5):
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm-smmu: Add support for split
On Tue, Dec 03, 2019 at 03:06:11PM +, Sharat Masetty wrote:
> This patch adds support for enabling Graphics Bus Interface(GBIF)
> used in multiple A6xx series chipets. Also makes changes to the
> PDC/RSC sequencing specifically required for A618. This is needed
> for proper interfacing with
On Tue, Dec 03, 2019 at 03:06:15PM +, Sharat Masetty wrote:
> Fix the cx debugbus related register configuration, to collect accurate
> bus data during gpu snapshot. This helps with complete snapshot dump
> and also complete proper GPU recovery.
Reviewed-by: Jordan Crouse
This g
On Tue, Dec 03, 2019 at 03:06:12PM +, Sharat Masetty wrote:
> Add the relevant GBIF registers and the debug bus to the a6xx gpu
> state. This comes in pretty handy when debugging GPU bus related
> issues.
>
> Change-Id: I224fda727012a456ccd28ca14caf9fcce236e629
> Signed-off-by: Sharat Masetty
On Sat, Dec 14, 2019 at 05:31:50PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c:2260:3-4: Unneeded semicolon
Reviewed-by: Jordan Crouse
>
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drive
On Sat, Dec 14, 2019 at 05:31:49PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:741:2-3: Unneeded semicolon
>
Reviewed-by: Jordan Crouse
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drivers/gpu/drm/m
On Sat, Dec 14, 2019 at 05:31:47PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/hdmi/hdmi_connector.c:104:3-4: Unneeded semicolon
Reviewed-by: Jordan Crouse
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drivers/gpu/drm/msm/
On Sat, Dec 14, 2019 at 05:31:48PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c:905:2-3: Unneeded semicolon
>
Reviewed-by: Jordan Crouse
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drivers/gpu/drm/
to start swapping TTBR0 for context-specific pagetables.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 46 ++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno
functions to create the address space so a2xx can do its own thing in its
own space. For all the other targets use a generic helper to initialize
IOMMU but leave the door open for newer targets to use customization
if they need it.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
aggressive cleanups that follow.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 4
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 ---
drivers/gpu/drm/msm/msm_gem_vma.c| 23
/iommu/2019-October/039720.html
Jordan Crouse (8):
dt-bindings: arm-smmu: Add Adreno GPU variant
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm-smmu: Pass io_pgtable_cfg to impl specific init_context
iommu/arm-smmu: Add split pagetables for Adreno IOMMU implementations
drm/msm: Attach
but the GMU sneaks out in the middle of the night
and takes the hardware for a joyride.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++--
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +++
> 2 files changed, 9 insertions(+
On Sun, Nov 17, 2019 at 06:48:23AM -0500, Brian Masney wrote:
> Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core
> and must use the On Chip MEMory (OCMEM) in order to be functional.
> There's a separate interconnect path that needs to be setup to OCMEM.
> Add support for
On Thu, Nov 14, 2019 at 11:18:56AM +0530, Shubhashree Dhar wrote:
> Current code assumes that all the irqs registers offsets can be
> accessed in all the hw revisions; this is not the case for some
> targets that should not access some of the irq registers.
> This change adds the support to
m that overflow, but is easy to avoid by just converting
> the ktime_t into jiffies directly.
This seems good to me. y2038 changes are the best changes.
Reviewed-by: Jordan Crouse
> Signed-off-by: Arnd Bergmann
> ---
> drivers/gpu/drm/msm/msm_drv.h | 3 +--
> 1 file change
On Tue, Nov 12, 2019 at 01:40:22PM -0300, Fabio Estevam wrote:
> Hi Jordan,
>
> On Fri, Nov 1, 2019 at 11:52 AM Jordan Crouse wrote:
>
> > I'm good with this. This really should only be around for
> > compatibility with downstream device tree files which should mean no
("drm/msm/a6xx: Add a6xx gpu state")
Thanks, I was going to suggest this as well.
> Reviewed-by: Rob Clark
Reviewed-by: Jordan Crouse
> > ---
> > drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 24
> > 1 file changed, 12 insertions(+), 1
On Thu, Oct 31, 2019 at 07:03:59PM -0300, Fabio Estevam wrote:
> Hi Rob,
>
> On Tue, Oct 15, 2019 at 11:19 AM Jeffrey Hugo
> wrote:
> >
> > On Tue, Oct 15, 2019 at 7:40 AM Fabio Estevam wrote:
> > >
> > > Booting the adreno driver on a imx53 board leads to the following
> > > error message:
>
On Mon, Oct 28, 2019 at 08:47:58AM -0600, Jordan Crouse wrote:
> On Wed, Oct 23, 2019 at 11:00:58AM -0700, Yiwei Zhang wrote:
> > Hi folks,
> >
> > This is Yiwei from the Android Platform Graphics team. On the downstream
> > Android, vendors used to report GPU
On Wed, Oct 23, 2019 at 11:00:58AM -0700, Yiwei Zhang wrote:
> Hi folks,
>
> This is Yiwei from the Android Platform Graphics team. On the downstream
> Android, vendors used to report GPU private memory allocations with debugfs
> nodes in their own formats. However, debugfs nodes are getting
warning: symbol
> 'a5xx_gpu_state_put' was not declared. Should it be static?
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c:1302:6: warning: symbol 'a5xx_show' was
> not declared. Should it be static?
Reviewed-by: Jordan Crouse
> Signed-off-by: Ben Dooks
> ---
> Cc: Rob Clark
> Cc: Sean Paul
>
On Sat, Sep 21, 2019 at 12:04:39PM +0200, khol...@gmail.com wrote:
> From: "Angelo G. Del Regno"
>
> The Adreno 510 GPU is a stripped version of the Adreno 5xx,
> found in low-end SoCs like 8x56 and 8x76, which has 256K of
> GMEM, with no GPMU nor ZAP.
> Also, since the Adreno 5xx part of this
ion-declaration]
>
> Fixes: 482f96324a4e ("drm/msm: Fix task dump in gpu recovery")
Reviewed-by: Jordan Crouse
> Signed-off-by: Arnd Bergmann
> ---
> drivers/gpu/drm/msm/msm_gpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/msm/
On Mon, Sep 16, 2019 at 01:34:55PM -0700, Rob Clark wrote:
> On Mon, Sep 16, 2019 at 1:12 PM Drew Davenport
> wrote:
> >
> > The arguments related to IOMMU port name have been unused since
> > commit 944fc36c31ed ("drm/msm: use upstream iommu") and can be removed.
> >
> > Signed-off-by: Drew
vels" property is optional and never present on
> i.MX5, turn the message into debug level instead.
Sounds legit to me. This is mainly for compatibility with downstream device tree
files and the folks doing DRM on Android should know what they are doing.
Reviewed-by: Jordan Crous
On Fri, Aug 23, 2019 at 05:16:36AM -0700, Brian Masney wrote:
> The files a3xx_gpu.c and a4xx_gpu.c have ifdefs for the OCMEM support
> that was missing upstream. Add two new functions (adreno_gpu_ocmem_init
> and adreno_gpu_ocmem_cleanup) that removes some duplicated code.
Reviewed-b
-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 28 +
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 1 +
drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 1 +
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 1 +
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 56
that takes advantage of split pagetables
if available.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 16 ++--
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 16 ++--
drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 4
drivers/gpu/drm/msm/disp
/iommu/2019-August/038244.html
[5] https://patchwork.freedesktop.org/patch/307601/
Jordan Crouse (7):
iommu/arm-smmu: Support split pagetables
dt-bindings: arm-smmu: Add Adreno GPU variant
iommu/arm-smmu: Add a SMMU variant for the Adreno GPU
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm
Remove the default for CONFIG_DRM_MSM and let the user select the driver
manually as one does.
Additionally select QCOM_COMMAND_DB for ARCH_QCOM targets to make sure
it doesn't get missed when we need it for a6xx targets.
v2: Move from default 'm' to no default
Signed-off-by: Jordan Crouse
On Wed, Aug 07, 2019 at 11:08:53AM -0700, Rob Clark wrote:
> On Wed, Aug 7, 2019 at 10:38 AM Sam Ravnborg wrote:
> >
> > Hi Jordan.
> > On Wed, Aug 07, 2019 at 11:24:27AM -0600, Jordan Crouse wrote:
> > > Most use cases for DRM_MSM will prefer to build both DR
it in.
Additionally select QCOM_COMMAND_DB for ARCH_QCOM targets to make sure
it doesn't get missed when we need it for a6xx tarets.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Kconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers
Remove the homebrewed bulk clock get function and replace it with
devm_clk_bulk_get_all().
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
drivers/gpu/drm/msm/msm_drv.c | 40 ---
drivers/gpu/drm/msm/msm_drv.h | 1
Explicitly mark intentional fall throughs in switch statements to keep
-Wimplicit-fallthrough from complaining.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 1 +
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 +
3 files
On Thu, Jul 25, 2019 at 11:52:39AM +0800, Yue Hu wrote:
> From: Yue Hu
>
> Since governor name is defined by DEVFREQ framework internally, use the
> macro definition instead of using the name directly.
Acked-by: Jordan Crouse for the msm part.
> Signed-off-by: Yue Hu
> ---
201 - 300 of 1091 matches
Mail list logo
