indentation,
really use qcom,gmu for the phandle name
v2: changed qcom,arc-level to qcom,level following discussion with Viresh;
change gmu phandle to qcom,gmu per Rob
Jordan Crouse (6):
drm/msm/gpu: Remove hardcoded interrupt name
drm/msm: drop interrupt-names
ARM: dts: qcom: Removed unused
Update the GPU bindings and document the new bindings for the GMU
device found with Adreno a6xx targets.
Signed-off-by: Jordan Crouse
---
v7: Updated the GMU compatible string and clarified details about when clocks
can be optional on the GPU
.../devicetree/bindings/display/msm/gmu.txt | 59
Add the nodes to describe the Adreno GPU and GMU devices.
Signed-off-by: Jordan Crouse
---
v7: Updated the GMU compatible string and removed interrupt-names
arch/arm64/boot/dts/qcom/sdm845.dtsi | 122 +++
1 file changed, 122 insertions(+)
diff --git a/arch/arm64/boot
On Tue, Dec 18, 2018 at 02:29:25PM -0800, Doug Anderson wrote:
> Hi,
>
> On Tue, Dec 18, 2018 at 10:32 AM Jordan Crouse wrote:
> >
> > 'interrupt-names' shouldn't be used in cases when there is only
> > one interrupt and it is not otherwise used in
Add documentation for the interconnect and interconnect-names bindings
for the GPU node as detailed by bindings/interconnect/interconnect.txt.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 4
1 file changed, 4 insertions(+)
diff --git a
interconnect name from driver and bindings
Jordan Crouse (3):
drm/msm/a6xx: Add support for an interconnect path
dt-bindings: drm/msm/a6xx: Document interconnect properties for GPU
arm64: dts: sdm845: Add interconnect for GPU
.../devicetree/bindings/display/msm/gpu.txt | 4
arch/arm64
not yet exist.
v5: Remove hardcoded interconnect name and just use the default
v4: Don't use a port string at all to skip the need for names in the DT
v3: Use macros and change port string per Georgi Djakov
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/Kconfig | 1 +
dr
On Thu, Dec 20, 2018 at 10:46:45AM -0800, Chia-I Wu wrote:
> It gets the generic states from the adreno core.
>
> This also adds a missing NULL check in msm_gpu_open.
>
> Signed-off-by: Chia-I Wu
Thanks for the patch. We have an expanded version of the 6xx gpu state in
msm-next [1]. You can l
On Thu, Dec 20, 2018 at 10:47:02AM -0800, Chia-I Wu wrote:
> memptrs_bo is used to store msm_rbmemptrs. Size it correctly.
>
> Signed-off-by: Chia-I Wu
Thanks for your patch. I'm really glad somebody is looking seriously at this
code. We have this in msm-next:
https://cgit.freedesktop.org/~ro
and will need to
> land in a tree that contains that patch.
>
> This patch needs to land before the patch ("arm64: dts: sdm845: Add
> gpu and gmu device nodes") since if a tree contains the device tree
> patch but not this one you'll get a crash at bootup.
>
Add the nodes to describe the Adreno GPU and GMU devices for sdm845.
Signed-off-by: Jordan Crouse
Reviewed-by: Douglas Anderson
Tested-by: Douglas Anderson
---
This has the following dependencies:
[v11,1/9] dt-bindings: opp: Introduce opp-level bindings
https://patchwork.kernel.org/patch
mu device nodes") since if a tree contains the device tree
> patch but not this one you'll get a crash at bootup.
>
> Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support")
> Signed-off-by: Douglas Anderson
I agree that splitting these out make sense for the workfl
Commit 24937c540917 ("dt-bindings: drm/msm/a6xx: Document GMU and update
GPU bindings") mistakenly omitted the GMU bindings as seen in [1].
Return them to their rightful place.
[1] https://patchwork.freedesktop.org/patch/268679/
Signed-off-by: Jordan Crouse
Reviewed-by: R
not yet exist.
v6: use icc_set_bw() instead of icc_set()
v5: Remove hardcoded interconnect name and just use the default
v4: Don't use a port string at all to skip the need for names in the DT
v3: Use macros and change port string per Georgi Djakov
Signed-off-by: Jordan Crouse
---
drivers/gp
On Fri, Jan 18, 2019 at 01:24:18PM -0700, Jordan Crouse wrote:
> Try to get the interconnect path for the GPU and vote for the maximum
> bandwidth to support all frequencies. This is needed for performance.
> Later we will want to scale the bandwidth based on the frequency to
> also
On Fri, Jan 18, 2019 at 01:52:20PM -0800, Doug Anderson wrote:
> Hi,
>
> On Fri, Jan 18, 2019 at 12:24 PM Jordan Crouse wrote:
> >
> > Try to get the interconnect path for the GPU and vote for the maximum
> > bandwidth to support all frequencies. This is needed for per
On Fri, Jan 18, 2019 at 03:04:34PM -0800, Evan Green wrote:
> On Fri, Jan 18, 2019 at 12:24 PM Jordan Crouse wrote:
> >
> > Try to get the interconnect path for the GPU and vote for the maximum
> > bandwidth to support all frequencies. This is needed for performance.
>
On Thu, Feb 14, 2019 at 06:16:01PM -0500, Rob Clark wrote:
> On Thu, Feb 14, 2019 at 2:19 AM Dan Carpenter
> wrote:
> >
> > The copy_to/from_user() functions return the number of bytes remaining
> > to be copied but we should return -EFAULT to the user.
> >
> > Fixes: f05c83e77460 ("drm/msm: add
On Sun, Feb 17, 2019 at 05:43:16PM -0500, Rob Clark wrote:
> On Sun, Feb 17, 2019 at 4:08 PM Rob Herring wrote:
> >
> > On Mon, Feb 4, 2019 at 10:15 AM Jordan Crouse
> > wrote:
> > >
> > > The GMU should have two power domains defined: "cx" an
ries/56656/
Fixes: f05c83e77460 ("drm/msm: add uapi to get/set debug name")
Reported-by: Dan Carpenter
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm
] reported and fixed by Dan Carpenter.
[1] https://patchwork.freedesktop.org/series/56656/
Fixes: f05c83e77460 ("drm/msm: add uapi to get/set debug name")
Reported-by: Dan Carpenter
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 5 -
1 file changed, 4 inser
hicken and egg problem.
Luckily this is easily fixed by removing the pm_runtime calls from the
functions and letting the device link to the IOMMU device handle the magic.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 13 +
1 file changed, 1 insertion(+), 12
The allocation for the clock bulk data does a classic sizeof(pointer)
instead of sizeof(struct) so the array ends up incorrectly sized
for the clock data.
Cc: sta...@vger.kernel.org
Fixes: 8e54eea ("drm/msm: Add a helper function to parse clock names")
Signed-off-by: Jordan Crouse
---
generating 32 bit addresses so switch over now to prepare
for using addresses above 4G for targets that support them.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++
2 files changed, 28 insertions
cular, I want to make sure that this fits with the
current thinking about how aux domains should look and feel.
[1] https://patchwork.freedesktop.org/series/43447/
[2] https://patchwork.kernel.org/patch/10825061/
Jordan Crouse (15):
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm-smmu: Add
Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path. This clears the way
to change ctx->aspace to a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c| 2 ++
drivers/gpu/d
some of the target files but I think
it pays for itself in improved code flow and flexibility.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 37 --
drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 50 ++
drivers/gpu/drm/msm
When we move to 64 bit addressing for a5xx and a6xx targets we will start
seeing pagefaults at larger addresses so format them appropriately in the
log message for easier debugging.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1
.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 120 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 19 +
drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 70 +
3 files changed, 192 insertions(+), 17 deletions(-)
diff
Add a helper function to create a GEM address space attached to
an iommu auxiliary domain for a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.h | 4 +++
drivers/gpu/drm/msm/msm_gem_vma.c | 53 +++
2 files changed
Add support for creating a auxiliary domain from the IOMMU device to
implement per-instance pagetables. Also add a helper function to
return the pagetable base address (ttbr) and asid to the caller so
that the GPU target code can set up the pagetable switch.
Signed-off-by: Jordan Crouse
Add support to create a GPU target specific address space for
a context. For those targets that support per-instance
pagetables they will return a new address space set up for
the instance if possible otherwise just use the global
device pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu
Targets that support per-instance pagetable switching will have to keep
track of which pagetable belongs to each instance to be able to recover
for preemption.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
Add support for per-instance pagetables for a6xx targets. Add support
to handle split pagetables and create a new instance if the needed
IOMMU support exists and insert the necessary PM4 commands to trigger
a pagetable switch at the beginning of a user command.
Signed-off-by: Jordan Crouse
a5xx and a6xx both share (mostly) the same code to load the zap shader and
bring the GPU out of secure mode. Move the formerly 5xx specific code to
adreno to make it available for a6xx too.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 109
M sequence this should fail and we would fall back
to writing the register.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 38 +-
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
2 files changed, 38 insertions(+), 1 deletion(-)
di
Describe the zap-shader node that defines a reserved memory region
to store the zap shader.
Signed-off-by: Jordan Crouse
---
Documentation/devicetree/bindings/display/msm/gpu.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/gpu.txt
b
he final two patches add the DT bindings and DT settings for
setting up the reserved memory that the shader requires.
Jordan Crouse (4):
drm/msm/gpu: Move zap shader loading to adreno
drm/msm/a6xx: Add zap shader load
dt-bindings: drm/msm/gpu: Document a5xx / a6xx zap shader region
arm64:
areas.
Jordan Crouse (16):
iommu/arm-smmu: Allow client devices to select direct mapping
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/io-pgtable-arm: Add support for AARCH64 split pagetables
iommu/arm-smmu: Add support for DOMAIN_ATTR_SPLIT_TABLES
iommu: Add DOMAIN_ATTR_PTBASE
iommu/arm-smmu
generating 32 bit addresses so switch over now to prepare
for using addresses above 4G for targets that support them.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 14 ++
2 files changed, 28 insertions
Add a helper function to create a GEM address space attached to
an iommu auxiliary domain for a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.h | 4 +++
drivers/gpu/drm/msm/msm_gem_vma.c | 53 +++
2 files changed
Add support for creating a auxiliary domain from the IOMMU device to
implement per-instance pagetables. Also add a helper function to
return the pagetable base address (ttbr) and asid to the caller so
that the GPU target code can set up the pagetable switch.
Signed-off-by: Jordan Crouse
Pass the index of the MMU domain in struct msm_file_private instead
of assuming gpu->id throughout the submit path. This clears the way
to change ctx->aspace to a per-instance pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c| 2 ++
drivers/gpu/d
some of the target files but I think
it pays for itself in improved code flow and flexibility.
v3: change NULl return to ERR_PTR in address space create functions
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 37 --
drivers/gpu/drm/msm/adreno
Add support to create a GPU target specific address space for
a context. For those targets that support per-instance
pagetables they will return a new address space set up for
the instance if possible otherwise just use the global
device pagetable.
Signed-off-by: Jordan Crouse
---
drivers/gpu
Targets that support per-instance pagetable switching will have to keep
track of which pagetable belongs to each instance to be able to recover
for preemption.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_ringbuffer.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu
When we move to 64 bit addressing for a5xx and a6xx targets we will start
seeing pagefaults at larger addresses so format them appropriately in the
log message for easier debugging.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_iommu.c | 2 +-
1 file changed, 1 insertion(+), 1
Add support for per-instance pagetables for a6xx targets. Add support
to handle split pagetables and create a new instance if the needed
IOMMU support exists and insert the necessary PM4 commands to trigger
a pagetable switch at the beginning of a user command.
Signed-off-by: Jordan Crouse
.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 120 +-
drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 19 +
drivers/gpu/drm/msm/adreno/a5xx_preempt.c | 70 +
3 files changed, 192 insertions(+), 17 deletions(-)
diff
Before loading the zap shader we should ensure that the reserved memory
region is big enough to hold the loaded file.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno
> It shouldn't be a problem to hook something else up to the IOMMU
> subsystem. Hopefully it's something that people are going to standardize
> on.
>
> > 3) The automatic attach of DMA domain is also causing a different
> >problem for us on the GPU side, preventing us from supporting per-
> >
zable gap in coverage since there
seem to be more of these guys in the world than 8996.
Reviewed-by: Jordan Crouse
> ---
>
> v3:
> -Adjusted MERCIU for A540 for best performance.
>
> drivers/gpu/drm/msm/adreno/a5xx.xml.h | 28
> drivers/gpu/drm/m
On Sun, Jun 16, 2019 at 09:29:26AM -0400, Brian Masney wrote:
> Some A3xx and A4xx Adreno GPUs do not have GMEM inside the GPU core and
> must use the On Chip MEMory (OCMEM) in order to be functional. Add the
> optional ocmem property to the Adreno Graphics Management Unit bindings.
>
> Signed-off
On Sun, Jun 16, 2019 at 09:29:30AM -0400, Brian Masney wrote:
> The files a3xx_gpu.c and a4xx_gpu.c have ifdefs for the OCMEM support
> that was missing upstream. Add two new functions (adreno_gpu_ocmem_init
> and adreno_gpu_ocmem_cleanup) that removes some duplicated code. We also
> need to change
On Wed, Jun 19, 2019 at 12:15:26PM -0600, Jordan Crouse wrote:
> On Sun, Jun 16, 2019 at 09:29:30AM -0400, Brian Masney wrote:
> > The files a3xx_gpu.c and a4xx_gpu.c have ifdefs for the OCMEM support
> > that was missing upstream. Add two new functions (adreno_gpu_ocm
iggers an insta-
> reboot, so lets remove the TPL1 registers from the snapshot.
Not to mention that write only registers are incredibly uninteresting for a
snapshot :)
Reviewed-by: Jordan Crouse
> Fixes: 7198e6b03155 drm/msm: add a3xx gpu support
> Signed-off-by: Rob Clark
> ---
&g
On Mon, Jul 01, 2019 at 11:22:35AM +0800, Fuqian Huang wrote:
> Using dev_get_drvdata directly.
msm parts LGTM. If you split the patches feel free to add my
Acked-by: Jordan Crouse
> Signed-off-by: Fuqian Huang
> ---
> drivers/gpu/drm/msm/adreno/adreno_device.c | 6 ++---
> +MODULE_FIRMWARE("qcom/a630_zap.mdt");
> +MODULE_FIRMWARE("qcom/a630_zap.b00");
> +MODULE_FIRMWARE("qcom/a630_zap.b01");
> +MODULE_FIRMWARE("qcom/a630_zap.b02");
Hopefully we are in the very last days of the split PIL so we can leave this
ugliness
is responsible for any
and if so it can invalidate itself.
This is also helpful for testing by confirming to the user driver if a
particular command stream caused a fault (or not as the case may be).
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/msm_drv.c | 9 +++-
drivers
On Thu, Mar 28, 2019 at 08:32:15AM -0500, Rob Herring wrote:
> On Tue, Mar 12, 2019 at 12:13:41PM -0600, Jordan Crouse wrote:
> > Describe the zap-shader node that defines a reserved memory region
> > to store the zap shader.
> >
> > Signed-off-by: Jordan Crouse
>
On Wed, Apr 03, 2019 at 02:48:11PM +0800, Yue Haibing wrote:
> From: YueHaibing
>
> When building CONFIG_DEBUG_FS is not set
> gcc warn this:
>
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c: In function a6xx_show:
> drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c:1124:2: error: implicit
> declarati
On Sun, Jun 30, 2019 at 06:14:41AM -0700, Rob Clark wrote:
> From: Rob Clark
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_gpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/msm_gp
fore we need to.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c | 5 -
> 1 file changed, 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_mdss.c
>
0/0x438
> kthread+0x12c/0x130
> ret_from_fork+0x10/0x18
>---[ end trace afc0dc5ab81a06bf ]---
>
> Not quite sure what triggered that, but we really shouldn't be abusing
> dma_{map,unmap}_sg() for cache maint.
I'm sure we'll see this rear its head aga
On Thu, Jul 25, 2019 at 11:52:39AM +0800, Yue Hu wrote:
> From: Yue Hu
>
> Since governor name is defined by DEVFREQ framework internally, use the
> macro definition instead of using the name directly.
Acked-by: Jordan Crouse for the msm part.
> Signed-off-by: Yue Hu
> ---
Explicitly mark intentional fall throughs in switch statements to keep
-Wimplicit-fallthrough from complaining.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 ++
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 1 +
drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 +
3 files
Remove the homebrewed bulk clock get function and replace it with
devm_clk_bulk_get_all().
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
drivers/gpu/drm/msm/msm_drv.c | 40 ---
drivers/gpu/drm/msm/msm_drv.h | 1
On Wed, Oct 23, 2019 at 11:00:58AM -0700, Yiwei Zhang wrote:
> Hi folks,
>
> This is Yiwei from the Android Platform Graphics team. On the downstream
> Android, vendors used to report GPU private memory allocations with debugfs
> nodes in their own formats. However, debugfs nodes are getting depre
On Mon, Oct 28, 2019 at 08:47:58AM -0600, Jordan Crouse wrote:
> On Wed, Oct 23, 2019 at 11:00:58AM -0700, Yiwei Zhang wrote:
> > Hi folks,
> >
> > This is Yiwei from the Android Platform Graphics team. On the downstream
> > Android, vendors used to report GPU priv
On Thu, Oct 31, 2019 at 07:03:59PM -0300, Fabio Estevam wrote:
> Hi Rob,
>
> On Tue, Oct 15, 2019 at 11:19 AM Jeffrey Hugo
> wrote:
> >
> > On Tue, Oct 15, 2019 at 7:40 AM Fabio Estevam wrote:
> > >
> > > Booting the adreno driver on a imx53 board leads to the following
> > > error message:
> >
uot;drm/msm/a6xx: Add a6xx gpu state")
Thanks, I was going to suggest this as well.
> Reviewed-by: Rob Clark
Reviewed-by: Jordan Crouse
> > ---
> > drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c | 24
> > 1 file changed, 12 insertions(+), 1
On Tue, Nov 12, 2019 at 01:40:22PM -0300, Fabio Estevam wrote:
> Hi Jordan,
>
> On Fri, Nov 1, 2019 at 11:52 AM Jordan Crouse wrote:
>
> > I'm good with this. This really should only be around for
> > compatibility with downstream device tree files which should me
t overflow, but is easy to avoid by just converting
> the ktime_t into jiffies directly.
This seems good to me. y2038 changes are the best changes.
Reviewed-by: Jordan Crouse
> Signed-off-by: Arnd Bergmann
> ---
> drivers/gpu/drm/msm/msm_drv.h | 3 +--
> 1 file change
On Thu, Nov 14, 2019 at 11:18:56AM +0530, Shubhashree Dhar wrote:
> Current code assumes that all the irqs registers offsets can be
> accessed in all the hw revisions; this is not the case for some
> targets that should not access some of the irq registers.
> This change adds the support to selecti
On Sun, Nov 17, 2019 at 06:48:23AM -0500, Brian Masney wrote:
> Some A3xx and all A4xx Adreno GPUs do not have GMEM inside the GPU core
> and must use the On Chip MEMory (OCMEM) in order to be functional.
> There's a separate interconnect path that needs to be setup to OCMEM.
> Add support for this
but the GMU sneaks out in the middle of the night
and takes the hardware for a joyride.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++--
> drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 3 +++
> 2 files changed, 9 insertions(+
On Sat, Dec 14, 2019 at 05:31:48PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c:905:2-3: Unneeded semicolon
>
Reviewed-by: Jordan Crouse
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drivers/gpu/drm/
On Sat, Dec 14, 2019 at 05:31:47PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/hdmi/hdmi_connector.c:104:3-4: Unneeded semicolon
Reviewed-by: Jordan Crouse
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drivers/gpu/drm/msm/
On Sat, Dec 14, 2019 at 05:31:49PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c:741:2-3: Unneeded semicolon
>
Reviewed-by: Jordan Crouse
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drivers/gpu/drm/m
On Sat, Dec 14, 2019 at 05:31:50PM +0800, zhengbin wrote:
> Fixes coccicheck warning:
>
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c:2260:3-4: Unneeded semicolon
Reviewed-by: Jordan Crouse
>
> Reported-by: Hulk Robot
> Signed-off-by: zhengbin
> ---
> drive
On Tue, Dec 03, 2019 at 03:06:12PM +, Sharat Masetty wrote:
> Add the relevant GBIF registers and the debug bus to the a6xx gpu
> state. This comes in pretty handy when debugging GPU bus related
> issues.
>
> Change-Id: I224fda727012a456ccd28ca14caf9fcce236e629
> Signed-off-by: Sharat Masetty
On Tue, Dec 03, 2019 at 03:06:15PM +, Sharat Masetty wrote:
> Fix the cx debugbus related register configuration, to collect accurate
> bus data during gpu snapshot. This helps with complete snapshot dump
> and also complete proper GPU recovery.
Reviewed-by: Jordan Crouse
This guy
On Tue, Dec 03, 2019 at 03:06:11PM +, Sharat Masetty wrote:
> This patch adds support for enabling Graphics Bus Interface(GBIF)
> used in multiple A6xx series chipets. Also makes changes to the
> PDC/RSC sequencing specifically required for A618. This is needed
> for proper interfacing with RPM
to create the address space so a2xx can do its own thing in its
own space. For all the other targets use a generic helper to initialize
IOMMU but leave the door open for newer targets to use customization
if they need it.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a2xx_gpu.c
/pipermail/iommu/2019-October/039718.html
[2] https://lists.linuxfoundation.org/pipermail/iommu/2019-October/039719.html
[3] https://lists.linuxfoundation.org/pipermail/iommu/2019-October/039720.html
Jordan Crouse (5):
iommu: Add DOMAIN_ATTR_SPLIT_TABLES
iommu/arm-smmu: Add support for split
start swapping TTBR0 for context-specific pagetables.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 52 ++-
1 file changed, 51 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno
aggressive cleanups that follow.
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 8
drivers/gpu/drm/msm/disp/mdp4/mdp4_kms.c | 4
drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c | 7 ---
drivers/gpu/drm/msm/msm_gem_vma.c| 23
On Thu, Dec 19, 2019 at 06:44:45PM +0530, Sharat Masetty wrote:
> Allow different Adreno targets the ability to pass
> specific mmu features to the generic layers. This will
> help conditionally configure certain iommu features for
> certain Adreno targets.
>
> Also Add a few simple support functi
On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote:
> The last level system cache can be partitioned to 32 different slices
> of which GPU has two slices preallocated. One slice is used for caching GPU
> buffers and the other slice is used for caching the GPU SMMU pagetables.
> This pat
On Thu, Dec 19, 2019 at 12:58:15PM -0700, Jordan Crouse wrote:
> On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote:
> > +
> > + /*
> > +* CNTL1 is used to specify SCID for (CP, TP, VFD, CCU and UBWC
> > +* FLAG cache) GPU blocks. This valu
On Fri, Dec 20, 2019 at 03:40:59PM +0530, smase...@codeaurora.org wrote:
> On 2019-12-20 01:28, Jordan Crouse wrote:
> >On Thu, Dec 19, 2019 at 06:44:46PM +0530, Sharat Masetty wrote:
> >>The last level system cache can be partitioned to 32 different slices
> >>
On Tue, Dec 24, 2019 at 08:27:28AM +0530, smase...@codeaurora.org wrote:
> On 2019-12-16 22:07, Jordan Crouse wrote:
> >Attempt to enable split pagetables if the arm-smmu driver supports it.
> >This will move the default address space from the default region to
> >the addr
On Mon, Dec 16, 2019 at 09:37:50AM -0700, Jordan Crouse wrote:
> Refactor how address space initialization works. Instead of having the
> address space function create the MMU object (and thus require separate but
> equal functions for gpummu and iommu) use a single function and pass
On Tue, Jan 07, 2020 at 05:38:42PM -0800, Rob Clark wrote:
> From: Rob Clark
>
> Since zap firmware can be device specific, allow for a firmware-name
> property in the zap node to specify which firmware to load, similarly to
> the scheme used for dsp/wifi/etc.
>
> Signed-off-by: Rob Clark
> ---
warning: symbol
> 'a5xx_gpu_state_put' was not declared. Should it be static?
> drivers/gpu/drm/msm/adreno/a5xx_gpu.c:1302:6: warning: symbol 'a5xx_show' was
> not declared. Should it be static?
Reviewed-by: Jordan Crouse
> Signed-off-by: Ben Dooks
> ---
> Cc: Rob Clark
>
aration introduced in v2
> - Reworked to use ERR_PTR/PTR_ERR
> - Simplified failure gotos.
Reviewed-by: Jordan Crouse
> Signed-off-by: Bas Nieuwenhuizen
> ---
> drivers/gpu/drm/msm/msm_drv.c| 6 +-
> drivers/gpu/drm/msm/msm_gem_submit.c | 232 +++
On Thu, Feb 06, 2020 at 05:43:52PM +0100, Bas Nieuwenhuizen wrote:
> Hi,
>
> I'd appreciate if you could take a look at this patch. I believe I
> have accommodated the earlier review comments.
Sorry, it was sitting on my todo list. Looks good.
> Thank you,
> Bas
>
> On Fri, Jan 24, 2020 at 12:5
ix a small memory leak
and free the buffer allocated by nvmem_cell_read().
Signed-off-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 27 ---
1 file changed, 20 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c
b/drivers/g
mdstream
> buffers.
One nit, but with that:
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_gem.h | 10 ++
> drivers/gpu/drm/msm/msm_gpu.c | 28 +++-
> drivers/gpu/drm/msm/msm_rd.c | 8 +---
>
cmdstream
> buffers.
>
> v2: add missing 'inline'
I should have checked my inbox before responding to v1.
Reviewed-by: Jordan Crouse
> Signed-off-by: Rob Clark
> ---
> drivers/gpu/drm/msm/msm_gem.h | 10 ++
> drivers/gpu/drm/msm/msm_gpu.c | 28 +++
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