Leif Delgass wrote:
On Wed, 5 Feb 2003, Ian Romanick wrote:
Leif Delgass wrote:
Those assumptions seem to be correct. For the most part, your patch
looks a lot like what I have in my local tree. :) The only thing I did
different was I overlapped the zero and one tables.
static GLuint
On Wed, 5 Feb 2003, Leif Delgass wrote:
Also, should I go ahead and commit my revised texmem patch?
Yes.
OK, will do. Do you want to commit your patch for combine3 to texmem? I
don't have an R200, so I can't test that, but it looks like it should be
easy to add there too. If
Leif Delgass wrote:
On Wed, 5 Feb 2003, Leif Delgass wrote:
Also, should I go ahead and commit my revised texmem patch?
Yes.
OK, will do. Do you want to commit your patch for combine3 to texmem? I
don't have an R200, so I can't test that, but it looks like it should be
easy to add there
On Thu, 6 Feb 2003, Ian Romanick wrote:
Some time ago there were some scissor problems that caused every glean
test to always fail. I think those were fixed in the radeon and r200
drivers about 6 months ago. On my R100 the only tests that failed for
me were the subtract tests and the
Ian Romanick wrote:
Leif Delgass wrote:
On Wed, 5 Feb 2003, Ian Romanick wrote:
[...]
Regarding glean, I need to test again, but I was seeing some other
failures even with the mesa-4-0-4 and trunk. I think there were some
off-by-one scissor errors and a couple of others. One question I
On Thu, 6 Feb 2003, Ian Romanick wrote:
I went ahead and committed my texmem changes as well as combine3 for
radeon and r200 (including the change to the zero/one table). I can't
test the r200 version, but it looks almost identical to R100.
Cool. I can't think of any reason why those
Leif Delgass wrote:
On Thu, 6 Feb 2003, Brian Paul wrote:
The mask values indicate which bits in the pixel (word) correspond to each
color channel. The buffer size is the sum of the red, green, blue, and alpha
bits.
Mach64/R128
r g b a amaskbsz ar ag ab aa Xvisual dpth
5 6 5 0
Brian Paul wrote:
Leif Delgass wrote:
On Thu, 6 Feb 2003, Brian Paul wrote:
The mask values indicate which bits in the pixel (word) correspond to
each color channel. The buffer size is the sum of the red, green,
blue, and alpha bits.
Mach64/R128
r g b a amaskbsz ar ag ab aa
Brian Paul wrote:
Err, he updated the texmem branch. I've updated the mesa-4-0-4 branch
so it matches the trunk. Perhaps Ian can update the texmem branch again
with the mga and glint changes. I don't have a copy of that branch
checked out.
Done.
first let me separate the framebuffer data from GL data
by four more spaces.
MGA
r g b a amaskbsz ar ag ab aa Xvisual dpth
5 6 5 0 16 16 16 16 0 16
8 8 8 8 32 16 16 16 0 24
alphaMask should be 0xff00.
In the argb
Alexander Stohr wrote:
first let me separate the framebuffer data from GL data
by four more spaces.
MGA
r g b a amaskbsz ar ag ab aa Xvisual dpth
5 6 5 0 16 16 16 16 0 16
8 8 8 8 32 16 16 16 0 24
alphaMask should be
On Thu, Feb 06, 2003 at 04:39:11PM -0700, Brian Paul wrote:
Alexander Stohr wrote:
GLINT
r g b a amaskbsz ar ag ab aa Xvisual dpth
5 5 5 5 000f1000 16 16 16 16 0 15 (pScrn-depth)
8 8 8 0 24 16 16 16 0 24 (pScrn-depth)
Hey and why does 5+5+5+5
Ian, now that you've merged in the software support for combine3 from the
Mesa trunk, I'm trying to get it working in hardware on R100 with texmem
(impatient as I am ;) ). I don't have Radeon docs, so I'm guessing about
the registers. I'm attaching a patch of what I've got. My assumptions
are
Leif Delgass wrote:
Ian, now that you've merged in the software support for combine3 from the
Mesa trunk, I'm trying to get it working in hardware on R100 with texmem
(impatient as I am ;) ). I don't have Radeon docs, so I'm guessing about
the registers. I'm attaching a patch of what I've got.
Ian, now that you've merged in the software support for combine3 from the
Mesa trunk, I'm trying to get it working in hardware on R100 with texmem
(impatient as I am ;) ).
Where do I find at least a short explanation on the effect this patch should
show to me (to the user) ? The only
On Wed, 5 Feb 2003, Ian Romanick wrote:
Leif Delgass wrote:
Ian, now that you've merged in the software support for combine3 from the
Mesa trunk, I'm trying to get it working in hardware on R100 with texmem
(impatient as I am ;) ). I don't have Radeon docs, so I'm guessing about
the
Martin Spott wrote:
Ian, now that you've merged in the software support for combine3 from the
Mesa trunk, I'm trying to get it working in hardware on R100 with texmem
(impatient as I am ;) ).
Where do I find at least a short explanation on the effect this patch should
show to me (to the user) ?
That would be easy enough to verify with oprofile. Just take a profile
with and without the patch. In order to get profile data on the GL
driver, do this:
oprofpp -l /usr/X11R6/lib/modules/dri/radeon_dri.so
Thanks for the explanation.
If there's anything else I can do to support your
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