On Friday, January 23, 2009 2:08 pm Jesse Barnes wrote:
> With DRI2 and UXA we don't actually tile back, depth or fake front buffers
> like we should on pre-965 chips, since they require fence regs to be set up
> in order to render properly.
>
> This patchset re-adds basic support for tiled renderi
With DRI2 and UXA we don't actually tile back, depth or fake front buffers
like we should on pre-965 chips, since they require fence regs to be set up
in order to render properly.
This patchset re-adds basic support for tiled rendering on pre-965 in some
configurations. It's been lightly teste
