This driver is for the ASPEED BMC SoC's GFX display hardware. This
driver runs on the ARM based BMC systems, unlike the ast driver which
runs on a host CPU and is is for a PCI graphics device.
Signed-off-by: Joel Stanley
Acked-by: Daniel Vetter
Reviewed-by: Noralf Trønnes
--
v2:
Use
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #58 from Diego Viola ---
I restarted the bisect and ended up at the same "bad commit":
6328536ff28ca26f2ad4e6f2c956c467acebda88 is the first bad commit
I wonder what I'm doing wrong...
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On Tue, 05 Mar 2019, claudiu.bez...@microchip.com wrote:
> From: Claudiu Beznea
>
> Add compatible for SAM9X60 HLCD controller.
>
> Signed-off-by: Claudiu Beznea
> ---
> drivers/mfd/atmel-hlcdc.c | 1 +
> 1 file changed, 1 insertion(+)
Applied, thanks.
--
Lee Jones [李琼斯]
Linaro Services
Neil Armstrong writes:
> On 15/03/2019 14:56, Neil Armstrong wrote:
>> This patchset adds :
>> - Optional reset properties in the midgard bindings
>> - Mali T820 Node in Amlogic Meson GXM DTSI
>>
>> Changes since v1:
>> - Updated midgard DT wording following the recently submitted
>> bifrost
This describes the ASPEED BMC SoC's display controller.
Signed-off-by: Joel Stanley
---
.../devicetree/bindings/gpu/aspeed-gfx.txt| 41 +++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/aspeed-gfx.txt
diff --git
This hardware is found inside ASPEED Baseboard Management Controller
(BMC) system on chips. It is called the 'SOC Display Controller' or 'GFX'.
Signed-off-by: Joel Stanley
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index
v2: Address review from Noralf and Daniel, add maintainers patch
This driver is for the ASPEED BMC SoC's GFX display hardware. This
driver runs on the ARM based BMC systems, unlike the ast driver which
runs on a host CPU and is is for a PCIe graphics device that happens to
live in the BMC's
On Thu, 28 Mar 2019 at 07:53, Daniel Vetter wrote:
> > +static int aspeed_gfx_get_modes(struct drm_connector *connector)
> > +{
> > + return drm_add_modes_noedid(connector, 800, 600);
>
> Is this the only mode you do, or just a default? Iirc if you report
> "connected", you'll get this as
On Tue, 05 Mar 2019, claudiu.bez...@microchip.com wrote:
> From: Claudiu Beznea
>
> Add new compatible string for the HLCD controller on SAM9X60 SoC.
>
> Signed-off-by: Claudiu Beznea
> ---
> Documentation/devicetree/bindings/mfd/atmel-hlcdc.txt | 1 +
> 1 file changed, 1 insertion(+)
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #59 from Diego Viola ---
If I do this:
$ git revert -n 6328536ff28ca26f2ad4e6f2c956c467acebda88
$ git revert -n 621b0fa8922ade0a8122b868177308e65e6d3595
Then xterm works fine and I still have direct rendering.
--
You are
Thanks, patch is:
Reviewed-by: Qiang Yu
Regards,
Qiang
On Tue, Apr 2, 2019 at 7:50 AM Stephen Rothwell wrote:
>
> Hi all,
>
> After merging the drm-misc tree, today's linux-next build (x86_64
> allmodconfig) failed like this:
>
> In file included from include/linux/kernel.h:7,
>
On Tue, Apr 2, 2019 at 1:48 AM Eric Anholt wrote:
>
> Qiang Yu writes:
>
> > On Fri, Mar 29, 2019 at 11:20 PM Daniel Vetter wrote:
> >>
> >> On Fri, Mar 29, 2019 at 09:47:48PM +0800, Qiang Yu wrote:
> >> > Signed-off-by: Qiang Yu
> >> > ---
> >> > MAINTAINERS | 9 +
> >> > 1 file
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #55 from Diego Viola ---
(In reply to Michel Dänzer from comment #53)
> It's probably worth trying git bisect again, double-checking at each step
> that you're testing the right thing.
I tried again and I can't get to replace the
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #56 from Diego Viola ---
Here's more or less what I'm currently seeing:
$ ldd /usr/bin/glxinfo | grep libGL
libGL.so.1 => /home/diego/mesa/lib/libGL.so.1 (0x7fbaac886000)
$ ls -l /home/diego/mesa/lib/libGL.so.1
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #57 from Diego Viola ---
I contacted Thomas Dickey (maintainer of xterm) and he said this about the
issue:
drivers, or Xorg in general -
for instance the parts painting by XCopyArea
(used by xterm and some other applications)
may
Hi, Dan:
On Thu, 2019-03-28 at 17:31 +0300, Dan Carpenter wrote:
> We don't want to overwrite "ret", it already holds the correct error
> code. The "regmap" variable might be a valid pointer as this point.
>
> Fixes: 8f83f26891e1 ("drm/mediatek: Add HDMI support")
> Signed-off-by: Dan Carpenter
Add the bindings for the Bifrost family of ARM Mali GPUs.
The Bifrost GPU architecture is similar to the Midgard family,
but with a different Shader Core & Execution Engine structures.
Bindings are based on the Midgard family bindings, but the inner
architectural changes makes it a separate
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #33 from Diego Viola ---
Created attachment 143829
--> https://bugs.freedesktop.org/attachment.cgi?id=143829=edit
glxinfo from Ubuntu 19.04 beta
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The current DT bindings assume that the DMA will be performed by the
devices through their parent DT node, and rely on that assumption for the
address translation using dma-ranges.
However, some SoCs have devices that will perform DMA through another bus,
with separate address translation rules.
Hi,
We've had for quite some time to hack around in our drivers to take into
account the fact that our DMA accesses are not done through the parent
node, but through another bus with a different mapping than the CPU for the
RAM (0 instead of 0x4000 for most SoCs).
After some discussion after
The MBUS clock is used by the MBUS controller, so let's export it so that
we can use it in our DT node.
Reviewed-by: Rob Herring
Signed-off-by: Maxime Ripard
---
drivers/clk/sunxi-ng/ccu-sun5i.h | 4
include/dt-bindings/clock/sun5i-ccu.h | 2 +-
2 files changed, 1 insertion(+), 5
The MBUS controller drives the MBUS that other devices in the SoC will
use to perform DMA. It also has a register interface that allows to
monitor and control the bandwidth and priorities for masters on that
bus.
Signed-off-by: Maxime Ripard
---
Dear Yannick,
Thank you for your patch, works fine,
Acked-by: Philippe Cornu
Philippe :-)
On 4/1/19 9:24 AM, Yannick Fertré wrote:
> Plane updates must be synchronized on vblank with the shadow register
> mechanism
> to avoid partial refresh on screen.
>
> Signed-off-by: Yannick Fertré
>
Dear Yannick,
Fully agree with this approach,
Acked-by: Philippe Cornu
Philippe :-)
On 3/29/19 4:49 PM, Yannick Fertré wrote:
> From: Philippe Cornu
>
> Use DRM_WARN() instead of DRM_DEBUG_DRIVER() to better
> inform the user in case of fifo underruns or
> transfer errors.
>
>
timeline syncobj gives user more flexibility and convenience to do
sychronization.
Lionel has written cts and adapted ANV based on this patch set, and also
reviewed
the patch set.
please someone from community helps to submit the patch set to drm-misc-next.
Christian König (3):
dma-buf: add
ARM Mali midgard GPU is similar to standard 64-bit stage 1 page tables, but
have a few differences. Add a new format type to represent the format. The
input address size is 48-bits and the output address size is 40-bits (and
possibly less?). Note that the later bifrost GPUs follow the standard
Similar to the single handle drm_gem_object_lookup(),
drm_gem_objects_lookup() takes an array of handles and returns an array
of GEM objects.
Cc: Maarten Lankhorst
Cc: Maxime Ripard
Cc: Sean Paul
Cc: David Airlie
Cc: Daniel Vetter
Signed-off-by: Rob Herring
---
drivers/gpu/drm/drm_gem.c |
Here's v2 of the panfrost driver. Lots of improvements from the RFC
primarily with support for job hangs resetting the GPU and runtime-pm
thanks to Tomeu.
Several dependencies have been applied already, but the first 2 patches
are the remaining dependencies. We need to take the iommu change via
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #32 from Michel Dänzer ---
(In reply to Diego Viola from comment #27)
> export LD_LIBRARY_PATH=/home/diego/mesa/lib
> export LIBGL_DRIVERS_PATH=/home/diego/mesa/lib/gallium
>
> So I assume this should make the X server pick the
On 2019年04月01日 16:19, Lionel Landwerlin wrote:
On 01/04/2019 06:54, Zhou, David(ChunMing) wrote:
-Original Message-
From: Lionel Landwerlin
Sent: Saturday, March 30, 2019 10:09 PM
To: Koenig, Christian ; Zhou, David(ChunMing)
; dri-devel@lists.freedesktop.org; amd-
https://bugs.freedesktop.org/show_bug.cgi?id=110229
Daniel Stone changed:
What|Removed |Added
Resolution|--- |NOTOURBUG
Status|NEW
Signed-off-by: Chunming Zhou
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index 8a0732088640..4d8db87048d3
From: Christian König
Use the dma_fence_chain object to create a timeline of fence objects
instead of just replacing the existing fence.
v2: rebase and cleanup
v3: fix garbage collection parameters
v4: add unorder point check, print a warn calltrace
Signed-off-by: Christian König
Cc: Lionel
From: Christian König
Lockless container implementation similar to a dma_fence_array, but with
only two elements per node and automatic garbage collection.
v2: properly document dma_fence_chain_for_each, add dma_fence_chain_find_seqno,
drop prev reference during garbage collection if it's
we need to import/export timeline point.
v2: unify to one transfer ioctl
Signed-off-by: Chunming Zhou
Cc: Lionel Landwerlin
Reviewed-by: Lionel Landwerlin
---
drivers/gpu/drm/drm_internal.h | 2 +
drivers/gpu/drm/drm_ioctl.c| 2 +
drivers/gpu/drm/drm_syncobj.c | 74
user mode can query timeline payload.
v2: check return value of copy_to_user
v3: handle querying entry by entry
v4: rebase on new chain container, simplify interface
v5: query last signaled timeline point, not last point.
v6: add unorder point check
Signed-off-by: Chunming Zhou
Cc: Tobias Hector
Plane updates must be synchronized on vblank with the shadow register mechanism
to avoid partial refresh on screen.
Signed-off-by: Yannick Fertré
---
drivers/gpu/drm/stm/ltdc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/stm/ltdc.c
On 15/03/2019 14:56, Neil Armstrong wrote:
> This patchset adds :
> - Optional reset properties in the midgard bindings
> - Mali T820 Node in Amlogic Meson GXM DTSI
>
> Changes since v1:
> - Updated midgard DT wording following the recently submitted
> bifrost bindings
>
> Christian Hewitt
Am 01.04.19 um 11:05 schrieb Lionel Landwerlin:
> On 01/04/2019 11:50, zhoucm1 wrote:
>>
>>
>> On 2019年04月01日 16:19, Lionel Landwerlin wrote:
>>> On 01/04/2019 06:54, Zhou, David(ChunMing) wrote:
> -Original Message-
> From: Lionel Landwerlin
> Sent: Saturday, March 30,
Hi, Wangyan:
On Wed, 2019-03-27 at 17:19 +0800, wangyan wang wrote:
> From: chunhui dai
>
> move the setting of fixed divider from enable/disable
> to the function of setting rate.
>
> the patch is for hdmi pll divider, the divder should
> be configured before clock calculation to ensure the
>
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #37 from Michel Dänzer ---
Hmm, Mesa was built against LLVM 7 in Arch & Fedora, against LLVM 8/9 in
Ubuntu. Maybe this was an LLVM issue fixed in version 8?
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Hi, Wangyan:
As offline discuss, I think you could just remove the flag
CLK_SET_RATE_PARENT and do not add CLK_SET_RATE_NO_REPARENT.
I would like the title to be more clear about what you do so we could
quickly understand what this patch do. For example:
drm/mediatek: remove flag
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #39 from Michel Dänzer ---
(In reply to Diego Viola from comment #38)
> Unfortunately that's not the issue, llvm-libs 8.0.0 just landed on Arch
> Linux [extra] repository and the issue still persists.
Has Mesa been rebuilt against
On Sat, Mar 30, 2019 at 10:07:58PM +0100, Noralf Trønnes wrote:
>
>
> Den 28.03.2019 09.17, skrev Daniel Vetter:
> > On Tue, Mar 26, 2019 at 06:55:43PM +0100, Noralf Trønnes wrote:
> >> drm_fb_helper_is_bound() is used to check if DRM userspace is in control.
> >> This is done by looking at the
On Fri, Mar 29, 2019 at 11:52:01AM -0500, Andrew F. Davis wrote:
> The docs state the callback is optional but it is not, make it optional.
>
> Signed-off-by: Andrew F. Davis
There's a bunch of dummy mmap implementations we could remove with this,
would be nice to follow up.
Reviewed-by:
Le ven. 29 mars 2019 à 16:42, Andrew F. Davis a écrit :
>
> On 3/29/19 10:30 AM, Benjamin Gaignard wrote:
> > Le ven. 29 mars 2019 à 16:19, Andrew F. Davis a écrit :
> >>
> >> On 3/29/19 9:44 AM, Benjamin Gaignard wrote:
> >>> Le ven. 29 mars 2019 à 01:16, John Stultz a
> >>> écrit :
>
>
Hi Andrew,
On Tue, Mar 19, 2019 at 7:47 AM Souptick Joarder wrote:
>
> Previouly drivers have their own way of mapping range of
> kernel pages/memory into user vma and this was done by
> invoking vm_insert_page() within a loop.
>
> As this pattern is common across different drivers, it can
> be
On 01/04/2019 06:54, Zhou, David(ChunMing) wrote:
-Original Message-
From: Lionel Landwerlin
Sent: Saturday, March 30, 2019 10:09 PM
To: Koenig, Christian ; Zhou, David(ChunMing)
; dri-devel@lists.freedesktop.org; amd-
g...@lists.freedesktop.org; ja...@jlekstrand.net; Hector, Tobias
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #34 from Diego Viola ---
Created attachment 143830
--> https://bugs.freedesktop.org/attachment.cgi?id=143830=edit
glxinfo from Ubuntu 18.04.2
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Le mar. 26 mars 2019 à 14:02, Philippe CORNU a écrit :
>
> (+ Benjamin)
>
> Dear Yannick,
> Many thanks for your patch.
> Acked-by: Philippe Cornu
>
> Dear Benjamin,
> May I ask you please to merge this patch + "drm/stm: dw_mipi_dsi-stm:
> add sleep power management" on drm-misc, if you agree of
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #35 from Diego Viola ---
Created attachment 143831
--> https://bugs.freedesktop.org/attachment.cgi?id=143831=edit
glxinfo from Fedora 29
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https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #36 from Diego Viola ---
(In reply to Michel Dänzer from comment #32)
> (In reply to Diego Viola from comment #27)
> > export LD_LIBRARY_PATH=/home/diego/mesa/lib
> > export LIBGL_DRIVERS_PATH=/home/diego/mesa/lib/gallium
> >
> >
On Wed, 2019-03-27 at 17:19 +0800, wangyan wang wrote:
> From: chunhui dai
>
> Recalculate the rate of this clock, by querying hardware.
You just describe _WHAT_ do you do here, I would like you to describe
_WHT_ do you do here. I think this patch is to make implementation of
recalc_rate() to
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #38 from Diego Viola ---
(In reply to Michel Dänzer from comment #37)
> Hmm, Mesa was built against LLVM 7 in Arch & Fedora, against LLVM 8/9 in
> Ubuntu. Maybe this was an LLVM issue fixed in version 8?
Unfortunately that's not
points array is one-to-one match with syncobjs array.
v2:
add seperate ioctl for timeline point wait, otherwise break uapi.
v3:
userspace can specify two kinds waits::
a. Wait for time point to be completed.
b. and wait for time point to become available
v4:
rebase
v5:
add comment for
From: Christian König
Implement finding the right timeline point in drm_syncobj_find_fence.
v2: return -EINVAL when the point is not submitted yet.
v3: fix reference counting bug, add flags handling as well
v4: add timeout for find fence
Signed-off-by: Christian König
Cc: Lionel Landwerlin
v2: individually allocate chain array, since chain node is free independently.
v3: all existing points must be already signaled before cpu perform signal
operation,
so add check condition for that.
v4: remove v3 change and add checking to prevent out-of-order
v5: unify binary and timeline
syncobj wait/signal operation is appending in command submission.
v2: separate to two kinds in/out_deps functions
v3: fix checking for timeline syncobj
Signed-off-by: Chunming Zhou
Cc: Tobias Hector
Cc: Jason Ekstrand
Cc: Dave Airlie
Cc: Chris Wilson
Cc: Lionel Landwerlin
Reviewed-by:
On 01/04/2019 09:47, Rob Herring wrote:
> This adds the initial driver for panfrost which supports Arm Mali
> Midgard and Bifrost family of GPUs. Currently, only the T860 and
> T760 Midgard GPUs have been tested.
>
> v2:
> - Add GPU reset on job hangs (Tomeu)
> - Add RuntimePM and devfreq support
The MBUS (and its associated controller) is the bus in the Allwinner SoCs
that DMA devices use in the system to access the memory.
Among other things (and depending on the SoC generation), it can also
enforce priorities or report bandwidth usages on a per-master basis.
One of the most notable
Some SoCs have devices that are using a separate bus from the main bus to
perform DMA.
These buses might have some restrictions and/or different mapping than from
the CPU side, so we'd need to express those using the usual dma-ranges, but
using a different DT node than the node's parent.
Now
Now that we can express our DMA topology, rely on those property instead of
hardcoding an offset from the dma_addr_t which wasn't really great.
We still need to add some code to deal with the old DT that would lack that
property, but we move the offset to the DRM device dma_pfn_offset to be
able
The __of_translate_address function is used to translate the device tree
addresses to physical addresses using the various ranges property to create
the offset.
However, it's shared between the CPU addresses (based on the ranges
property) and the DMA addresses (based on dma-ranges). Since we're
https://bugs.freedesktop.org/show_bug.cgi?id=110229
--- Comment #18 from Laurent ---
I saw you wrote a GLSL compiler to translate GLSL source code to binary code
but I think it's a waste of time because GLSL source code is very similar to C
source code so I think I'll use gcc compiler to
Le mar. 26 mars 2019 à 13:57, Philippe CORNU a écrit :
>
> Dear Yannick,
> Many thanks for your patch.
>
> Acked-by: Philippe Cornu
Applied on drm-misc-next.
Benjamin
>
> Philippe :-)
>
>
> On 3/21/19 9:13 AM, Yannick Fertré wrote:
> > Implements system sleep power management ops.
> >
> >
https://bugs.freedesktop.org/show_bug.cgi?id=110290
Michel Dänzer changed:
What|Removed |Added
Component|DRM/AMDgpu |DRM/AMDgpu-pro
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On 01/04/2019 11:50, zhoucm1 wrote:
On 2019年04月01日 16:19, Lionel Landwerlin wrote:
On 01/04/2019 06:54, Zhou, David(ChunMing) wrote:
-Original Message-
From: Lionel Landwerlin
Sent: Saturday, March 30, 2019 10:09 PM
To: Koenig, Christian ; Zhou,
David(ChunMing)
;
On 3/29/19 4:48 PM, Yannick Fertré wrote:
> Interrupt register must be disabled before call of
> devm_request_threaded_irq function to avoid dummy interruption.
>
> Signed-off-by: Yannick Fertré
> ---
> drivers/gpu/drm/stm/ltdc.c | 8
> 1 file changed, 4 insertions(+), 4
On 3/29/19 10:32 PM, Mukesh Ojha wrote:
>
> On 3/29/2019 9:20 PM, Yannick Fertré wrote:
>> Wrong DISPLAY_FLAGS used to set the data enable polarity.
> Used or checked?
> Can you also explain how it is wrong to check against this FLAG in commit?
Dear Yannick,
Many thanks for your patch,
Dear
Hi, Wangyan:
I would like the title to more clear about what this patch do. For
example:
drm/mediatek: no change parent rate in round_rate() for MT2701 HDMI phy
On Wed, 2019-03-27 at 17:19 +0800, wangyan wang wrote:
> From: chunhui dai
>
> We should not change the rate of parent for hdmi phy
On 03/21/2019 11:52 PM, Christoph Hellwig wrote:
> gbefb uses managed resources, so it should do the same for DMA
> allocations.
>
> Signed-off-by: Christoph Hellwig
Acked-by: Bartlomiej Zolnierkiewicz
Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R Institute Poland
Samsung Electronics
On 03/20/2019 11:07 AM, Lee Jones wrote:
On 02/12/2019 09:42 AM, Lee Jones wrote:
> On Fri, 08 Feb 2019, Bartlomiej Zolnierkiewicz wrote:
>
>>
>> On 01/17/2019 05:19 PM, Daniel Thompson wrote:
>>> On Thu, Jan 17, 2019 at 04:33:35PM +0300, Alexander Shiyan wrote:
https://bugs.freedesktop.org/show_bug.cgi?id=108521
--- Comment #49 from Alex Deucher ---
(In reply to Dimitar Atanasov from comment #48)
> May be problem is the CPU, because it has only 16 PCIe lains, so 8 for vega
> M,
> 4 for NVME, and 4 for others, I have seen that card reader is also
On 03/31/2019 02:18 PM, Sudip Mukherjee wrote:
> On Sun, Mar 17, 2019 at 06:24:56AM +0800, Yifeng Li wrote:
>> Hi all,
>>
>> This patchset contains a series of important fixes to various problems,
>> including lockups, crashes, screen gliches, and missing video modes.
>> These patches are crucial
Chris Wilson writes:
> Quoting Daniel Vetter (2019-04-01 14:06:48)
>> On Mon, Apr 1, 2019 at 9:47 AM Rob Herring wrote:
>> > +{
>> > + int i, ret = 0;
>> > + struct drm_gem_object *obj;
>> > +
>> > + spin_lock(>table_lock);
>> > +
>> > + for (i = 0; i < count; i++) {
>>
Rob Herring writes:
> This adds the initial driver for panfrost which supports Arm Mali
> Midgard and Bifrost family of GPUs. Currently, only the T860 and
> T760 Midgard GPUs have been tested.
>
> v2:
> - Add GPU reset on job hangs (Tomeu)
> - Add RuntimePM and devfreq support (Tomeu)
> - Fix
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #53 from Michel Dänzer ---
It's probably worth trying git bisect again, double-checking at each step that
you're testing the right thing.
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On Thu, Mar 28, 2019 at 08:32:15AM -0500, Rob Herring wrote:
> On Tue, Mar 12, 2019 at 12:13:41PM -0600, Jordan Crouse wrote:
> > Describe the zap-shader node that defines a reserved memory region
> > to store the zap shader.
> >
> > Signed-off-by: Jordan Crouse
> > ---
> >
> >
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #54 from Diego Viola ---
(In reply to Michel Dänzer from comment #53)
> It's probably worth trying git bisect again, double-checking at each step
> that you're testing the right thing.
Sure, I think my attempt from #c47 should have
Hi Thierry,
On Mon, Feb 18, 2019 at 9:27 PM Fabio Estevam wrote:
>
> Add support for the VXT VL050-8048NT-C01 800x480 panel to the
> panel-simple driver.
>
> This panel is used on some boards manufactured by TechNexion, such as
> imx7d-pico.
>
> Reviewed-by: Otavio Salvador
> Reviewed-by: Sam
On 03/29/2019 09:46 PM, Mukesh Ojha wrote:
>
> On 3/19/2019 5:50 PM, shile.zh...@linux.alibaba.com wrote:
>> From: Shile Zhang
>>
>> To fix following divide-by-zero error found by Syzkaller:
>>
>>divide error: [#1] SMP PTI
>>CPU: 7 PID: 8447 Comm: test Kdump: loaded Not tainted
>>
https://bugzilla.kernel.org/show_bug.cgi?id=203111
Alex Deucher (alexdeuc...@gmail.com) changed:
What|Removed |Added
CC|
On 3/29/19 7:26 PM, Zengtao (B) wrote:
Hi laura:
-Original Message-
From: Laura Abbott [mailto:labb...@redhat.com]
Sent: Friday, March 29, 2019 9:27 PM
To: Zengtao (B) ; sumit.sem...@linaro.org
Cc: Greg Kroah-Hartman ; Arve Hjønnevåg
; Todd Kjos ; Martijn Coenen
; Joel Fernandes ;
On Fri, Mar 29, 2019 at 06:46:21PM +, Robin Murphy wrote:
> On 19/03/2019 14:49, Liviu Dudau wrote:
> > On Tue, Mar 19, 2019 at 01:14:54PM +, Robin Murphy wrote:
> > > [ +Sudeep - just FYI ]
> > >
> > > Hi Liviu,
> > >
> > > On 27/02/2019 09:40, Liviu Dudau wrote:
> > > > Hi Robin,
> > >
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #52 from Diego Viola ---
(In reply to Michel Dänzer from comment #51)
> (In reply to Diego Viola from comment #46)
> > Maybe that's why the bisect went bad?
>
> That's likely one reason at least. At this point it's probably best if
https://bugs.freedesktop.org/show_bug.cgi?id=109345
--- Comment #6 from Alex Deucher ---
(In reply to Allan Cairns from comment #5)
> Created attachment 143815 [details]
> Additional dmseg logs
>
> dmseg output for
> Xeno Kernel 5 with no DRM - Boots to second card Firepro
> Xeno Kernel 5.1 RC2
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu.h| 22 ++
amdgpu/amdgpu_cs.c | 16
2 files changed, 38 insertions(+)
diff --git a/amdgpu/amdgpu.h b/amdgpu/amdgpu.h
index b5bd3ed9..2350835b 100644
--- a/amdgpu/amdgpu.h
+++ b/amdgpu/amdgpu.h
@@ -1670,6
v2: adapt to new one transfer ioctl
Signed-off-by: Chunming Zhou
---
amdgpu/amdgpu-symbol-check | 3 ++
amdgpu/amdgpu.h| 51
amdgpu/amdgpu_cs.c | 68 ++
3 files changed, 122 insertions(+)
diff --git
v2: symbos are stored in lexical order.
v3: drop export/import and extra query indirection
Signed-off-by: Chunming Zhou
Signed-off-by: Christian König
---
amdgpu/amdgpu-symbol-check | 2 ++
amdgpu/amdgpu.h| 39 ++
amdgpu/amdgpu_cs.c | 23
This adds support for the Mixel DPHY as found on i.MX8 CPUs but since
this is an IP core it will likely be found on others in the future. So
instead of adding this to the nwl host driver make it a generic PHY
driver.
The driver supports the i.MX8MQ. Support for i.MX8QM and i.MX8QXP can be
added
Add DT property for defining the pin used for HPD.
Signed-off-by: Tomi Valkeinen
Cc: devicet...@vger.kernel.org
Cc: Rob Herring
---
* Dropped the interrupt properties
* Renamed hpd-num to hpd-pin
* Added toshiba prefix for hpd-pin
.../devicetree/bindings/display/bridge/toshiba,tc358767.txt
Support Rocktech jh057n00900 5.5" 720x1440 TFT LCD panel. It is a MIPI
DSI video mode panel.
The panel seems to use a Sitronix ST7703 look alike (most of the
commands look similar to the ST7703's data sheet but use a different
number of parameters). The initial version of the DSI init sequence
v4 fixes up the DT binding example and uses a wider cc list since I
failed to extend that when touching more files.
The panel is a 5.5" 720x1440 TFT LCD MIPI DSI panel with built in
touchscreen and backlight as found in the Librem 5 devkit.
These patches are against linux next as of 2019-03-22.
Add ROCKTECH DISPLAYS LIMITED (https://rocktech.com.hk) LCD panel
supplier.
Signed-off-by: Guido Günther
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt
The Rocktec jh057n00900 is a 5.5" MIPI DSI video mode panel with a
720x1440 resolution and a built in backlight.
Signed-off-by: Guido Günther
---
.../display/panel/rocktech,jh057n00900.txt | 18 ++
1 file changed, 18 insertions(+)
create mode 100644
On 01/04/2019 12:00, Steven Price wrote:
> On 01/04/2019 09:09, Neil Armstrong wrote:
>> Add the bindings for the Bifrost family of ARM Mali GPUs.
>>
>> The Bifrost GPU architecture is similar to the Midgard family,
>> but with a different Shader Core & Execution Engine structures.
>>
>> Bindings
On 02/15/2019 09:25 AM, Geert Uytterhoeven wrote:
> On Fri, Feb 15, 2019 at 3:19 AM Finn Thain wrote:
>> The value of info->var.bits_per_pixel get checked in macfb_setcolreg().
>> Remove additional checks as they are redundant.
>>
>> macfb_defined.activate gets initialized to FB_ACTIVATE_NOW by
On Thu, Mar 28, 2019 at 01:02:49PM +, Mans Rullgard wrote:
> Sometimes it is desirabled to use a separate i2c controller for ddc
> access. This adds support for the ddc-i2c-bus property of the
> hdmi-connector node, using the specified controller if provided.
>
> Signed-off-by: Mans Rullgard
On 02/15/2019 09:58 AM, Geert Uytterhoeven wrote:
> Hi all,
>
> This patch series fixes the frame buffer on Atari Falcon when using
> kexec while blanked, and does some miscellaneous cleanups.
>
> This has been tested on ARAnyM.
>
> Thanks!
>
> Geert Uytterhoeven (4):
> fbdev: atafb:
https://bugs.freedesktop.org/show_bug.cgi?id=110214
--- Comment #47 from Diego Viola ---
OK, this one is also weird, I've compiled mesa-18.3.0 in my home directory,
exported these two variables:
export LD_LIBRARY_PATH=/home/diego/mesa/lib
export LIBGL_DRIVERS_PATH=/home/diego/mesa/lib/gallium
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