From: Dave Airlie
This looked like indirect ptr for not much reason in the create
object path, I just wonder why it couldn't be simpler like this,
The tests aren't cleaned up but this was more of is this a good idea
test patch.
---
drivers/gpu/drm/i915/gem/i915_gem_lmem.c | 16 ---
To use QHD or higher, we need to modify the pixel_bvb_clk value. So
add register to control this clock.
Signed-off-by: Hoegeun Kwon
---
drivers/clk/bcm/clk-raspberrypi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/bcm/clk-raspberrypi.c
b/drivers/clk/bcm/clk-raspberrypi.c
It is necessary to control the hdmi pixel bvb clock. Add bvb clock.
Signed-off-by: Hoegeun Kwon
---
arch/arm/boot/dts/bcm2711-rpi-4-b.dts | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
b/arch/arm/boot/dts/bcm2711-rpi-4-b.dts
When using a resolution exceeding FHD, bvb clock is required.
Add bvb clock-names property.
Signed-off-by: Hoegeun Kwon
---
.../bindings/display/brcm,bcm2711-hdmi.yaml | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git
Hi everyone,
There is a problem that the output does not work at a resolution
exceeding FHD. To solve this, we need to adjust the bvb clock at a
resolution exceeding FHD.
Rebased on top of next-20200708 and [1].
[1] : [PATCH v4 00/78] drm/vc4: Support BCM2711 Display Pipeline (Maxime's
There is a problem that the output does not work at a resolution
exceeding FHD. To solve this, we need to adjust the bvb clock at a
resolution exceeding FHD.
Signed-off-by: Hoegeun Kwon
---
drivers/gpu/drm/vc4/vc4_hdmi.c | 25 +
drivers/gpu/drm/vc4/vc4_hdmi.h | 1 +
2
https://bugzilla.kernel.org/show_bug.cgi?id=208373
--- Comment #3 from Lucas (l.sym...@live.com) ---
(In reply to Alex Deucher from comment #1)
> If this is a regression between 5.7.2 and 5.7.0, can you bisect?
How do you Bisect? I can try doing that if it helps.
Also, kernel 8.5.3-2 seemed to
Hi Swapnil,
Thank you for the patch.
On Mon, Aug 31, 2020 at 10:23:34AM +0200, Swapnil Jakhade wrote:
> Add a new DRM bridge driver for Cadence MHDP8546 DPTX IP used in TI J721E
> SoC. MHDP DPTX IP is the component that complies with VESA DisplayPort (DP)
> and embedded Display Port (eDP)
Initializes Mipi DSI and sets up connects to ADV bridge
v2: removed license text
upclassed dev_private, removed HAVE_IRQ. (Sam)
v3: Squashed all 59 commits to one
v4: review changes from Sam Ravnborg
renamed dev_p to kmb
v5: corrected spellings
v6: corrected checkpatch warnings
v7:
This is a new DRM driver for Intel's KeemBay SOC.
The SoC couples an ARM Cortex A53 CPU with an Intel
Movidius VPU.
This driver is tested with the KMB EVM board which is the refernce baord
for Keem Bay SOC. The SOC's display pipeline is as follows
+--++-+
Cc: Sam Ravnborg
Signed-off-by: Anitha Chrisanthus
Reviewed-by: Bob Paauwe
---
drivers/gpu/drm/Kconfig | 2 ++
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/kmb/Kconfig | 13 +
drivers/gpu/drm/kmb/Makefile | 2 ++
4 files changed, 18 insertions(+)
create mode 100644
Hi Maxime,
Thank you for the patch.
On Thu, Jul 30, 2020 at 11:35:02AM +0200, Maxime Ripard wrote:
> The current code to parse the DT, deal with the older device trees, and
> register either the RGB or LVDS output has so far grown organically into
> the bind function and has become quite hard to
On Sun, Aug 30, 2020 at 3:26 AM Sandeep Raghuraman wrote:
>
Please add a commit message. Also, split this into 2-3 patches:
1. add the new dpm callback
2. add the sumo implementation of the new callback (could be combined with 1)
3. expose the voltage via hwmon
For the last patch, you probably
Thank you reviews by Dave, Maxime and Stefan.
On 8/29/20 12:37 AM, Dave Stevenson wrote:
> Hi Maxime, Stefan, and Hoegeun
>
> On Fri, 28 Aug 2020 at 16:25, Maxime Ripard wrote:
>> Hi,
>>
>> On Fri, Aug 28, 2020 at 02:45:49PM +0200, Stefan Wahren wrote:
>>> Am 28.08.20 um 08:30 schrieb Hoegeun
Hi Maxime,
Thank you for the patch.
On Thu, Jul 30, 2020 at 11:35:01AM +0200, Maxime Ripard wrote:
> The drm_of_lvds_get_dual_link_pixel_order() function took so far the
> device_node of the two ports used together to make up a dual-link LVDS
> output.
>
> This assumes that a binding would use
On Mon, Aug 31, 2020 at 7:35 PM Bjorn Andersson
wrote:
>
> On Fri 14 Aug 02:40 UTC 2020, Rob Clark wrote:
>
> > From: Rob Clark
> >
> > Currently it doesn't matter, since we free the ctx immediately. But
> > when we start refcnt'ing the ctx, we don't want old dangling list
> > entries to hang
This is a basic KMS atomic modesetting display driver for KeemBay family of
SOCs. Driver has no 2D or 3D graphics.It calls into the ADV bridge
driver at the connector level.
Single CRTC with LCD controller->mipi DSI-> ADV bridge
Only 1080p resolution and single plane is supported at this time.
Register definitions for Keem Bay display driver
v2: removed license text (Sam)
v3: Squashed all 59 commits to one
v4: review changes from Sam Ravnborg
renamed dev_p to kmb
v5: corrected spellings
v6: corrected checkpatch warnings
Cc: Sam Ravnborg
Signed-off-by: Anitha Chrisanthus
On Fri, Aug 28, 2020 at 09:07:13AM +0800, crj wrote:
> Hi Ville Syrjälä,
>
> 在 2020/8/27 18:57, Ville Syrjälä 写道:
> > On Wed, Aug 26, 2020 at 10:23:28PM +0800, Algea Cao wrote:
> >> CEA 861.3 spec adds colorimetry data block for HDMI.
> >> Parsing the block to get the colorimetry data from
> >>
Hi Sam,
Thanks a lot for the review. I will address your comments in v7.
For those that are not addressed, please see my reply inline.
Regards,
Anitha
> -Original Message-
> From: Sam Ravnborg
> Sent: Thursday, August 20, 2020 1:10 PM
> To: Chrisanthus, Anitha
> Cc:
On Thu, Aug 27, 2020 at 01:04:54PM +0800, Kai Heng Feng wrote:
> Hi Ville,
>
> > On Aug 27, 2020, at 12:24 AM, Ville Syrjälä
> > wrote:
> >
> > On Wed, Aug 26, 2020 at 01:21:15PM +0800, Kai-Heng Feng wrote:
> >> LSPCON only supports 8 bpc for RGB/YCbCr444.
> >>
> >> Set the correct bpp
On Sun, Aug 30, 2020 at 3:25 AM Sandeep Raghuraman wrote:
>
> This patch series adds support for reporting sclk and vddc values for Radeon
> GPUs, where supported.
This commit message should be specific to this particular patch rather
than the series. You could probably expose mclk as well.
Hi Maxime,
Thank you for the patch.
On Thu, Jul 30, 2020 at 11:35:03AM +0200, Maxime Ripard wrote:
> The A20 can use its second TCON as the secondary LVDS link in a dual-link
> setup, with the TCON0 being the main link. Extend a bit the parsing code to
> leverage the DRM dual-link code, register
topic/nouveau-i915-dp-helpers-and-cleanup-2020-08-31-1:
UAPI Changes:
None
Cross-subsystem Changes:
* Moves a bunch of miscellaneous DP code from the i915 driver into a set
of shared DRM DP helpers
Core Changes:
* New DRM DP helpers (see above)
Driver Changes:
* Implements usage of the
https://bugzilla.kernel.org/show_bug.cgi?id=208893
--- Comment #15 from Alex Deucher (alexdeuc...@gmail.com) ---
Does setting amdgpu.dpm=0 on the kernel command line in grub fix the issue? If
so, remove that and try setting amdgpu.ppfeaturemask=0xbffd on the kernel
command line in grub.
Hi Krzysztof,
On 29.08.2020 19:25, Krzysztof Kozlowski wrote:
> Commit 52005dece527 ("ARM: dts: Add assigned clock parents to CMU node
> for exynos3250") added assigned clocks under Clock Management Unit to
> fix hangs when accessing ISP registers.
>
> This is not the place for it as CMU does not
On Mon, 2020-08-31 at 07:03 +0800, Chun-Kuang Hu wrote:
> Hi, Chunfeng & Kishon:
>
> How do you feel about this patch?
It's fine to me,
Reviewed-by: Chunfeng Yun
Thanks a lot
>
> Regards,
> Chun-Kuang.
>
> Chun-Kuang Hu 於 2020年8月23日 週日 上午9:48寫道：
> >
> > From: CK Hu
> >
> > mtk_hdmi_phy
27.08.2020 18:54, Thierry Reding пишет:
...
>> The Tegra DRM has a very special quirk for ARM32 that was added in this
>> commit [2] and driver relies on checking of whether explicit or implicit
>> IOMMU is used in order to activate the quirk.
>>
>> [2]
>>
Hi Samuel,
Am Montag, 31. August 2020, 02:47:56 CEST schrieb Samuel Dionne-Riel:
> I have an Asus Chromebook Tablet CT100PA, which I will refer to as
> "dumo" from this point on, which is a specific variant of gru-scarlet.
> As far as I am aware, all gru-scarlet are the same, except for the
>
On Sun, Aug 30, 2020 at 02:57:48PM +0200, Hans de Goede wrote:
> Replace the enable, disable and config pwm_ops with an apply op,
> to support the new atomic PWM API.
>
> Reviewed-by: Andy Shevchenko
> Signed-off-by: Hans de Goede
> ---
> Changes in v6:
> - Rebase on 5.9-rc1
> - Use do_div when
On Sun, Aug 30, 2020 at 02:57:49PM +0200, Hans de Goede wrote:
> Implement the pwm_ops.get_state() method to complete the support for the
> new atomic PWM API.
>
> Reviewed-by: Andy Shevchenko
> Signed-off-by: Hans de Goede
> ---
> Changes in v6:
> - Rebase on 5.9-rc1
> - Use DIV_ROUND_UP_ULL
This is a note to let you know that I've just added the patch titled
drm/modeset-lock: Take the modeset BKL for legacy drivers
to the 5.8-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
On Mon, Aug 31, 2020 at 10:19:06AM +0200, Krzysztof Kozlowski wrote:
> On Mon, Aug 31, 2020 at 10:11:02AM +0200, Marek Szyprowski wrote:
> > Hi Krzysztof,
> >
> > On 29.08.2020 19:25, Krzysztof Kozlowski wrote:
> > > Commit 52005dece527 ("ARM: dts: Add assigned clock parents to CMU node
> > > for
Hi Philipp,
url:
https://github.com/0day-ci/linux/commits/Philipp-Zabel/drm-add-drmm_encoder_alloc/20200826-203629
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-m001-20200826 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-15) 9.3.0
If you fix
Am 31.08.20 um 06:16 schrieb Randy Dunlap:
Fix kernel-doc warning in :
../include/linux/dma-buf.h:330: warning: Function parameter or member
'name_lock' not described in 'dma_buf'
Signed-off-by: Randy Dunlap
Cc: Sumit Semwal
Cc: Gustavo Padovan
Cc: Christian König
Cc:
https://bugzilla.kernel.org/show_bug.cgi?id=203905
shanmukhat...@gmail.com (shanmukhat...@gmail.com) changed:
What|Removed |Added
CC|
On Sun, Aug 30, 2020 at 02:57:42PM +0200, Hans de Goede wrote:
> Before this commit a suspend + resume of the LPSS PWM controller
> would result in the controller being reset to its defaults of
> output-freq = clock/256, duty-cycle=100%, until someone changes
> to the output-freq and/or duty-cycle
On 29.08.2020 16:24, Krzysztof Kozlowski wrote:
> Additional properties actually might appear (e.g. power-domains) so use
> unevaluatedProperties to fix dtbs_check warnings like:
>
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dt.yaml: i2s@1144:
> Additional properties are not allowed
Add a new DRM bridge driver for Cadence MHDP8546 DPTX IP used in TI J721E
SoC. MHDP DPTX IP is the component that complies with VESA DisplayPort (DP)
and embedded Display Port (eDP) standards. It integrates uCPU running the
embedded Firmware (FW) interfaced over APB interface.
Basically, it takes
On Mon, Aug 31, 2020 at 7:30 AM Ben Skeggs wrote:
>
> On Tue, 25 Aug 2020 at 17:21, Alexander Kapshuk
> wrote:
> >
> > Since upgrading to linux-next based on 5.9.0-rc1 and 5.9.0-rc2 I have
> > had my mouse pointer disappear soon after logging in, and I have
> > observed the system freezing
Hi Leon,
Le dim. 30 août 2020 à 16:36, 何小龙 (Leon He)
a écrit :
+struct ili9341 {
+ struct drm_panel panel;
+ struct mipi_dsi_device *dsi;
+ const struct ili9341_pdata *pdata;
+
+ struct gpio_desc*reset_gpiod;
+ u32 rotation;
+};
+
Hi Paul, you
Daniel Vetter 于2020年7月29日周三 上午5:51写道：
>
> On Tue, Jul 28, 2020 at 12:08 PM Kevin Tang wrote:
> >
> > From: Kevin Tang
> >
> > Adds DPU(Display Processor Unit) support for the Unisoc's display subsystem.
> > It's support multi planes, scaler, rotation, PQ(Picture Quality) and more.
> >
> > RFC
The only usage of these is to assign their address to the fbops field in
the fb_info struct, which is a const pointer. Make them const to allow
the compiler to put them in read-only memory.
Signed-off-by: Rikard Falkeborn
---
drivers/gpu/drm/gma500/framebuffer.c | 6 +++---
1 file changed, 3
Add J721E wrapper for mhdp, which sets up the clock and data muxes.
Signed-off-by: Jyri Sarha
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Tomi Valkeinen
Reviewed-by: Laurent Pinchart
---
drivers/gpu/drm/bridge/cadence/Kconfig| 13
Hi,
I have an Asus Chromebook Tablet CT100PA, which I will refer to as
"dumo" from this point on, which is a specific variant of gru-scarlet.
As far as I am aware, all gru-scarlet are the same, except for the
display, and in turn the different scarlets with the innolux panel
are the same.
I do
On Sun, 2020-08-23 at 09:48 +0800, Chun-Kuang Hu wrote:
> Mediatek HDMI phy driver is moved from drivers/gpu/drm/mediatek to
> drivers/phy/mediatek, so add the new folder to the Mediatek DRM drivers'
> information.
>
> Signed-off-by: Chun-Kuang Hu
> Reviewed-by: Matthias Brugger
> ---
>
Fix kernel-doc warning in :
../include/linux/dma-buf.h:330: warning: Function parameter or member
'name_lock' not described in 'dma_buf'
Signed-off-by: Randy Dunlap
Cc: Sumit Semwal
Cc: Gustavo Padovan
Cc: Christian König
Cc: linux-me...@vger.kernel.org
Cc: dri-devel@lists.freedesktop.org
Add @cookie to dma_fence_end_signalling() to prevent kernel-doc
warning in drivers/dma-buf/dma-fence.c:
../drivers/dma-buf/dma-fence.c:291: warning: Function parameter or member
'cookie' not described in 'dma_fence_end_signalling'
Signed-off-by: Randy Dunlap
Cc: Sumit Semwal
Cc: Gustavo
Hi Sam,
Le sam. 29 août 2020 à 23:07, Sam Ravnborg a
écrit :
On Thu, Aug 27, 2020 at 01:44:03PM +0200, Paul Cercueil wrote:
of_graph_get_remote_node() requires of_node_put() to be called on
the
device_node pointer when it's no more in use.
Fixes: fc1acf317b01 ("drm/ingenic: Add support
On Sun, Aug 30, 2020 at 10:51:22AM +0200, Krzysztof Kozlowski wrote:
> Update the address of Maxime Ripard as one in @free-electrons.com does
> not work.
>
> Cc: Maxime Ripard
> Signed-off-by: Krzysztof Kozlowski
Acked-by: Maxime Ripard
Thanks!
Maxime
signature.asc
Description: PGP
Le dim. 30 août 2020 à 21:21, Ezequiel Garcia
a écrit :
Hi Paul,
On Thu, 27 Aug 2020 at 09:04, Paul Cercueil
wrote:
Even if support for the IPU was compiled in, we may run on a device
(e.g. the Qi LB60) where the IPU is not available, or simply with
an old
devicetree without the
From: Yuti Amonkar
Document the bindings used for the Cadence MHDP8546 DPI/DP bridge in
yaml format.
Signed-off-by: Yuti Amonkar
Signed-off-by: Swapnil Jakhade
Reviewed-by: Rob Herring
Reviewed-by: Laurent Pinchart
---
.../display/bridge/cdns,mhdp8546.yaml | 154 ++
On Sun, Aug 30, 2020 at 02:57:43PM +0200, Hans de Goede wrote:
> This commit removes a check where we would skip writing the ctrl register
> and then setting the update bit in case the ctrl register already contains
> the correct values.
>
> In a perfect world skipping the update should be fine
Dear all,
Here are the notes we took during the BoF.
I believe the meeting was super interesting.
Although it felt a bit short for the topic,
we left with a few interesting ideas.
Thanks everyone!
Ezequiel
---
LPC 2020 BoF: Negotiating DMA-BUF Heaps
Attendees:
* Brian Starkey
* Daniel Stone
This patch series adds new DRM bridge driver for Cadence MHDP8546 DPI/DP
bridge. The Cadence Display Port IP is also referred as MHDP (Mobile High
Definition Link, High-Definition Multimedia Interface, Display Port).
Cadence Display Port complies with VESA DisplayPort (DP) and embedded
Display
On Thu, 2020-08-20 at 16:08 +0100, Robin Murphy wrote:
> Now that arch/arm is wired up for default domains and iommu-dma,
> implement the corresponding driver-side support for groups and DMA
> domains to replace the shared mapping workaround.
>
> Signed-off-by: Robin Murphy
> ---
>
Hi Maxime,
On 7/9/20 2:41 AM, Maxime Ripard wrote:
> Hi everyone,
>
> Here's a (pretty long) series to introduce support in the VC4 DRM driver
> for the display pipeline found in the BCM2711 (and thus the RaspberryPi 4).
>
> The main differences are that there's two HDMI controllers and that
Hello Guido Günther,
The patch 72967d5616d3: "drm/panel: Add panel driver for the Mantix
MLAF057WE51-X DSI panel" from Aug 17, 2020, leads to the following
static checker warning:
drivers/gpu/drm/panel/panel-mantix-mlaf057we51.c:205 mantix_get_modes()
error: we previously assumed
Hi,
On 8/31/20 10:56 AM, Andy Shevchenko wrote:
On Sun, Aug 30, 2020 at 02:57:43PM +0200, Hans de Goede wrote:
This commit removes a check where we would skip writing the ctrl register
and then setting the update bit in case the ctrl register already contains
the correct values.
In a perfect
On Mon, Aug 31, 2020 at 02:30:52PM +0200, Sylwester Nawrocki wrote:
> On 29.08.2020 16:24, Krzysztof Kozlowski wrote:
> > Samsung Exynos SoCs use syscon for system registers so document its
> > compatibles.
> >
> > Signed-off-by: Krzysztof Kozlowski
> > ---
> >
On Mon, Aug 31, 2020 at 10:11:02AM +0200, Marek Szyprowski wrote:
> Hi Krzysztof,
>
> On 29.08.2020 19:25, Krzysztof Kozlowski wrote:
> > Commit 52005dece527 ("ARM: dts: Add assigned clock parents to CMU node
> > for exynos3250") added assigned clocks under Clock Management Unit to
> > fix hangs
Hi Krzysztof,
On 31.08.2020 10:19, Krzysztof Kozlowski wrote:
> On Mon, Aug 31, 2020 at 10:11:02AM +0200, Marek Szyprowski wrote:
>> On 29.08.2020 19:25, Krzysztof Kozlowski wrote:
>>> Commit 52005dece527 ("ARM: dts: Add assigned clock parents to CMU node
>>> for exynos3250") added assigned
' as documented in
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Swapnil-Jakhade/drm-Add-support-for-Cadence-MHDP8546-DPI-DP-bridge-and-J721E-wrapper/20200831-162549
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config
Hi Laurentiu,
On Fr, 2020-08-28 at 11:36 +0300, Laurentiu Palcu wrote:
> Hi Lucas,
>
> I was wondering about the plans to merge this series. Since not many
> people can test it properly due to lack of DCSS support in the upstream
> NWL driver (which I heard it's coming soon) and a completely
Hi Lucas, Sam,
On Mon, Aug 31, 2020 at 12:37:23PM +0200, Lucas Stach wrote:
> Hi Laurentiu,
>
> On Fr, 2020-08-28 at 11:36 +0300, Laurentiu Palcu wrote:
> > Hi Lucas,
> >
> > I was wondering about the plans to merge this series. Since not many
> > people can test it properly due to lack of DCSS
Hi,
On 8/31/20 1:10 PM, Thierry Reding wrote:
On Sun, Aug 30, 2020 at 02:57:42PM +0200, Hans de Goede wrote:
Before this commit a suspend + resume of the LPSS PWM controller
would result in the controller being reset to its defaults of
output-freq = clock/256, duty-cycle=100%, until someone
On 29.08.2020 16:24, Krzysztof Kozlowski wrote:
> Additional properties actually might appear (e.g. assigned-clocks) so
> use unevaluatedProperties to fix dtbs_check warnings like:
>
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dt.yaml:
> system-controller@105c:
>
Am 31.08.20 um 06:17 schrieb Randy Dunlap:
Add @cookie to dma_fence_end_signalling() to prevent kernel-doc
warning in drivers/dma-buf/dma-fence.c:
../drivers/dma-buf/dma-fence.c:291: warning: Function parameter or member
'cookie' not described in 'dma_fence_end_signalling'
Signed-off-by:
On Sun, Aug 30, 2020 at 02:57:41PM +0200, Hans de Goede wrote:
> In the not-enabled -> enabled path pwm_lpss_apply() needs to get a
> runtime-pm reference; and then on any errors it needs to release it
> again.
>
> This leads to somewhat hard to read code. This commit introduces a new
>
On 29.08.2020 19:25, Krzysztof Kozlowski wrote:
> The fixed clocks are kept under dedicated node fixed-rate-clocks, thus a
> fake "reg" was added. This is not correct with dtschema as fixed-clock
> binding does not have a "reg" property:
>
>arch/arm/boot/dts/exynos3250-artik5-eval.dt.yaml:
Hi Krzysztof,
On 29.08.2020 16:25, Krzysztof Kozlowski wrote:
> The USB-C connector bindings require port@0. Such port was already
> described in DTS but outside of the connector itself. Put it into
> proper place to fix dtbs_check warnings like:
>
>
On Fri, Aug 28, 2020 at 12:53:32PM +0300, Jani Nikula wrote:
> On Tue, 25 Aug 2020, Dan Carpenter wrote:
> > Hello Mathieu Malaterre,
> >
> > The patch e9c0c874711b: "drm/dp: annotate implicit fall throughs"
> > from Jan 14, 2019, leads to the following static checker warning:
> >
> >
Hi Philipp,
https://git-scm.com/docs/git-format-patch]
url:
https://github.com/0day-ci/linux/commits/Philipp-Zabel/drm-add-drmm_encoder_alloc/20200826-203629
base: git://anongit.freedesktop.org/drm-intel for-linux-next
config: x86_64-randconfig-m001-20200826 (attached as .config)
compiler:
On Sun, Aug 30, 2020 at 02:57:40PM +0200, Hans de Goede wrote:
> When the user requests a high enough period ns value, then the
> calculations in pwm_lpss_prepare() might result in a base_unit value of 0.
>
> But according to the data-sheet the way the PWM controller works is that
> each input
On Sun, Aug 30, 2020 at 02:57:39PM +0200, Hans de Goede wrote:
> According to the data-sheet the way the PWM controller works is that
> each input clock-cycle the base_unit gets added to a N bit counter and
> that counter overflowing determines the PWM output frequency.
>
> So assuming e.g. a 16
On Sun, Aug 30, 2020 at 02:57:46PM +0200, Hans de Goede wrote:
> The pwm-crc code is using 2 different enable bits:
> 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE)
> 2. bit 0 of the BACKLIGHT_EN register
>
> The BACKLIGHT_EN register at address 0x51 really controls a separate
> output-only
On Sun, Aug 30, 2020 at 02:57:47PM +0200, Hans de Goede wrote:
> The pwm-crc code is using 2 different enable bits:
> 1. bit 7 of the PWM0_CLK_DIV (PWM_OUTPUT_ENABLE)
> 2. bit 0 of the BACKLIGHT_EN register
>
> So far we've kept the PWM_OUTPUT_ENABLE bit set when disabling the PWM,
> this commit
On Sun, Aug 30, 2020 at 02:57:45PM +0200, Hans de Goede wrote:
> The CRC PWM controller has a clock-divider which divides the clock with
> a value between 1-128. But as can seen from the PWM_DIV_CLK_xxx
> defines, this range maps to a register value of 0-127.
>
> So after calculating the
On 29.08.2020 16:24, Krzysztof Kozlowski wrote:
> Additional properties or nodes actually might appear (e.g. operating
> points table) so use unevaluatedProperties to fix dtbs_check warnings
> like:
>
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dt.yaml: gpu@14ac:
> 'opp_table' does not
On 29.08.2020 16:24, Krzysztof Kozlowski wrote:
> Additional properties actually might appear (e.g. clocks) so use
> unevaluatedProperties to fix dtbs_check warnings like:
>
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dt.yaml: timer@101c:
> 'clock-names', 'clocks' do not match any of
On Sun, Aug 30, 2020 at 02:57:43PM +0200, Hans de Goede wrote:
> This commit removes a check where we would skip writing the ctrl register
> and then setting the update bit in case the ctrl register already contains
> the correct values.
>
> In a perfect world skipping the update should be fine
On Sun, Aug 30, 2020 at 02:57:44PM +0200, Hans de Goede wrote:
> While looking into adding atomic-pwm support to the pwm-crc driver I
> noticed something odd, there is a PWM_BASE_CLK define of 6 MHz and
> there is a clock-divider which divides this with a value between 1-128,
> and there are 256
On Sun, Aug 30, 2020 at 02:57:44PM +0200, Hans de Goede wrote:
> While looking into adding atomic-pwm support to the pwm-crc driver I
> noticed something odd, there is a PWM_BASE_CLK define of 6 MHz and
> there is a clock-divider which divides this with a value between 1-128,
> and there are 256
Hi,
On 8/31/20 1:13 PM, Thierry Reding wrote:
On Sun, Aug 30, 2020 at 02:57:43PM +0200, Hans de Goede wrote:
This commit removes a check where we would skip writing the ctrl register
and then setting the update bit in case the ctrl register already contains
the correct values.
In a perfect
On Saturday, August 29, 2020 4:06 PM, Sidong Yang wrote:
> Currently vkms module doesn't support gamma function for userspace. so igt
> subtests in kms_plane(pixel-format-pipe-A-plan) failed for calling
> drmModeCrtcSetGamma().
It doesn't seem like this IGT test's goal is to exercise support
Hello Linus Walleij,
The patch 5fc537bfd000: "drm/mcde: Add new driver for ST-Ericsson
MCDE" from May 24, 2019, leads to the following static checker
warning:
drivers/gpu/drm/mcde/mcde_display.c:570 mcde_configure_channel()
error: uninitialized symbol 'val'.
On 29.08.2020 16:24, Krzysztof Kozlowski wrote:
> Samsung Exynos SoCs use syscon for system registers so document its
> compatibles.
>
> Signed-off-by: Krzysztof Kozlowski
> ---
> Documentation/devicetree/bindings/mfd/syscon.yaml | 4
> 1 file changed, 4 insertions(+)
>
> diff --git
Hi James,
On Sun, Aug 23, 2020 at 03:53:50PM -0700, James Jones wrote:
> On 8/23/20 1:46 PM, Laurent Pinchart wrote:
> > On Sun, Aug 23, 2020 at 01:04:43PM -0700, James Jones wrote:
> >> On 8/20/20 1:15 AM, Ezequiel Garcia wrote:
> >>> On Mon, 2020-08-17 at 20:49 -0700, James Jones wrote:
>
https://bugzilla.kernel.org/show_bug.cgi?id=209091
Bug ID: 209091
Summary: i915: drm:fw_domains_get [i915] *ERROR* render: timed
out waiting for forcewake ack request.
Product: Drivers
Version: 2.5
Kernel Version: 5.8.5
From: Krishna Manikandan
[ Upstream commit 9d5cbf5fe46e350715389d89d0c350d83289a102 ]
Define shutdown callback for display drm driver,
so as to disable all the CRTCS when shutdown
notification is received by the driver.
This change will turn off the timing engine so
that no display
From: Rob Clark
[ Upstream commit 35c719da95c0d28560bff7bafeaf07ebb212665e ]
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c:817 dpu_crtc_enable() error:
uninitialized symbol 'request_bandwidth'.
Reported-by: kernel test robot
Signed-off-by: Rob Clark
Reviewed-by: Sean Paul
Signed-off-by: Rob
From: Krishna Manikandan
[ Upstream commit 9d5cbf5fe46e350715389d89d0c350d83289a102 ]
Define shutdown callback for display drm driver,
so as to disable all the CRTCS when shutdown
notification is received by the driver.
This change will turn off the timing engine so
that no display
From: Tomi Valkeinen
[ Upstream commit 7fd5b25499bcec157dd4de9a713425efcf4571cd ]
After commit 92cc68e35863c1c61c449efa2b2daef6e9926048 ("drm/vblank: Use
spin_(un)lock_irq() in drm_crtc_vblank_on()") omapdrm locking is broken:
WARNING: inconsistent lock state
5.8.0-rc2-00483-g92cc68e35863 #13
From: Rob Clark
[ Upstream commit 43906812eaab06423f56af5cca9a9fcdbb4ac454 ]
This has roughly the same effect as drm_atomic_helper_wait_for_vblanks(),
basically just ensuring that vblank accounting is enabled so that we get
valid timestamp/seqn on pageflip events.
Signed-off-by: Rob Clark
From: Jaehyun Chung
[ Upstream commit b61f05622ace5b9498ae279cdfd1c9f0c1ce3f75 ]
[Why]
Revert HDCP disable sequence change that blanks stream before
disabling HDCP. PSP and HW teams are currently investigating the
root cause of why HDCP cannot be disabled before stream blank,
which is expected
From: Furquan Shaikh
[ Upstream commit 5896585512e5156482335e902f7c7393b940da51 ]
In `amdgpu_dm_update_backlight_caps()`, there is a local
`amdgpu_dm_backlight_caps` object that is filled in by
`amdgpu_acpi_get_backlight_caps()`. However, this object is
uninitialized before the call and hence
From: Nicholas Kazlauskas
[ Upstream commit 168f09cdadbd547c2b202246ef9a8183da725f13 ]
[Why]
These aren't stable on some platform configurations when driving
multiple displays, especially on higher resolution.
In particular the delay in asserting p-state and validating from
x86 outweights any
From: Dmitry Baryshkov
[ Upstream commit f5749d6181fa7df5ae741788e5d96f593d3a60b6 ]
New Qualcomm firmware has changed a way it reports back the 'started'
event. Support new register values.
Signed-off-by: Dmitry Baryshkov
Signed-off-by: Rob Clark
Signed-off-by: Sasha Levin
---
From: Tong Zhang
[ Upstream commit ed9ab229fea24cbcab17f484297dc8344afb7ea9 ]
core_link_read_dpcd returns only DC_OK(1) and DC_ERROR_UNEXPECTED(-1),
the caller should check error using DC_OK instead of checking against 0
Signed-off-by: Tong Zhang
Signed-off-by: Alex Deucher
Signed-off-by:
From: Kalyan Thota
[ Upstream commit ccc862b957c6413b008fbe458034372847992d7f ]
In TEST_ONLY commit, rm global_state will duplicate the
object and request for new reservations, once they pass
then the new state will be swapped with the old and will
be available for the Atomic Commit.
This
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