On Mon, Jan 28, 2019 at 09:09:26PM +0800, Tan Xiaojun wrote:
> On 2019/1/28 19:54, Laszlo Ersek wrote:
> > On 01/28/19 11:46, Mark Rutland wrote:
> >> On Wed, Jan 23, 2019 at 10:54:56AM +0100, Laszlo Ersek wrote:
> >>> And even on the original (unspecified) h
On Wed, Jan 23, 2019 at 10:54:56AM +0100, Laszlo Ersek wrote:
> On 01/23/19 10:26, Ard Biesheuvel wrote:
> > On Wed, 23 Jan 2019 at 10:14, Laszlo Ersek wrote:
> >> On 01/22/19 16:37, Ard Biesheuvel wrote:
>
> >>> Is SetUefiImageMemoryAttributes() being
> >>> called to remap the memory R-X ?
> >>
On Wed, Jan 23, 2019 at 03:02:14PM +0100, Ard Biesheuvel wrote:
> On Wed, 23 Jan 2019 at 10:55, Laszlo Ersek wrote:
> >
> > On 01/23/19 10:26, Ard Biesheuvel wrote:
> > > On Wed, 23 Jan 2019 at 10:14, Laszlo Ersek wrote:
> > >> On 01/22/19 16:37, Ard Biesheuvel wrote:
> >
> > >>> Is
Hi,
On Wed, Mar 29, 2017 at 06:55:26PM +0200, Laszlo Ersek wrote:
> On 03/29/17 18:17, Ard Biesheuvel wrote:
> > On 29 March 2017 at 17:09, Jon Masters wrote:
> >> Thanks Laszlo. A quick note from me that regardless of this
> >> discussion I will be pushing to ensure the version
[Adding Marc Zyngier]
On Fri, Jan 20, 2017 at 02:20:43PM +, Ard Biesheuvel wrote:
> Users of ArmGenericTimerVirtCounterLib may execute under virtualization,
> which implies that they may be affected by core errata of the host.
>
> Some implementations of the ARM Generic Timer are affected by
er configure stage 2 translation in UEFI.
>
> Reported-by: Vishal Oliyil Kunnil <vish...@qti.qualcomm.com>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Apologies for this. FWIW:
Acked-by: Mark Rutl
iesheu...@linaro.org>
> ---
> ArmPkg/Drivers/CpuDxe/Exception.c | 9 +
> 1 file changed, 9 insertions(+)
These look sensible to me. FWIW, for both patches:
Acked-by: Mark Rutland <mark.rutl...@arm.com>
Mark.
>
> diff --git a/ArmPkg/Drivers/CpuDxe/Exception.c
>
On Mon, Jun 13, 2016 at 05:51:23PM +0200, Ard Biesheuvel wrote:
> On 13 June 2016 at 17:45, Mark Rutland <mark.rutl...@arm.com> wrote:
> > On Mon, Jun 13, 2016 at 05:26:07PM +0200, Ard Biesheuvel wrote:
> >> On some platforms, performing cache maintenance on regions tha
On Mon, Jun 13, 2016 at 05:26:07PM +0200, Ard Biesheuvel wrote:
> On some platforms, performing cache maintenance on regions that are backed
> by NOR flash result in SErrors. Since cache maintenance is unnecessary in
> that case, create a PEIM specific version that only performs said cache
>
On Wed, May 11, 2016 at 12:23:58PM +0200, Ard Biesheuvel wrote:
> On 11 May 2016 at 12:22, Mark Rutland <mark.rutl...@arm.com> wrote:
> > On Wed, May 11, 2016 at 12:07:51PM +0200, Ard Biesheuvel wrote:
> >> On 11 May 2016 at 11:35, Achin Gupta <achin.gu...@arm.com
On Wed, May 11, 2016 at 12:07:51PM +0200, Ard Biesheuvel wrote:
> On 11 May 2016 at 11:35, Achin Gupta wrote:
> >> diff --git
> >> a/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
> >> b/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
> >>
On Mon, May 09, 2016 at 07:02:16PM +0100, Ryan Harkin wrote:
> On 9 May 2016 at 11:07, Ryan Harkin <ryan.har...@linaro.org> wrote:
> > On 9 May 2016 at 10:22, Mark Rutland <mark.rutl...@arm.com> wrote:
> >> On Sat, May 07, 2016 at 10:43:45AM +0200, Ard Biesheuvel wr
On Sat, May 07, 2016 at 10:43:45AM +0200, Ard Biesheuvel wrote:
> On 6 May 2016 at 19:19, Mark Rutland <mark.rutl...@arm.com> wrote:
> > The LAN9118 driver uses memory fences in a novel but erroneous fashion, due
> > to
> > a misunderstanding of some under-commen
ndholm <leif.lindh...@linaro.org>
Cc: Ryan Harkin <ryan.har...@linaro.org>
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
---
EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c | 5 -
EmbeddedPkg/Drivers/Lan9118D
in <ryan.har...@linaro.org>
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
---
EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.c | 78 +++---
EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h | 4 +-
Embedd
ndholm <leif.lindh...@linaro.org>
Cc: Ryan Harkin <ryan.har...@linaro.org>
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Contributed-under: TianoCore Contribution Agreement 1.0
---
EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118DxeHw.h | 71 +
EmbeddedPkg/Drivers/Lan
this in a more
consistent fashion.
The LAN9118 datasheet is publicly available at:
http://www.microchip.com/wwwproducts/en/LAN9118
Thanks,
Mark.
Mark Rutland (4):
Revert "EmbeddedPkg/Lan9118Dxe: use MemoryFence"
EmbeddedPkg/Lan9118Dxe: add LAN9118 MMIO wrappers
EmbeddedPkg/Lan91
converting these
stalls to memory fences was erroneous, and may result in stale values
being read.
This reverts commit a4626006bbf86113453aeb7920895e66cdd04737.
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Ryan Harkin <ryan.har...@linaro
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Acked-by: Mark Rutland <mark.rutl...@arm.com>
Mark.
> ---
> ArmPkg/Include/Library/ArmLib.h | 6 ++
> ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf | 5 +-
> ArmPkg/Library/ArmLib/AA
On Thu, Apr 14, 2016 at 01:36:00PM +0200, Ard Biesheuvel wrote:
> On 14 April 2016 at 13:17, Mark Rutland <mark.rutl...@arm.com> wrote:
> > On Tue, Apr 12, 2016 at 08:57:46AM +0200, Ard Biesheuvel wrote:
> > I take it that ArmReplaceLiveTranslationEntry isn't part of the
On Tue, Apr 12, 2016 at 08:57:46AM +0200, Ard Biesheuvel wrote:
> On ARM, manipulating live page tables is cumbersome since the architecture
> mandates the use of break-before-make, i.e., replacing a block entry with
> a table entry requires an intermediate step via an invalid entry, or TLB
>
On Mon, Apr 11, 2016 at 06:50:06PM +0200, Ard Biesheuvel wrote:
> On 11 April 2016 at 18:47, Mark Rutland <mark.rutl...@arm.com> wrote:
> > On Mon, Apr 11, 2016 at 06:08:29PM +0200, Ard Biesheuvel wrote:
> >> +//VOID
> >> +//ArmReplaceLiveTranslationEnt
On Mon, Apr 11, 2016 at 06:08:29PM +0200, Ard Biesheuvel wrote:
> +//VOID
> +//ArmReplaceLiveTranslationEntry (
> +// IN UINT64 *Entry,
> +// IN UINT64 Value
> +// )
> +ASM_PFX(ArmReplaceLiveTranslationEntry):
> + .macro __replace_entry, el
> + mrs x8, sctlr_el\el
> + and x9, x8,
Hi Ard,
On Mon, Apr 11, 2016 at 03:57:15PM +0200, Ard Biesheuvel wrote:
> On ARM, manipulating live page tables is cumbersome since the architecture
> mandates the use of break-before-make, i.e., replacing a block entry with
> a table entry requires an intermediate step via an invalid entry, or
On Wed, Dec 16, 2015 at 12:24:30PM +0100, Ard Biesheuvel wrote:
> On 16 December 2015 at 12:18, Mark Rutland <mark.rutl...@arm.com> wrote:
> > On Wed, Dec 16, 2015 at 10:37:39AM +0100, Ard Biesheuvel wrote:
> >> diff --git a/ArmPkg/Include/Chipset/AArch64.h
> >> b
On Wed, Dec 16, 2015 at 10:37:39AM +0100, Ard Biesheuvel wrote:
> Unfortunately, Clang does not support the use of symbol references in .org
> directives, and bails with the following error message when it encounters
> them:
>
> <...>:error: expected assembly-time absolute expression
> .org
On Thu, Nov 26, 2015 at 04:06:40PM +0100, Ard Biesheuvel wrote:
> On 20 November 2015 at 13:46, Mark Rutland <mark.rutl...@arm.com> wrote:
> > On Fri, Nov 20, 2015 at 01:39:26PM +0100, Ard Biesheuvel wrote:
> >> The PrePeiCore vector table for AArch64 mode is only half
on Agreement 1.0
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Acked-by: Mark Rutland <mark.rutl...@arm.com>
Mark.
> ---
> ArmPlatformPkg/PrePeiCore/AArch64/Exception.S | 40
> 1 file changed, 40 insertions(+)
>
> diff --git a/ArmPlatfo
ed-off-by: Leif Lindholm <leif.lindh...@linaro.org>
Looks sensible to me. FWIW:
Acked-by: Mark Rutland <mark.rutl...@arm.com>
Mark.
> ---
> ArmPkg/Include/Library/ArmLib.h| 6 --
> ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 8
> ArmPkg/Libr
On Thu, Nov 19, 2015 at 03:42:51PM +0100, Ard Biesheuvel wrote:
> On 19 November 2015 at 14:44, Mark Rutland <mark.rutl...@arm.com> wrote:
> > We currently rely on .align directives to ensure that each exception
> > vector entry is the appropriate offset from th
the
DebugAgentVectorTable symbol.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
---
ArmPkg/Library/DebugAgentSymbolsBaseLib/AArch64/DebugAg
> > Is the SError taken directly to EL2? I understood from your previous
> > reply that the EDK2 exception handler was invoked at this point, so is
> > there anything at EL3 which is trying to catch exceptions and then
> > re-inject them down to EL2?
> None that I would be aware of.
Ok.
> > The
On Mon, Nov 16, 2015 at 06:23:20PM +, Vladimir Olovyannikov wrote:
> > -Original Message-
> > From: Mark Rutland [mailto:mark.rutl...@arm.com]
[...]
> > What is the earliest point in EDK2 that you have unmasked SError?
> >
> > Are you doing this in Pr
ent: Monday, November 16, 2015 10:28 AM
> >> To: Vladimir Olovyannikov
> >> Cc: Mark Rutland; edk2-devel@lists.01.org
> >> Subject: Re: [edk2] Armv8 64bit: System error booting linux from the UEFI
> >>
> > [...]
> >> >
> >> > Async abort
On Fri, Nov 13, 2015 at 10:39:34PM +, Vladimir Olovyannikov wrote:
>
>
> > -Original Message-
> > From: Ard Biesheuvel [mailto:ard.biesheu...@linaro.org]
> > Sent: Friday, November 13, 2015 3:00 AM
> > To: Vladimir Olovyannikov
> > Cc: edk2-devel@lists.01.org
> > Subject: Re: Armv8
On Thu, Nov 12, 2015 at 11:35:28AM +, Leif Lindholm wrote:
> Hi Ard,
>
> On Mon, Nov 09, 2015 at 02:18:58PM +0100, Ard Biesheuvel wrote:
> > Mark all cached memory mappings as shareable (or inner shareable on
> > AArch64) so that our view of memory is kept coherent by the hardware.
> >
> >
I've been trying to test an EFI application on x86_64 using Ubuntu 14.04's QEMU
2.0.0. I have a directory 'foo' containing the application, and I get QEMU to
create a virtual FAT device:
$ qemu-system-x86_64 -nographic \
-bios src/edk2/Build/OvmfX64/RELEASE_GCC48/FV/OVMF.fd \
-hda
djacent data if the cache writeback granularity exceeds
> the cache linesize.
>
> Reported-by: Mark Rutland <mark.rutl...@arm.com>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
> ---
> ArmPkg/L
KB, no?
The ARM ARM says the architectural maximum is 512 /words/ (i.e. 2KB).
With those changes:
Reviewed-by: Mark Rutland <mark.rutl...@arm.com>
Thanks,
Mark.
> +
> + return 4 << CWG;
> +}
> --
> 1.9.1
>
___
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On Wed, Nov 04, 2015 at 12:17:16PM +, Cohen, Eugene wrote:
> > The set/way operations are really only suitable for managing the caches
> > themselves
>
> This makes sense to me and I agree that the majority of developers
> should only be dealing with managing buffers and should only use the
On Wed, Nov 04, 2015 at 04:24:20PM +0100, Laszlo Ersek wrote:
> On 11/04/15 16:19, Ard Biesheuvel wrote:
[...]
> > The problem remains that VA and set/way ops are completely different
> > things. Each by-VA operation handles all copies of the same cacheline
> > throughout the cache hierarchy at
declaration and all definitions.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel <ard.biesheu...@linaro.org>
Acked-by: Mark Rutland <mark.rutl...@arm.com>
Mark.
> ---
> ArmPkg/Include/Library/ArmLib.h|
struction cache
>ArmInvalidateInstructionCache ();
>// Enable Instruction Caches on all cores.
I'm not sure the I-cache maintenance is necessary either, given that
we're already executing code that must have been fetched into the
I-cache, but that really depends on what EDK's requirements
he above, this is most definitely an improvement.
Reviewed-by: Mark Rutland <mark.rutl...@arm.com>
Mark.
> ---
> ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c | 25 --
> ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.c | 27
> ArmPkg/Library/ArmLib
On Tue, Nov 03, 2015 at 01:51:46PM +, Cohen, Eugene wrote:
> Please don't remove this functionality. At times we do want to use
> this library to turn off the cache in preparation for going to another
> environment (say, loading an OS) and this is useful.
Could you elaborate on your
requisite DSB; ISB sequence, so we didn't actually need
to introduce an ISB here.
I don't know if it's best to remove the ISB here, or move both the DSB
and ISB here for consistency across all the cache maintenance
primitives.
Either way, with that fixed up:
Reviewed-by: Mark Rutland <mark.rutl.
Hi Ard,
On Mon, Nov 02, 2015 at 02:24:18PM +0100, Ard Biesheuvel wrote:
> There is no need to issue a full data synchronization barrier and an
> instruction synchronization barrier after each and every set/way or
> MVA cache maintenance operation. So remove them.
So long as the loops calling
].
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Laszlo Ersek <ler...@redhat.com>
Cc: Leif Lindholm <leif.lindh...@linaro.org>
---
ArmVirtPkg/ArmVirt.dsc.inc | 8
On Fri, Oct 16, 2015 at 12:48:37PM +0200, Laszlo Ersek wrote:
> On 10/16/15 12:15, Mark Rutland wrote:
> > Some AArch64 toolchains also invoke the software stack checker
> > functions on certain code - so include BaseStackCheckLib for
> > AARCH64 as well as for ARM. Si
[LibraryClasses.common].
At the same time, fix the grammar for the related comments.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Mark Rutland <mark.rutl...@arm.com>
Cc: Ard Biesheuvel <ard.biesheu...@linaro.org>
Cc: Laszlo Ersek <ler...@redhat.com>
Cc: Leif Li
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