On Tue, 2015-08-18 at 10:45 +0200, Ard Biesheuvel wrote:
On 18 August 2015 at 10:39, Haojian Zhuang haojian.zhu...@linaro.org wrote:
// All bits low except one bit high, restricted to 8 bits
// (i.e. ensures zeros above 8bits)
But '' is wrong at here. It'll only return 1 or 0
.
* Support multiple PL061 gpio controllers in one platform.
v2:
* Append the patch to fix gpio pin mask macro.
Haojian Zhuang (3):
ArmPlatformPkg: PL061: fix accessing GPIO DATA
EmbeddedPkg: enhance for multiple gpio controllers
ArmPlatformPkg: PL061: support multiple controller
Support multiple PL061 controllers.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c| 107 ++---
.../Drivers/PL061GpioDxe/PL061GpioDxe.inf | 3
EmbeddedGpio only supports one gpio controller in one platform. Now create
PLATFORM_GPIO_CONTROLLER to support multiple gpio controllers in one platform.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
EmbeddedPkg
-by: Haojian Zhuang haojian.zhu...@linaro.org
---
ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c| 137 +++--
.../Drivers/PL061GpioDxe/PL061GpioDxe.inf | 1 +
ArmPlatformPkg/Include/Drivers/PL061Gpio.h | 47 ---
3 files changed, 125 insertions(+), 60
EmbeddedGpio only supports one gpio controller in one platform. Now create
PLATFORM_GPIO_CONTROLLER to support multiple gpio controllers in one platform.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
EmbeddedPkg
controllers in one platform.
v2:
* Append the patch to fix gpio pin mask macro.
Haojian Zhuang (3):
ArmPlatformPkg: PL061: fix accessing GPIO DATA
EmbeddedPkg: enhance for multiple gpio controllers
ArmPlatformPkg: PL061: support multiple controller
ArmPlatformPkg/Drivers/PL061GpioDxe
of this message until overflow.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
ArmPlatformPkg/Bds/Bds.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/ArmPlatformPkg/Bds/Bds.c b/ArmPlatformPkg/Bds/Bds.c
to be read as 0, regardless of their value.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/ArmPlatformPkg
On Tue, 2015-08-11 at 09:42 +0200, Ard Biesheuvel wrote:
On 11 August 2015 at 09:11, Haojian Zhuang haojian.zhu...@linaro.org wrote:
The way of accessing PL061 GPIODATA register is wrong.
The spec said in below.
In order to write to GPIODATA, the corresponding bits in the mask
to be read as 0, regardless of their value.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang haojian.zhu...@linaro.org
---
ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/ArmPlatformPkg
Haojian
Thanks for the sharing.
May I know if you have validated variable set in UEFI runtime?
I found it is marked as DXE driver instead of RUNTIME driver. But maybe I am
wrong.
Thank you
Yao Jiewen
-Original Message-
From: Haojian Zhuang [mailto:haojian.zhu...@linaro.org
On 11 November 2015 at 08:20, Vladimir Olovyannikov
wrote:
> Hello,
>
> I am not sure this is the right forum to ask this question, so I am sorry in
> advance if this is an offtopic here (please point me to the proper one).
>
> I brought up UEFI on the device and am trying
BdsConnectAndUpdateDevicePath() won't set right handle if device path
is file path or memory mapped. Now try to tranverse all handles for
FvFile in Fv.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
ArmPkg/Library/
in file system.
Now check the device path first. If it's not file path in file system,
return directly.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
ArmPkg/Library/BdsLib/BdsFilePath.c | 8 +---
1 file changed, 5 inse
Fix to load Fv file from UEFI image.
Haojian Zhuang (2):
ArmPkg: Bds: check path first for supporting fs
ArmPkg: Bds: tranverse handles for fv file
ArmPkg/Library/BdsLib/BdsFilePath.c | 143
1 file changed, 80 insertions(+), 63 deletions(-)
--
1.9.1
在 02/10/2016 11:55 PM, Leif Lindholm 写道:
Apologies to Haojian for not giving any feedback on his set of
significant improvements to the pl061 GPIO controller driver.
I found myself unable to review his modifications due to the complexity
of the original driver, so I decided to refactor it ...
Make use of DMA to transfer multiple blocks at one time. It could
improve the performance on MMC/SD driver.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Include/Protocol/MmcHost.h| 6 +
Embed
When SD card is used, mediaid is not initialized and used directly. So
fix it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 7 ++-
1 file changed, 6 insertions
Since there's percentage calcution, multiply on 32bit variable
will cause overflow. So fix the variables as 64bit.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Zhangfei Gao <zhangfei@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhu...@l
Support both manufacturer and product string descriptors. Otherwise,
the manufacturer and product sub nodes won't be created in sysfs
directory of linux host.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
.../D
Set the right value of Manufacturer, Product and SerialNumber
in usb string descriptor.
Haojian Zhuang (2):
EmbeddedPkg: FastbootUsb: set serial number as 3
EmbeddedPkg: FastbootUsb: add string descriptors
.../Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsb.c | 6 +++---
1
Set serial number as 3. If the serial number is 0, fastboot won't
load real serial number from descriptor at all.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
.../Drivers/AndroidFastbootTransport
Riku Voipio <riku.voi...@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
.../ArmVExpressFastBootDxe/ArmVExpressFastBoot.c | 58 --
.../Include/Protocol/AndroidFastbootPlatform.h | 26 ++
2 files changed, 81 insertions(+), 3 deletion
On 2016/2/27 4:38, Leif Lindholm wrote:
Hi Haojian,
On Fri, Feb 26, 2016 at 05:27:47PM +0800, Haojian Zhuang wrote:
* Wait OCR busy bit free according to eMMC spec.
* Define ECSD structure.
* Add interface to set IO bus width and speed.
* Support to access multiple blocks
On 01/15/2016 10:29 AM, Haojian Zhuang wrote:
BdsFileSystemSupport() checks Handle first before validating device
path of file. There's the potential issue at here.
BdsConnectAndUpdateDevicePath() will skip to locate handle if it's
file or memory mapped. Then BdsFileSystemSupport() tries
-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
ArmPlatformPkg/Drivers/PL061GpioDxe/PL061Gpio.c| 141 -
.../Drivers/PL061GpioDxe/PL061GpioDxe.inf | 1 +
ArmPlatformPkg/Include/Drivers/PL061Gpio.h | 46 ---
3 files changed, 129 insertions(
EmbeddedGpio only supports one gpio controller in one platform. Now
create PLATFORM_GPIO_CONTROLLER to support multiple gpio controllers
in one platform.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
Embed
structure in embedded gpio.
* Support multiple PL061 gpio controllers in one platform.
v2:
* Append the patch to fix gpio pin mask macro.
Haojian Zhuang (2):
EmbeddedPkg: enhance for multiple gpio controllers
ArmPlatformPkg: PL061: support multiple controller
ArmPlatformPkg/Drivers
在 03/14/2016 09:19 PM, Leif Lindholm 写道:
On Mon, Mar 14, 2016 at 01:30:37PM +0800, Haojian Zhuang wrote:
Support multiple PL061 controllers. If platform gpio driver couldn't be
found, PL061 gpio driver will continue to load PcdPL061GpioBase as the
register base.
It could be compatible
Add more SD commands to support 4-bit bus width & iospeed. It's not
formal code. And it needs to be updated later.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Include/Protocol/MmcHost.h
Make use of DMA to transfer multiple blocks at one time. It could
improve the performance on MMC/SD driver.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Include/Protocol/MmcHost.h| 6 +
Embed
According to eMMC spec, OCR.PowerUp bit is also busy bit. If the busy
bit is '0', CMD1 should be sent and OCR should be fetched again. And add
a timeout counter on the repeated steps.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.
By default, MMC is initialized with 1-bit mode and less than 400KHz bus
clock. It causes MMC working inefficiently.
Add the interface to change the bus width and speed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.
Set io bus width on both MMC controller and EXTCSD. Otherwise, it may
cause unmatched failure case. And support more timing mode, high speed,
HS200 & HS400 mode.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
E
Declare fields in ECSD structure. And drop the original 128 words
arrary.
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Universal/MmcDxe/Mmc.h | 157 ++-
EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 4 +-
2 files change
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Universal/MmcDxe/Mmc.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/EmbeddedPkg/Universal/MmcDxe/Mmc.h
b/EmbeddedPkg/Universal/MmcDxe
Since ECSD also describes the information of card, move it into
structure CardInfo.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Universal/MmcDxe/Mmc.h | 1 +
EmbeddedPkg/Universal/
When SD card is used, mediaid is not initialized and used directly. So
fix it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 7 ++-
1 file changed, 6 insertions
bus width and speed.
* Support to access multiple blocks.
Haojian Zhuang (9):
MmcDxe: wait OCR busy bit free
MmcDxe: move ECSD into CardInfo structure
MmcDxe: add SPEC_VERS field in CSD structure
MmcDxe: add interface to change io width and speed
MmcDxe: declare ECSD structure
MmcDxe
On 5 April 2016 at 02:54, Ard Biesheuvel wrote:
> On 4 April 2016 at 19:17, Ryan Harkin wrote:
>> Hi Haojian,
>>
>> I've had time to investigate where TC2 is hanging with your patches
>> applied and narrowed it down to the single line of code
On 5 April 2016 at 11:25, Tian, Feng wrote:
> Hi, HaoJian
>
> We newly added EDKII SD/MMC stack to EDKII repo. If the SD/MMC host
> controller follows SD PCI host controller spec, the whole stack should work.
>
> But looks like PL180 doesn't follow the SD PCI host controller
On 5 April 2016 at 17:49, Ryan Harkin <ryan.har...@linaro.org> wrote:
> On 5 April 2016 at 09:37, Ryan Harkin <ryan.har...@linaro.org> wrote:
>> On 5 April 2016 at 03:57, Haojian Zhuang <haojian.zhu...@linaro.org> wrote:
>>> On 5 April 2016 at 01:17, Ryan H
, You would have to have an
override version as it doesn't follow SD/MMC specs.
Thanks
Feng
-Original Message-
From: edk2-devel [mailto:edk2-devel-boun...@lists.01.org] On Behalf Of Haojian
Zhuang
Sent: Thursday, July 21, 2016 9:40 PM
To: Ard Biesheuvel <ard.biesheu...@linaro.org>; C
-Original Message-
From: af...@apple.com [mailto:af...@apple.com]
Sent: Thursday, July 21, 2016 12:04 PM
To: Haojian Zhuang <haojian.zhu...@linaro.org>
Cc: Tian, Feng <feng.t...@intel.com>; edk2-devel@lists.01.org; Leif Lindholm
<leif.lindh...@linaro.org>; Ard Biesh
On 2016/7/21 19:27, Ard Biesheuvel wrote:
On 20 July 2016 at 07:44, Michael Zimmermann wrote:
Hi,
since commit '5db1cce ArmPkg ArmVirtPkg MdeModulePkg: switch to separate
ArmMmuLib' you need to add ArmMmuLib to your platform's dsc file:
On 2016/7/21 19:27, Ard Biesheuvel wrote:
On 20 July 2016 at 07:44, Michael Zimmermann wrote:
Hi,
since commit '5db1cce ArmPkg ArmVirtPkg MdeModulePkg: switch to separate
ArmMmuLib' you need to add ArmMmuLib to your platform's dsc file:
C partition. So BlockVariableDxe is created to access
variables on block devices.
Thanks
Feng
-Original Message-
From: Haojian Zhuang [mailto:haojian.zhu...@linaro.org]
Sent: Thursday, July 21, 2016 10:34 AM
To: Tian, Feng <feng.t...@intel.com>
Cc: Leif Lindholm <leif.lindh...@
Hi all,
I have a few questions on eMMC/SD driver when I'm working on my driver.
In my hikey platform, there's no PCI bus. So I create my own DwMmc
driver to do the same thing as SdMmcPciHcDxe driver. There's one
controller for eMMC and one controller for SD.
1. How to support both eMMC and
在 07/21/2016 11:23 AM, Tian, Feng 写道:
Hi, Haojian
If there is no PCI bus, you could implement a fake one. Just like what we did
at edk2\Omap35xxPkg\PciEmulation. Through this way, you can reuse SdMmcPciHc
driver.
Oh, your eMMC/SD IP is compatible SDHC. But Designware eMMC/SD IP isn't
On 2016/7/21 19:24, Ard Biesheuvel wrote:
On 21 July 2016 at 13:17, Haojian Zhuang <haojian.zhu...@linaro.org> wrote:
On 2016/7/21 9:52, Haojian Zhuang wrote:
在 07/21/2016 09:51 AM, Haojian Zhuang 写道:
Hi Feng,
I think the main difference is who to handle the CRC bits. In the
desi
On 2016/7/21 9:52, Haojian Zhuang wrote:
在 07/21/2016 09:51 AM, Haojian Zhuang 写道:
Hi Feng,
I think the main difference is who to handle the CRC bits. In the
designware emmc/sd controller, the whole 128-bit value is loaded into
the four response registers. There's no any shift on the 128-bit
The CSD structure is a 128-bit structure. But EmmcGetCsd() only loads
120 bits with 8-bit offset. Now fix it.
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
MdeModulePkg/Bus/Sd/EmmcDxe/EmmcBlockIo.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
PL061_GPIO_DATA_REG offset is referenced in PL061EffectiveAddress ()
already. So remove the duplicated reference when invoke PL061GetPins ()
or PL061SetPins ().
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
ArmPlatf
On 13 February 2017 at 15:53, Haojian Zhuang <haojian.zhu...@linaro.org> wrote:
> When call PL061GetPins() or PL061SetPins(), should use GPIO_PIN_MASK(offset)
> as parameter, not offset.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Haojia
On 13 February 2017 at 15:52, Haojian Zhuang <haojian.zhu...@linaro.org> wrote:
> PL061_GPIO_DATA_REG offset is referenced in PL061EffectiveAddress ()
> already. So remove the duplicated reference when invoke PL061GetPins ()
> or PL061SetPins ().
>
> Contributed-under: T
The OCS value should be initiliazed as 0x0F according to UFS spec.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
Reviewed-by: Feng Tian <feng.t...@intel.com>
---
MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsPassThruHci
The OCS value should be initiliazed as 0x0F according to UFS spec.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
MdeModulePkg/Bus/Ufs/UfsBlockIoPei/UfsHci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MdeMod
When UPIU packet is sent, (BIT0 << Slot) should be set according
to context. But BIT0 is used without Slot when UfsWaitMemSet ()
is invoked.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
MdeModulePkg/Bus/Ufs/U
When UPIU packet is sent, (BIT0 << Slot) should be set according
to context. But BIT0 is used without Slot when UfsWaitMemSet ()
is invoked.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
Reviewed-by: Feng
v2:
1. Drop unnecessary patches.
2. Append fixes on UfsBlockIoPei driver.
v1:
1. Fix issues in UFS driver.
2. Add PhyInit in UFS driver.
3. Add retry in ScsiDisk for UFS device.
Haojian Zhuang (5):
MdeModuelPkg/UfsPassThruDxe: fix to identify 32 bits address mode
MdeModulePkg
When UFS_HC_CAP_64ADDR bit is set, it means 64-bit address,
not 32-bit address.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
Reviewed-by: Feng Tian <feng.t...@intel.com>
---
MdeModulePkg/Bus/Ufs/UfsPassThruDxe/UfsP
Declare fields in ECSD structure. And drop the original 128 words
arrary.
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Universal/MmcDxe/Mmc.h | 157 ++-
EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 4 +-
2 files change
By default, MMC is initialized with 1-bit mode and less than 400KHz bus
clock. It causes MMC working inefficiently.
Add the interface to change the bus width and speed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.
According to eMMC spec, OCR.PowerUp bit is also busy bit. If the busy
bit is '0', CMD1 should be sent and OCR should be fetched again. And add
a timeout counter on the repeated steps.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.
Since ECSD also describes the information of card, move it into
structure CardInfo.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Universal/MmcDxe/Mmc.h | 1 +
EmbeddedPkg/Universal/
spec.
* Define ECSD structure.
* Add interface to set IO bus width and speed.
* Support to access multiple blocks.
Haojian Zhuang (10):
MmcDxe: wait OCR busy bit free
MmcDxe: move ECSD into CardInfo structure
MmcDxe: add SPEC_VERS field in CSD structure
MmcDxe: add interface to chang
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Universal/MmcDxe/Mmc.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/EmbeddedPkg/Universal/MmcDxe/Mmc.h
b/EmbeddedPkg/Universal/MmcDxe
Set io bus width on both MMC controller and EXTCSD. Otherwise, it may
cause unmatched failure case. And support more timing mode, high speed,
HS200 & HS400 mode.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
E
Make use of DMA to transfer multiple blocks at one time. It could
improve the performance on MMC/SD driver.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Include/Protocol/MmcHost.h| 6 +
Embed
When CMD6 & ACMD51 are added into indentifying SD process, PL180
should also support CMD6 & ACMD51. Otherwise, it'll hang when
system tries to read expected data.
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c | 15
When SD card is used, mediaid is not initialized and used directly. So
fix it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 7 ++-
1 file changed, 6 insertions
Add more SD commands to support 4-bit bus width & iospeed. It's not
formal code. And it needs to be updated later.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Include/Protocol/MmcHost.h
On 8 November 2016 at 22:58, Leif Lindholm <leif.lindh...@linaro.org> wrote:
> On Tue, Nov 08, 2016 at 12:37:12PM +, Ryan Harkin wrote:
>> Hi Haojian,
>>
>> On 7 November 2016 at 15:49, Haojian Zhuang <haojian.zhu...@linaro.org>
>> wrote:
>> >
When CMD6 & ACMD51 are added into indentifying SD process, PL180
should also support CMD6 & ACMD51. Otherwise, it'll hang when
system tries to read expected data.
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c | 15
Add more SD commands to support 4-bit bus width & iospeed. It's not
formal code. And it needs to be updated later.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Include/Protocol/MmcHost.h
According to eMMC spec, OCR.PowerUp bit is also busy bit. If the busy
bit is '0', CMD1 should be sent and OCR should be fetched again. And add
a timeout counter on the repeated steps.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.
Since ECSD also describes the information of card, move it into
structure CardInfo.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Universal/MmcDxe/Mmc.h | 1 +
EmbeddedPkg/Universal/
Declare fields in ECSD structure. And drop the original 128 words
arrary.
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Universal/MmcDxe/Mmc.h | 157 ++-
EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 4 +-
2 files change
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Universal/MmcDxe/Mmc.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/EmbeddedPkg/Universal/MmcDxe/Mmc.h
b/EmbeddedPkg/Universal/MmcDxe
By default, MMC is initialized with 1-bit mode and less than 400KHz bus
clock. It causes MMC working inefficiently.
Add the interface to change the bus width and speed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.
Set io bus width on both MMC controller and EXTCSD. Otherwise, it may
cause unmatched failure case. And support more timing mode, high speed,
HS200 & HS400 mode.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
E
When SD card is used, mediaid is not initialized and used directly. So
fix it.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c | 7 ++-
1 file changed, 6 insertions
Since CMD6 & ACMD51 needs to read data size less than 512, proper
variable length should be set.
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
Tested-by: Ryan Harkin <ryan.har...@linaro.org>
---
ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c | 14 --
1
On 9 November 2016 at 01:32, Ryan Harkin <ryan.har...@linaro.org> wrote:
> Hi Haojian,
>
> I've tested your v4 series.
>
> On 8 November 2016 at 15:21, Haojian Zhuang <haojian.zhu...@linaro.org> wrote:
>> v4:
>> * Fix PL180 hang in some cases. Since the
On 9 November 2016 at 04:43, Leif Lindholm <leif.lindh...@linaro.org> wrote:
> On Tue, Nov 08, 2016 at 11:21:10PM +0800, Haojian Zhuang wrote:
>> Declare fields in ECSD structure. And drop the original 128 words
>> arrary.
>
> Functionality-wise, I'm happy with this,
Since CMD6 & ACMD51 needs to read data size less than 512, proper
variable length should be set.
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
---
ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
Make use of DMA to transfer multiple blocks at one time. It could
improve the performance on MMC/SD driver.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
Tested-by: Ryan Harkin <ryan.har...@linaro.org>
---
Embedde
When CMD6 & ACMD51 are added into indentifying SD process, PL180
should also support CMD6 & ACMD51. Otherwise, it'll hang when
system tries to read expected data.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
T
Add more SD commands to support 4-bit bus width & iospeed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
Tested-by: Ryan Harkin <ryan.har...@linaro.org>
---
EmbeddedPkg/Include/Protocol/MmcHost.h |
to send ACMD51.
v1:
* Wait OCR busy bit free according to eMMC spec.
* Define ECSD structure.
* Add interface to set IO bus width and speed.
* Support to access multiple blocks.
Haojian Zhuang (4):
MmcDxe: add interface to change io width and speed
MmcDxe: set iospeed and bus wid
mode, high speed,
HS200 & HS400 mode.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
Tested-by: Ryan Harkin <ryan.har...@linaro.org>
---
EmbeddedPkg/Include/Protocol/MmcHost.h | 25 ++-
EmbeddedPkg/Univer
When CMD6 & ACMD51 are added into indentifying SD process, PL180
should also support CMD6 & ACMD51. Otherwise, it'll hang when
system tries to read expected data.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
Re
. And support more timing mode, high speed,
HS200 & HS400 mode.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
Tested-by: Ryan Harkin <ryan.har...@linaro.org>
---
EmbeddedPkg/Include/Protocol/MmcHost.h | 31 +
us width and speed.
* Support to access multiple blocks.
Haojian Zhuang (4):
MmcDxe: add interface in mmc host protocol
MmcDxe: set iospeed and bus width in SD stack
PL180: update for indentifying SD
MmcDxe: expand to support multiple blocks
ArmPlatformPkg/Drivers/PL180MciDxe/PL180Mci.c
Add more SD commands to support 4-bit bus width & iospeed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
Tested-by: Ryan Harkin <ryan.har...@linaro.org>
---
EmbeddedPkg/Include/Protocol/MmcHost.h |
Make use of DMA to transfer multiple blocks at one time. It could
improve the performance on MMC/SD driver.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
Tested-by: Ryan Harkin <ryan.har...@linaro.org>
---
Embedde
mode, high speed,
HS200 & HS400 mode.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
Tested-by: Ryan Harkin <ryan.har...@linaro.org>
---
EmbeddedPkg/Include/Protocol/MmcHost.h | 20 +++
EmbeddedPkg/Univer
OCR busy bit free according to eMMC spec.
* Define ECSD structure.
* Add interface to set IO bus width and speed.
* Support to access multiple blocks.
Haojian Zhuang (4):
MmcDxe: add interface to change io width and speed
MmcDxe: set iospeed and bus width in SD stack
PL180
Add more SD commands to support 4-bit bus width & iospeed.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Haojian Zhuang <haojian.zhu...@linaro.org>
Tested-by: Ryan Harkin <ryan.har...@linaro.org>
---
EmbeddedPkg/Include/Protocol/MmcHost.h |
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