On Tue, Nov 17, 2015 at 03:59:13PM +0100, Ard Biesheuvel wrote:
> To align with the way normal cacheable memory is mapped, set the
> shareable bit for cached accesses performed by the page table walker.
>
> Contributed-under: TianoCore Contribution Agreement 1.0
> Signed-off-by: Ard Biesheuvel
R
To align with the way normal cacheable memory is mapped, set the
shareable bit for cached accesses performed by the page table walker.
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel
---
ArmPkg/Include/Chipset/ArmV7Mmu.h | 6 +++---
1 file changed, 3 inserti
2 matches
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