I read in !emc-pstc that Doug McKean dmck...@corp.auspex.com wrote (in
004b01c24f87$66393680$cb3e3...@corp.auspex.com) about 'Insulation
Distance Between Circuitboard Layers (Safety)' on Thu, 29 Aug 2002:
FR4 has a dielectric factor of about 4.7. That simply
means it's 4.7 times stronger than
Something's bothering me about this discussion.
It's not what people have said that I disagree.
Maybe it's to be put in the FWIW department,
1MV breaks down 1 meter of air @ STP.
It then follows that 1KV breaks down 1 mm of air.
So, that's 1mm AIR/1KV.
FR4 has a dielectric factor of
In a former job, I prevailed on them to follow (mostly) a rule of 100 mils
clearance between any inner OR outer layer conductor, and conducting
objects directly exposed to ESD. This, after a helpful layout designer
decided to improve things by adding internal ESD traces interlaced with
power and
In a message dated 8/28/2002, Chris Maxwell writes:
Can anyone see any pinholes in my reasoning? Can anyone recall the thread
regarding multiple layers of thin insulation?
Hi Chris:
Wow, you are really pushing the limits with your board design. I work with
EN 60950, and the clause in
Hi all,
A couple of weeks ago, I started a thread trying to relate creepage and
clearance distances on the surface of a circuitboard to layer spacing of
interior layers of a circuitboard. I deal with EN 61010-1; and I'm considering
double insulation between AC and SELV.
The result of that
5 matches
Mail list logo
