Re: [PSES] Power Integrity Question

2018-04-09 Thread Istvan Novak

Yes and no.
The coupling path was closing through the user PCB...


John Woodgate wrote:


That should be warned about in the data sheet. Internal EMC problems 
tend to be rare, which is good, but because they are rare, there 
should be warnings if they can occur.


John Woodgate OOO-Own Opinions Only
J M Woodgate and Associateswww.woodjohn.uk
Rayleigh, Essex UK
On 2018-04-09 13:19, Istvan Novak wrote:
And examples can be even more strange: we had DC-DC converter modules 
failing to work properly because one of the converter's power pins 
feeding an internal linear regulator picked up noise from the same 
converter.


Regards,
Istvan Novak



John Woodgate wrote:
I agree. One particular point is keeping a trace connected to an 
inverting input very short, even if that means including a 
low-value  'stopper' resistor close to the chip. That point has 
quasi-infinite sensitivity but infinitesimal impedance only within 
the op-amp pass band. Above the pass-band, it is an antenna 
connected to a diode. And yes, it can pick up power rail noise.


John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk
Rayleigh, Essex UK

On 2018-04-09 04:27, Doug Smith wrote:

Hi Ken and the group,

Many analog circuits, as well as the analog parts of large ICs that 
you mention, do have response to GHz noise even 1 MHz unity gain 
opamps! Low frequency op amps can  generate a DC offset on their 
inputs from GHz digital noise or radio signals, a common problem 
for the last  45 years since I first observed it. Power supply 
rejection of op amps goes to pot pretty quickly with frequency as 
well. High frequency effects therefore are important even to low 
speed analog circuits. In some ways, one must lay out the low 
frequency analog circuit using microwave techniques to keep RF 
noise at bay. The circuit features must be keep really small,, 
including the bypass capacitors being kept extremely close (< 100 
mils) to the op amp.


45 years ago, faced with opamp problems from RF noise I developed 
some techniques for keeping the op amps happy. I discuss these in 
my upcoming course.


Doug

University of Oxford, Course Tutor
Department for Continuing Education
Oxford, Oxfordshire, United Kingdom
--
Doug Smith
P.O. Box 60941
Boulder City, NV 89006-0941
TEL/FAX: 702-570-6108/570-6013
Mobile: 408-858-4528
Email: d...@dsmith.org
Web: http://www.dsmith.org
--





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Re: [PSES] Power Integrity Question

2018-04-09 Thread John Woodgate
That should be warned about in the data sheet. Internal EMC problems 
tend to be rare, which is good, but because they are rare, there should 
be warnings if they can occur.


John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk
Rayleigh, Essex UK

On 2018-04-09 13:19, Istvan Novak wrote:
And examples can be even more strange: we had DC-DC converter modules 
failing to work properly because one of the converter's power pins 
feeding an internal linear regulator picked up noise from the same 
converter.


Regards,
Istvan Novak



John Woodgate wrote:
I agree. One particular point is keeping a trace connected to an 
inverting input very short, even if that means including a low-value  
'stopper' resistor close to the chip. That point has quasi-infinite 
sensitivity but infinitesimal impedance only within the op-amp pass 
band. Above the pass-band, it is an antenna connected to a diode. And 
yes, it can pick up power rail noise.


John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk
Rayleigh, Essex UK

On 2018-04-09 04:27, Doug Smith wrote:

Hi Ken and the group,

Many analog circuits, as well as the analog parts of large ICs that 
you mention, do have response to GHz noise even 1 MHz unity gain 
opamps! Low frequency op amps can  generate a DC offset on their 
inputs from GHz digital noise or radio signals, a common problem for 
the last  45 years since I first observed it. Power supply rejection 
of op amps goes to pot pretty quickly with frequency as well. High 
frequency effects therefore are important even to low speed analog 
circuits. In some ways, one must lay out the low frequency analog 
circuit using microwave techniques to keep RF noise at bay. The 
circuit features must be keep really small,, including the bypass 
capacitors being kept extremely close (< 100 mils) to the op amp.


45 years ago, faced with opamp problems from RF noise I developed 
some techniques for keeping the op amps happy. I discuss these in my 
upcoming course.


Doug

University of Oxford, Course Tutor
Department for Continuing Education
Oxford, Oxfordshire, United Kingdom
--
Doug Smith
P.O. Box 60941
Boulder City, NV 89006-0941
TEL/FAX: 702-570-6108/570-6013
Mobile: 408-858-4528
Email: d...@dsmith.org
Web: http://www.dsmith.org
--





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Re: [PSES] Power Integrity Question

2018-04-09 Thread Istvan Novak
And examples can be even more strange: we had DC-DC converter modules 
failing to work properly because one of the converter's power pins 
feeding an internal linear regulator picked up noise from the same 
converter.


Regards,
Istvan Novak



John Woodgate wrote:
I agree. One particular point is keeping a trace connected to an 
inverting input very short, even if that means including a low-value  
'stopper' resistor close to the chip. That point has quasi-infinite 
sensitivity but infinitesimal impedance only within the op-amp pass 
band. Above the pass-band, it is an antenna connected to a diode. And 
yes, it can pick up power rail noise.


John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk
Rayleigh, Essex UK

On 2018-04-09 04:27, Doug Smith wrote:

Hi Ken and the group,

Many analog circuits, as well as the analog parts of large ICs that 
you mention, do have response to GHz noise even 1 MHz unity gain 
opamps! Low frequency op amps can  generate a DC offset on their 
inputs from GHz digital noise or radio signals, a common problem for 
the last  45 years since I first observed it. Power supply rejection 
of op amps goes to pot pretty quickly with frequency as well. High 
frequency effects therefore are important even to low speed analog 
circuits. In some ways, one must lay out the low frequency analog 
circuit using microwave techniques to keep RF noise at bay. The 
circuit features must be keep really small,, including the bypass 
capacitors being kept extremely close (< 100 mils) to the op amp.


45 years ago, faced with opamp problems from RF noise I developed 
some techniques for keeping the op amps happy. I discuss these in my 
upcoming course.


Doug

University of Oxford, Course Tutor
Department for Continuing Education
Oxford, Oxfordshire, United Kingdom
--
Doug Smith
P.O. Box 60941
Boulder City, NV 89006-0941
TEL/FAX: 702-570-6108/570-6013
Mobile: 408-858-4528
Email: d...@dsmith.org
Web: http://www.dsmith.org
--





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Re: [PSES] Power Integrity Question

2018-04-09 Thread John Woodgate
I agree. One particular point is keeping a trace connected to an 
inverting input very short, even if that means including a low-value  
'stopper' resistor close to the chip. That point has quasi-infinite 
sensitivity but infinitesimal impedance only within the op-amp pass 
band. Above the pass-band, it is an antenna connected to a diode. And 
yes, it can pick up power rail noise.


John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk
Rayleigh, Essex UK

On 2018-04-09 04:27, Doug Smith wrote:

Hi Ken and the group,

Many analog circuits, as well as the analog parts of large ICs that you mention, 
do have response to GHz noise even 1 MHz unity gain opamps! Low frequency op amps 
can  generate a DC offset on their inputs from GHz digital noise or radio signals, 
a common problem for the last  45 years since I first observed it. Power supply 
rejection of op amps goes to pot pretty quickly with frequency as well. High 
frequency effects therefore are important even to low speed analog circuits. In 
some ways, one must lay out the low frequency analog circuit using microwave 
techniques to keep RF noise at bay. The circuit features must be keep really 
small,, including the bypass capacitors being kept extremely close (< 100 mils) 
to the op amp.

45 years ago, faced with opamp problems from RF noise I developed some 
techniques for keeping the op amps happy. I discuss these in my upcoming course.

Doug

University of Oxford, Course Tutor
Department for Continuing Education
Oxford, Oxfordshire, United Kingdom
--
Doug Smith
P.O. Box 60941
Boulder City, NV 89006-0941
TEL/FAX: 702-570-6108/570-6013
Mobile: 408-858-4528
Email: d...@dsmith.org
Web: http://www.dsmith.org
--





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list. To post a message to the list, send your e-mail to 

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Re: [PSES] Power Integrity Question

2018-04-08 Thread Doug Smith
Hi Ken and the group,

Many analog circuits, as well as the analog parts of large ICs that you 
mention, do have response to GHz noise even 1 MHz unity gain opamps! Low 
frequency op amps can  generate a DC offset on their inputs from GHz digital 
noise or radio signals, a common problem for the last  45 years since I first 
observed it. Power supply rejection of op amps goes to pot pretty quickly with 
frequency as well. High frequency effects therefore are important even to low 
speed analog circuits. In some ways, one must lay out the low frequency analog 
circuit using microwave techniques to keep RF noise at bay. The circuit 
features must be keep really small,, including the bypass capacitors being kept 
extremely close (< 100 mils) to the op amp.

45 years ago, faced with opamp problems from RF noise I developed some 
techniques for keeping the op amps happy. I discuss these in my upcoming course.

Doug

University of Oxford, Course Tutor
Department for Continuing Education
Oxford, Oxfordshire, United Kingdom
--
Doug Smith
P.O. Box 60941
Boulder City, NV 89006-0941
TEL/FAX: 702-570-6108/570-6013
Mobile: 408-858-4528
Email: d...@dsmith.org
Web: http://www.dsmith.org
--


On Sun, 8 Apr 2018 12:30:10 -0400, Istvan Novak  wrote:

Ken,

Again, there is no generic answer, it depends on the circuit you feed.  
Generic low speed logic can be fairly tolerant to noise, but today's 
high-speed digital chips also have a lot of analog-like circuits: PLL, 
oscillators, SerDes drivers and receivers.  Dependent on their 
construction, their tolerance to noise can be very different.  If we are 
lucky, we get that requirement from the device's data sheet, so that we 
can decide about acceptable limits rail by rail and device by device.

Dips usually dont kill a device, it may cause 'only' functional errors.  
A spike can cause damage to the chips, but only if it appears on the 
semiconductor itself.  But we do not have direct access to the 
semiconductor to measure the voltage, and as opposed to signal 
integrity, where we can deembed the package and can reliably infer the 
waveform on the silicon from a waveform measured at the pin and from a 
package model, we almost never have a model for the power path of the 
package to do the same deembedding with power noise.

Regards,
Istvan Novak



Ken Javor wrote:
> Re: [PSES] Power Integrity Question Then let’s slightly rephrase the 
> question. What sort of ripple causes problems? Is it dips - how much? 
> Spikes – again, how much?  Let’s confine this to digital logic. Analog 
> is easier because there is defined power supply ripple rejection for 
> parts plus the noise sources aren’t high speed.
>
> Ken Javor
> Phone: (256) 650-5261
>
>
> 
> *From: *John Woodgate 
> *Date: *Sun, 8 Apr 2018 08:09:47 +0100
> *To: *Ken Javor , 
> 
> *Subject: *Re: [PSES] Power Integrity Question
>
>
>
> A specific target would typically be 'less than 1/3 of the value known 
> to just provoke trouble'.
>
>
> John Woodgate OOO-Own Opinions Only
> J M Woodgate and Associates www.woodjohn.uk  
> 
> Rayleigh, Essex UK
>
> On 2018-04-08 04:25, Ken Javor wrote:
>
>
> Re: [PSES] Power Integrity Question If the answer to how much
> ripple is too much, or how little ripple is good enough is in all
> cases, “it depends,” then does that mean that the pursuit of power
> integrity has a purely functional pass/fail criteria; i.e., that
> the unit operates properly, as opposed to a specific target on
> ripple level?
>
>  Ken Javor
>  Phone: (256) 650-5261
>
>
>
>
> ------------
> *From: *John Woodgate  
> 
> *Date: *Sat, 7 Apr 2018 17:58:36 +0100
> *To: *Ken Javor 
> 
>  ,
>  
> 
> *Subject: *Re: [PSES] Power Integrity Question
>
>
>
> I don't think that there is a general rule that doesn't have so
> many exceptions as to be useless. Even a 'simple' audio power
> amplifier can show this. A conventional linear amplifier can have
> very good PSRR (power supply rejection ratio) but a Class D
> amplifier has zero dB PSRR - none at all.
>
>
>  John Woodgate OOO-Own Opinions Only
>  J M Woodgate and Associates www.woodjohn.uk
>  
>  
>  Rayleigh, Essex UK
>
>  On 2018-04-07 17:41, Ken Javor wrote:
>
>
>
> Power Integrity Question There are many learned
> books/papers/discussions on how to achieve proper power
> integrity by way of proper PCB layout and proper capacitor

Re: [PSES] Power Integrity Question

2018-04-08 Thread Istvan Novak

Ken,

Again, there is no generic answer, it depends on the circuit you feed.  
Generic low speed logic can be fairly tolerant to noise, but today's 
high-speed digital chips also have a lot of analog-like circuits: PLL, 
oscillators, SerDes drivers and receivers.  Dependent on their 
construction, their tolerance to noise can be very different.  If we are 
lucky, we get that requirement from the device's data sheet, so that we 
can decide about acceptable limits rail by rail and device by device.


Dips usually dont kill a device, it may cause 'only' functional errors.  
A spike can cause damage to the chips, but only if it appears on the 
semiconductor itself.  But we do not have direct access to the 
semiconductor to measure the voltage, and as opposed to signal 
integrity, where we can deembed the package and can reliably infer the 
waveform on the silicon from a waveform measured at the pin and from a 
package model, we almost never have a model for the power path of the 
package to do the same deembedding with power noise.


Regards,
Istvan Novak



Ken Javor wrote:
Re: [PSES] Power Integrity Question Then let’s slightly rephrase the 
question. What sort of ripple causes problems? Is it dips - how much? 
Spikes – again, how much?  Let’s confine this to digital logic. Analog 
is easier because there is defined power supply ripple rejection for 
parts plus the noise sources aren’t high speed.


Ken Javor
Phone: (256) 650-5261



*From: *John Woodgate 
*Date: *Sun, 8 Apr 2018 08:09:47 +0100
*To: *Ken Javor , 


*Subject: *Re: [PSES] Power Integrity Question



A specific target would typically be 'less than 1/3 of the value known 
to just provoke trouble'.



John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk <http://www.woodjohn.uk> 
<http://www.woodjohn.uk>

Rayleigh, Essex UK

On 2018-04-08 04:25, Ken Javor wrote:


Re: [PSES] Power Integrity Question If the answer to how much
ripple is too much, or how little ripple is good enough is in all
cases, “it depends,” then does that mean that the pursuit of power
integrity has a purely functional pass/fail criteria; i.e., that
the unit operates properly, as opposed to a specific target on
ripple level?

 Ken Javor
 Phone: (256) 650-5261





*From: *John Woodgate  <mailto:j...@woodjohn.uk>
<mailto:j...@woodjohn.uk>
*Date: *Sat, 7 Apr 2018 17:58:36 +0100
*To: *Ken Javor 
<mailto:ken.ja...@emccompliance.com>
<mailto:ken.ja...@emccompliance.com> ,
 <mailto:EMC-PSTC@LISTSERV.IEEE.ORG>
<mailto:EMC-PSTC@LISTSERV.IEEE.ORG>
*Subject: *Re: [PSES] Power Integrity Question



I don't think that there is a general rule that doesn't have so
many exceptions as to be useless. Even a 'simple' audio power
amplifier can show this. A conventional linear amplifier can have
very good PSRR (power supply rejection ratio) but a Class D
amplifier has zero dB PSRR - none at all.


 John Woodgate OOO-Own Opinions Only
 J M Woodgate and Associates www.woodjohn.uk
<http://www.woodjohn.uk> <http://www.woodjohn.uk>
<http://www.woodjohn.uk> <http://www.woodjohn.uk>
 Rayleigh, Essex UK

 On 2018-04-07 17:41, Ken Javor wrote:



Power Integrity Question There are many learned
books/papers/discussions on how to achieve proper power
integrity by way of proper PCB layout and proper capacitor
decoupling techniques, but what is the goal?  I don't mean the
functional goal, which is obvious, but rather what is the
metric?  Is it ripple voltage peak-to-peak, maximum excursion,
minimum excursion, some rms value, or...?

  This question is decoupled from achieving PI for the purpose
of controlling radiated emissions: just asking how close to
pure unadulterated dc a dc rail must be in order to be
considered properly functional.

  Understand the answer will be different for an analog rail
vs. a digital one, and for different digital rails, but
appreciate insight into what constitutes acceptable power
quality for all dc rails used in a typical piece of electronics.

  Thank you,

  Ken Javor
  Phone: (256) 650-5261


   -
 


 This message is from the IEEE Product Safety Engineering
Society emc-pstc discussion list. To post a message to the
list, send your e-mail to 
<mailto:emc-p...@ieee.org> <mailto:emc-p...@ieee.org>


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at: http://w

Re: [PSES] Power Integrity Question

2018-04-08 Thread Ken Javor
Then let¹s slightly rephrase the question. What sort of ripple causes
problems? Is it dips - how much? Spikes ­ again, how much?  Let¹s confine
this to digital logic. Analog is easier because there is defined power
supply ripple rejection for parts plus the noise sources aren¹t high speed.

Ken Javor
Phone: (256) 650-5261



From: John Woodgate 
Date: Sun, 8 Apr 2018 08:09:47 +0100
To: Ken Javor , 
Subject: Re: [PSES] Power Integrity Question

   

A specific target would typically be 'less than 1/3 of the value known to
just provoke trouble'.
 
 
John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk <http://www.woodjohn.uk>
Rayleigh, Essex UK
 
On 2018-04-08 04:25, Ken Javor wrote:
 
 
>  Re: [PSES] Power Integrity Question If the answer to how much ripple is too
> much, or how little ripple is good enough is in all cases, ³it depends,² then
> does that mean that the pursuit of power integrity has a purely functional
> pass/fail criteria; i.e., that the unit operates properly, as opposed to a
> specific target on ripple level?
>  
>  Ken Javor
>  Phone: (256) 650-5261
>  
>  
>  
>  
> 
> From: John Woodgate  <mailto:j...@woodjohn.uk>
>  Date: Sat, 7 Apr 2018 17:58:36 +0100
>  To: Ken Javor 
> <mailto:ken.ja...@emccompliance.com> , 
> <mailto:EMC-PSTC@LISTSERV.IEEE.ORG>
>  Subject: Re: [PSES] Power Integrity Question
>  
>     
>  
>  I don't think that there is a general rule that doesn't have so many
> exceptions as to be useless. Even a 'simple' audio power amplifier can show
> this. A conventional linear amplifier can have very good PSRR (power supply
> rejection ratio) but a Class D amplifier has zero dB PSRR - none at all.
>   
>   
>  John Woodgate OOO-Own Opinions Only
>  J M Woodgate and Associates www.woodjohn.uk <http://www.woodjohn.uk>
> <http://www.woodjohn.uk>
>  Rayleigh, Essex UK
>   
>  On 2018-04-07 17:41, Ken Javor wrote:
>   
>   
>   
>>  Power Integrity Question There are many learned books/papers/discussions on
>> how to achieve proper power integrity by way of proper PCB layout and proper
>> capacitor decoupling techniques, but what is the goal?  I don't mean the
>> functional goal, which is obvious, but rather what is the metric?  Is it
>> ripple voltage peak-to-peak, maximum excursion, minimum excursion, some rms
>> value, or...?
>>   
>>   This question is decoupled from achieving PI for the purpose of controlling
>> radiated emissions: just asking how close to pure unadulterated dc a dc rail
>> must be in order to be considered properly functional.
>>   
>>   Understand the answer will be different for an analog rail vs. a digital
>> one, and for different digital rails, but appreciate insight into what
>> constitutes acceptable power quality for all dc rails used in a typical piece
>> of electronics.
>>   
>>   Thank you,
>>   
>>   Ken Javor
>>   Phone: (256) 650-5261
>>   
>>   
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Re: [PSES] Power Integrity Question

2018-04-08 Thread John Woodgate
A specific target would typically be 'less than 1/3 of the value known 
to just provoke trouble'.


John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk
Rayleigh, Essex UK

On 2018-04-08 04:25, Ken Javor wrote:
Re: [PSES] Power Integrity Question If the answer to how much ripple 
is too much, or how little ripple is good enough is in all cases, “it 
depends,” then does that mean that the pursuit of power integrity has 
a purely functional pass/fail criteria; i.e., that the unit operates 
properly, as opposed to a specific target on ripple level?


Ken Javor
Phone: (256) 650-5261




*From: *John Woodgate 
*Date: *Sat, 7 Apr 2018 17:58:36 +0100
*To: *Ken Javor , 


*Subject: *Re: [PSES] Power Integrity Question



I don't think that there is a general rule that doesn't have so many 
exceptions as to be useless. Even a 'simple' audio power amplifier can 
show this. A conventional linear amplifier can have very good PSRR 
(power supply rejection ratio) but a Class D amplifier has zero dB 
PSRR - none at all.



John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk <http://www.woodjohn.uk> 
<http://www.woodjohn.uk>

Rayleigh, Essex UK

On 2018-04-07 17:41, Ken Javor wrote:


Power Integrity Question There are many learned
books/papers/discussions on how to achieve proper power integrity
by way of proper PCB layout and proper capacitor decoupling
techniques, but what is the goal?  I don't mean the functional
goal, which is obvious, but rather what is the metric?  Is it
ripple voltage peak-to-peak, maximum excursion, minimum excursion,
some rms value, or...?

 This question is decoupled from achieving PI for the purpose of
controlling radiated emissions: just asking how close to pure
unadulterated dc a dc rail must be in order to be considered
properly functional.

 Understand the answer will be different for an analog rail vs. a
digital one, and for different digital rails, but appreciate
insight into what constitutes acceptable power quality for all dc
rails used in a typical piece of electronics.

 Thank you,

 Ken Javor
 Phone: (256) 650-5261


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Re: [PSES] Power Integrity Question

2018-04-07 Thread Ken Javor
If the answer to how much ripple is too much, or how little ripple is good
enough is in all cases, ³it depends,² then does that mean that the pursuit
of power integrity has a purely functional pass/fail criteria; i.e., that
the unit operates properly, as opposed to a specific target on ripple level?

Ken Javor
Phone: (256) 650-5261




From: John Woodgate 
Date: Sat, 7 Apr 2018 17:58:36 +0100
To: Ken Javor , 
Subject: Re: [PSES] Power Integrity Question

   

I don't think that there is a general rule that doesn't have so many
exceptions as to be useless. Even a 'simple' audio power amplifier can show
this. A conventional linear amplifier can have very good PSRR (power supply
rejection ratio) but a Class D amplifier has zero dB PSRR - none at all.
 
 
John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk <http://www.woodjohn.uk>
Rayleigh, Essex UK
 
On 2018-04-07 17:41, Ken Javor wrote:
 
 
>  Power Integrity Question There are many learned books/papers/discussions on
> how to achieve proper power integrity by way of proper PCB layout and proper
> capacitor decoupling techniques, but what is the goal?  I don't mean the
> functional goal, which is obvious, but rather what is the metric?  Is it
> ripple voltage peak-to-peak, maximum excursion, minimum excursion, some rms
> value, or...?
>  
>  This question is decoupled from achieving PI for the purpose of controlling
> radiated emissions: just asking how close to pure unadulterated dc a dc rail
> must be in order to be considered properly functional.
>  
>  Understand the answer will be different for an analog rail vs. a digital one,
> and for different digital rails, but appreciate insight into what constitutes
> acceptable power quality for all dc rails used in a typical piece of
> electronics.
>  
>  Thank you,
>  
>  Ken Javor
>  Phone: (256) 650-5261
>  
>  
>   -
>  
>  
> 
> This message is from the IEEE Product Safety Engineering Society emc-pstc
> discussion list. To post a message to the list, send your e-mail to
> 
>  
> 
> All emc-pstc postings are archived and searchable on the web at:
> http://www.ieee-pses.org/emc-pstc.html
>  
> 
> Attachments are not permitted but the IEEE PSES Online Communities site at
> http://product-compliance.oc.ieee.org/ can be used for graphics (in well-used
> formats), large files, etc.
>  
> 
> Website: http://www.ieee-pses.org/
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> unsubscribe) <http://www.ieee-pses.org/list.html>
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>  Mike Cantwell 
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Re: [PSES] Power Integrity Question

2018-04-07 Thread Istvan Novak

Hi Ken,

Good question, and as you already suspect, there is no clear, generic 
answer (and for the same reason there is no such thing as typical 
electronics).  Having practiced this art for decades, and teaching 
courses (up to five days in length) on the subject, the best we can do 
is to explain all possible factors that eventually the responsible 
designer has to take into account.


You will find pieces of the answer in various books and on the 
publications posted on my website, for instance

http://www.electrical-integrity.com/Paper_download_files/Ansoft_EMI_Workshop_SUN_for_22Aug07_v2.pdf

Regards,
Istvan Novak

Ken Javor wrote:
Power Integrity Question There are many learned 
books/papers/discussions on how to achieve proper power integrity by 
way of proper PCB layout and proper capacitor decoupling techniques, 
but what is the goal?  I don't mean the functional goal, which is 
obvious, but rather what is the metric?  Is it ripple voltage 
peak-to-peak, maximum excursion, minimum excursion, some rms value, or...?


This question is decoupled from achieving PI for the purpose of 
controlling radiated emissions: just asking how close to pure 
unadulterated dc a dc rail must be in order to be considered properly 
functional.


Understand the answer will be different for an analog rail vs. a 
digital one, and for different digital rails, but appreciate insight 
into what constitutes acceptable power quality for all dc rails used 
in a typical piece of electronics.


Thank you,

Ken Javor
Phone: (256) 650-5261


-


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Re: [PSES] Power Integrity Question

2018-04-07 Thread John Woodgate
I don't think that there is a general rule that doesn'thave so many 
exceptions as to be useless. Even a 'simple' audio power amplifier can 
show this. A conventional linear amplifier can have very good PSRR 
(power supply rejection ratio) but a Class D amplifier has zero dB PSRR 
- none at all.


John Woodgate OOO-Own Opinions Only
J M Woodgate and Associates www.woodjohn.uk
Rayleigh, Essex UK

On 2018-04-07 17:41, Ken Javor wrote:
Power Integrity Question There are many learned 
books/papers/discussions on how to achieve proper power integrity by 
way of proper PCB layout and proper capacitor decoupling techniques, 
but what is the goal?  I don't mean the functional goal, which is 
obvious, but rather what is the metric?  Is it ripple voltage 
peak-to-peak, maximum excursion, minimum excursion, some rms value, or...?


This question is decoupled from achieving PI for the purpose of 
controlling radiated emissions: just asking how close to pure 
unadulterated dc a dc rail must be in order to be considered properly 
functional.


Understand the answer will be different for an analog rail vs. a 
digital one, and for different digital rails, but appreciate insight 
into what constitutes acceptable power quality for all dc rails used 
in a typical piece of electronics.


Thank you,

Ken Javor
Phone: (256) 650-5261


-


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