subject:"\[Emc\-users\] mesa 7i80 configuration"

Re: [Emc-users] mesa 7i80 configuration

2022-01-28 Thread Peter C. Wallace

On Fri, 28 Jan 2022, John Figie wrote:

Date: Fri, 28 Jan 2022 17:28:19 -0600
From: John Figie 
Reply-To: "Enhanced Machine Controller (EMC)"

To: "Enhanced Machine Controller (EMC)" 
Subject: Re: [Emc-users] mesa 7i80 configuration

OK

So I don't see any documentation for PktUART and it would require a custom
bit file. So that is something maybe I could add later in a custom bit file?

Sure

In the meantime I just need something that actually works that has 3 pwm
outputs and 3 encoder inputs. So can you suggest a bit file that I can use
as is and may also be a starting point for a custom file that adds 3 UARTS?

Any of the SVST bitfiles should work

regards,

John

On Fri, Jan 28, 2022, 3:48 PM Peter C. Wallace  wrote:

halrun I get a different error
hm2/hm2_7i80.0: inconsistent Module Descriptor for UART Transmit Channel,
not loading driver.

Thats probably because that was built with a batch file and theres a
source code
tweek needed for the UART module because it uses a differeent register
stride
  For this and other reasons, I would suggest not using the UART and using
the
PktUART instead. This wil likely require a custom bitfile

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Re: [Emc-users] mesa 7i80 configuration

2022-01-28 Thread John Figie

OK

So I don't see any documentation for PktUART and it would require a custom
bit file. So that is something maybe I could add later in a custom bit file?

In the meantime I just need something that actually works that has 3 pwm
outputs and 3 encoder inputs. So can you suggest a bit file that I can use
as is and may also be a starting point for a custom file that adds 3 UARTS?

regards,

John

On Fri, Jan 28, 2022, 3:48 PM Peter C. Wallace  wrote:

>
> > halrun I get a different error
> > hm2/hm2_7i80.0: inconsistent Module Descriptor for UART Transmit Channel,
> > not loading driver.
> >
> Thats probably because that was built with a batch file and theres a
> source code
> tweek needed for the UART module because it uses a differeent register
> stride
>   For this and other reasons, I would suggest not using the UART and using
> the
> PktUART instead. This wil likely require a custom bitfile
>
>

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Re: [Emc-users] mesa 7i80 configuration

2022-01-28 Thread Peter C. Wallace

On Fri, 28 Jan 2022, John Figie wrote:

Date: Fri, 28 Jan 2022 14:30:59 -0600
From: John Figie 
Reply-To: "Enhanced Machine Controller (EMC)"

To: "Enhanced Machine Controller (EMC)" 
Subject: Re: [Emc-users] mesa 7i80 configuration

What is the md5 checksum of the bitfile you are using?

zephyr@Clausing:~/linuxcnc/configs/7i80/7i80/configs/hostmot2$ md5sum

7i80hd_25_2x7i65.bit
d3f91185e95027ca93ae00a1334d852d  7i80hd_25_2x7i65.bit

That matches so its probably a bad bitfile. I thin most of those bitfile were 
made automatically a long time ago and may have timing issues

I can remake it if you wish

But this may be all academic at this point. I think that even if I get the
file loaded with BSPIs the stuff
that I will need to figure out to make this all work seems difficult and
may not be worth the time.

So what I _really_ wanted is a simple SPI interface to send current command
to my drives, which
I thought would be simple to do, however, now I think I should just use a
bit file that was intended to work
with a card like the 7i33.  So I found something that I like called
7i80hd_25_svua8_4. I think this is for a 7i33 but it also
has some UARTs as well. I would like to make use of the UARTs for
non-realtime communications with some of my
devices such as SICK hiperface encoders to read the absolute position and
or maybe communications with some of
my drives.  Instead of using the SPI passing simple current_magnituce to
the drive I will just use the PWM output as the
current command like an analog servo in torque (current) mode.

If that really all does work I feel like I may be more competent hacking
the VHDL code for the FPGA to add my own SPIs that
just look like the PWM registers to LinuxCNC. When I had a real job I used
Altera (now Intel) Quartus with SOC (dual ARM with
FPGA) so using the Xilinx stuff does not seem as challenging as linuxCNC
code.

but when I load the 7i80hd_25_svua8_4 and then run my simple hal file using
halrun I get a different error
hm2/hm2_7i80.0: inconsistent Module Descriptor for UART Transmit Channel,
not loading driver.

Thats probably because that was built with a batch file and theres a source code 
tweek needed for the UART module because it uses a differeent register stride
 For this and other reasons, I would suggest not using the UART and using the 
PktUART instead. This wil likely require a custom bitfile

so, do I need to load something like mesa_uart first? that does not
appear in the list of 2.8 or 2.7 man pages so I suspect
I need to do something different but a lot of the 2.8 man pages are missing
- so this is really getting hard
fo figure out

regards,

John

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Mesa Electronics

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Re: [Emc-users] mesa 7i80 configuration

2022-01-28 Thread John Figie

> What is the md5 checksum of the bitfile you are using?
>
> zephyr@Clausing:~/linuxcnc/configs/7i80/7i80/configs/hostmot2$ md5sum
7i80hd_25_2x7i65.bit
d3f91185e95027ca93ae00a1334d852d  7i80hd_25_2x7i65.bit

But this may be all academic at this point. I think that even if I get the
file loaded with BSPIs the stuff
that I will need to figure out to make this all work seems difficult and
may not be worth the time.

So what I _really_ wanted is a simple SPI interface to send current command
to my drives, which
I thought would be simple to do, however, now I think I should just use a
bit file that was intended to work
with a card like the 7i33.  So I found something that I like called
7i80hd_25_svua8_4. I think this is for a 7i33 but it also
has some UARTs as well. I would like to make use of the UARTs for
non-realtime communications with some of my
devices such as SICK hiperface encoders to read the absolute position and
or maybe communications with some of
my drives.  Instead of using the SPI passing simple current_magnituce to
the drive I will just use the PWM output as the
current command like an analog servo in torque (current) mode.

If that really all does work I feel like I may be more competent hacking
the VHDL code for the FPGA to add my own SPIs that
just look like the PWM registers to LinuxCNC. When I had a real job I used
Altera (now Intel) Quartus with SOC (dual ARM with
FPGA) so using the Xilinx stuff does not seem as challenging as linuxCNC
code.

but when I load the 7i80hd_25_svua8_4 and then run my simple hal file using
halrun I get a different error
hm2/hm2_7i80.0: inconsistent Module Descriptor for UART Transmit Channel,
not loading driver.

so, do I need to load something like mesa_uart first? that does not
appear in the list of 2.8 or 2.7 man pages so I suspect
I need to do something different but a lot of the 2.8 man pages are missing
- so this is really getting hard
fo figure out

regards,

John

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Re: [Emc-users] mesa 7i80 configuration

2022-01-28 Thread Peter C. Wallace


On Fri, 28 Jan 2022, John Figie wrote:


Date: Fri, 28 Jan 2022 13:21:04 -0600
From: John Figie 
Reply-To: "Enhanced Machine Controller (EMC)"

To: "Enhanced Machine Controller (EMC)" 
Subject: Re: [Emc-users] mesa 7i80 configuration

Peter,

Thanks for verifying this in your environment.
When you say communications issue do you mean something other than
electrical noise?

I doubt that there is a noise issue with my communications as right now I
am in a pretty
good environment. There are no drives or other noisy devices running, the
mesa hardware is mounted to a 3/8" thick grounded
aluminum sub panel with standoffs. The 5v power supply is ungrounded but
supplied through a shielded cable with the shield
single point grounded to the subpanel. The power looks clean on a scope.
The subpanel is connected to the PE (protective earth)
for the building. The ethernet CAT5E UTP cable is maybe about 3' long.

If I read the FPGA hmid using mesaflash I also read 65535. If the data was
bad from noise then wouldn't
the packet be dropped (bad crc) and other data besides the idrom value be
incorrect?
but the mesaflash --readhmid returns all of the other info that is expected
- i think.




That's really weird, it actually looks like a FPGA or bitfile fault

What is the md5 checksum of the bitfile you are using?


Also I can rebuild that file for testing



the output looks like this:
zephyr@Clausing:~/linuxcnc/configs/7i80/7i80/configs/hostmot2$ mesaflash
--device 7i80 --addr 10.10.10.10 --readhmid
Configuration Name: HOSTMOT2

General configuration information:

 BoardName : MESA7I80
 FPGA Size: 25 KGates
 FPGA Pins: 256
 Number of IO Ports: 3
 Width of one I/O port: 24
 Clock Low frequency: 100. MHz
 Clock High frequency: 200. MHz
 IDROM Type: 65535
 Instance Stride 0: 4
 Instance Stride 1: 64
 Register Stride 0: 256
 Register Stride 1: 256

Modules in configuration:

 Module: WatchDog
 There are 1 of WatchDog in configuration
 Version: 0
 Registers: 3
 BaseAddress: 0C00
 ClockFrequency: 100.000 MHz
 Register Stride: 256 bytes
 Instance Stride: 4 bytes

 Module: IOPort
 There are 3 of IOPort in configuration
 Version: 0
 Registers: 5
 BaseAddress: 1000
 ClockFrequency: 100.000 MHz
 Register Stride: 256 bytes
 Instance Stride: 4 bytes

 Module: MuxedQCount
 There are 16 of MuxedQCount in configuration
 Version: 3
 Registers: 5
 BaseAddress: 3500
 ClockFrequency: 100.000 MHz
 Register Stride: 256 bytes
 Instance Stride: 4 bytes

 Module: MuxedQCountSel
 There are 1 of MuxedQCountSel in configuration
 Version: 0
 Registers: 0
 BaseAddress: 
 ClockFrequency: 100.000 MHz
 Register Stride: 256 bytes
 Instance Stride: 4 bytes

 Module: BufSPI
 There are 2 of BufSPI in configuration
 Version: 0
 Registers: 3
 BaseAddress: 5400
 ClockFrequency: 100.000 MHz
 Register Stride: 256 bytes
 Instance Stride: 64 bytes

 Module: LED
 There are 1 of LED in configuration
 Version: 0
 Registers: 1
 BaseAddress: 0200
 ClockFrequency: 100.000 MHz
 Register Stride: 256 bytes
 Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for P1
Pin#  I/O   Pri. funcSec. func   Chan  Pin func
  Pin Dir

1  0   IOPort   MuxedQCount  0MuxQ-A
  (In)
3  1   IOPort   MuxedQCount  0MuxQ-B
  (In)
5  2   IOPort   MuxedQCount  0MuxQ-IDX
  (In)
7  3   IOPort   MuxedQCount  1MuxQ-A
  (In)
9  4   IOPort   MuxedQCount  1MuxQ-B
  (In)
11  5   IOPort   MuxedQCount  1MuxQ-IDX
  (In)
13  6   IOPort   MuxedQCount  2MuxQ-A
  (In)
15  7   IOPort   MuxedQCount  2MuxQ-B
  (In)
17  8   IOPort   MuxedQCount  2MuxQ-IDX
  (In)
19  9   IOPort   MuxedQCount  3MuxQ-A
  (In)
21 10   IOPort   MuxedQCount  3MuxQ-B
  (In)
23 11   IOPort   MuxedQCount  3MuxQ-IDX
  (In)
25 12   IOPort   None
27 13   IOPort   MuxedQCountSel   0MuxSel0
   (Out)
29 14   IOPort   BufSPI   0/Frame
  (Out)
31 15   IOPort   BufSPI   0DOut
  (Out)
33 16   IOPort   BufSPI   0SClk
  (Out)
35 17   IOPort   BufSPI   0DIn
   (In)
37 18   IOPort   BufSPI   0CS2
   (Out)
39 19   IOPort   BufSPI   0CS1
   (Out)
41 20   IOPort   BufSPI   0CS0
   (Out)
43 21   IOPort   None
45

Re: [Emc-users] mesa 7i80 configuration

2022-01-28 Thread John Figie

Peter,

Thanks for verifying this in your environment.
When you say communications issue do you mean something other than
electrical noise?

I doubt that there is a noise issue with my communications as right now I
am in a pretty
good environment. There are no drives or other noisy devices running, the
mesa hardware is mounted to a 3/8" thick grounded
aluminum sub panel with standoffs. The 5v power supply is ungrounded but
supplied through a shielded cable with the shield
single point grounded to the subpanel. The power looks clean on a scope.
The subpanel is connected to the PE (protective earth)
for the building. The ethernet CAT5E UTP cable is maybe about 3' long.

If I read the FPGA hmid using mesaflash I also read 65535. If the data was
bad from noise then wouldn't
the packet be dropped (bad crc) and other data besides the idrom value be
incorrect?
but the mesaflash --readhmid returns all of the other info that is expected
- i think.

the output looks like this:
zephyr@Clausing:~/linuxcnc/configs/7i80/7i80/configs/hostmot2$ mesaflash
--device 7i80 --addr 10.10.10.10 --readhmid
Configuration Name: HOSTMOT2

General configuration information:

  BoardName : MESA7I80
  FPGA Size: 25 KGates
  FPGA Pins: 256
  Number of IO Ports: 3
  Width of one I/O port: 24
  Clock Low frequency: 100. MHz
  Clock High frequency: 200. MHz
  IDROM Type: 65535
  Instance Stride 0: 4
  Instance Stride 1: 64
  Register Stride 0: 256
  Register Stride 1: 256

Modules in configuration:

  Module: WatchDog
  There are 1 of WatchDog in configuration
  Version: 0
  Registers: 3
  BaseAddress: 0C00
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: IOPort
  There are 3 of IOPort in configuration
  Version: 0
  Registers: 5
  BaseAddress: 1000
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: MuxedQCount
  There are 16 of MuxedQCount in configuration
  Version: 3
  Registers: 5
  BaseAddress: 3500
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: MuxedQCountSel
  There are 1 of MuxedQCountSel in configuration
  Version: 0
  Registers: 0
  BaseAddress: 
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

  Module: BufSPI
  There are 2 of BufSPI in configuration
  Version: 0
  Registers: 3
  BaseAddress: 5400
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 64 bytes

  Module: LED
  There are 1 of LED in configuration
  Version: 0
  Registers: 1
  BaseAddress: 0200
  ClockFrequency: 100.000 MHz
  Register Stride: 256 bytes
  Instance Stride: 4 bytes

Configuration pin-out:

IO Connections for P1
Pin#  I/O   Pri. funcSec. func   Chan  Pin func
   Pin Dir

 1  0   IOPort   MuxedQCount  0MuxQ-A
   (In)
 3  1   IOPort   MuxedQCount  0MuxQ-B
   (In)
 5  2   IOPort   MuxedQCount  0MuxQ-IDX
   (In)
 7  3   IOPort   MuxedQCount  1MuxQ-A
   (In)
 9  4   IOPort   MuxedQCount  1MuxQ-B
   (In)
11  5   IOPort   MuxedQCount  1MuxQ-IDX
   (In)
13  6   IOPort   MuxedQCount  2MuxQ-A
   (In)
15  7   IOPort   MuxedQCount  2MuxQ-B
   (In)
17  8   IOPort   MuxedQCount  2MuxQ-IDX
   (In)
19  9   IOPort   MuxedQCount  3MuxQ-A
   (In)
21 10   IOPort   MuxedQCount  3MuxQ-B
   (In)
23 11   IOPort   MuxedQCount  3MuxQ-IDX
   (In)
25 12   IOPort   None
27 13   IOPort   MuxedQCountSel   0MuxSel0
(Out)
29 14   IOPort   BufSPI   0/Frame
   (Out)
31 15   IOPort   BufSPI   0DOut
   (Out)
33 16   IOPort   BufSPI   0SClk
   (Out)
35 17   IOPort   BufSPI   0DIn
(In)
37 18   IOPort   BufSPI   0CS2
(Out)
39 19   IOPort   BufSPI   0CS1
(Out)
41 20   IOPort   BufSPI   0CS0
(Out)
43 21   IOPort   None
45 22   IOPort   None
47 23   IOPort   None

IO Connections for P2
Pin#  I/O   Pri. funcSec. func   Chan  Pin func
   Pin Dir

 1 24   IOPort   MuxedQCount  4MuxQ-A
   (In)
 3 25   IOPort   MuxedQCount  4

Re: [Emc-users] mesa 7i80 configuration

2022-01-27 Thread Peter C. Wallace


On Thu, 27 Jan 2022, John Figie wrote:


Date: Thu, 27 Jan 2022 17:28:03 -0600
From: John Figie 
Reply-To: "Enhanced Machine Controller (EMC)"

To: "Enhanced Machine Controller (EMC)" 
Subject: Re: [Emc-users] mesa 7i80 configuration



7i80hd_25_2x7i65.bit has 2x BSPI and 16 muxed encoders

(which would work for testing even if
you don't have muxed interface hardware)

It sounds like you would want custom formware


mesaflash --device 7i80 --addr 10.10.10.10 --write  7i80hd_25_2x7i65.bit

it writes and verifies but then in halrun I get a different error. I tried
this several times.

hm2/hm2_7i80.0 Low level init 0.15
hm2/hm2_7i80.0 invalid IDROM type 65535, expected 2 or 3 aborting load
board fails HM2_registration

also when you say 16 muxed encoders how are these muxed?

regards,

John


Muxed encoders are 2x multiplexed (even/odd) by a single output pin

Umm not sure what the error is all about, maybe communication issues?

I get this with 7i80hd_25_2x7i65 firmware:

LINUXCNC - 2.8.2
Machine configuration directory is '/home/pcw/linuxcnc/configs'
Machine configuration file is '7i80hdtest.ini'
Starting LinuxCNC...
Found file(REL): ./basic.hal
Note: Using POSIX realtime
hm2: loading Mesa HostMot2 driver version 0.15
hm2_eth: loading Mesa AnyIO HostMot2 ethernet driver version 0.2
hm2_eth: 10.10.10.10: INFO: Hardware address (MAC): 00:60:1b:11:81:72
hm2_eth: discovered 7I80HD-25
hm2/hm2_7i80.0: Low Level init 0.15
hm2/hm2_7i80.0: created Buffered SPI function hm2_7i80.0.bspi.0.
hm2/hm2_7i80.0: created Buffered SPI function hm2_7i80.0.bspi.1.
hm2/hm2_7i80.0: 72 I/O Pins used:
hm2/hm2_7i80.0: IO Pin 000 (P1-01): Muxed Encoder #0, pin Muxed A (Input)
hm2/hm2_7i80.0: IO Pin 001 (P1-03): Muxed Encoder #0, pin Muxed B (Input)
hm2/hm2_7i80.0: IO Pin 002 (P1-05): Muxed Encoder #0, pin Muxed Index 
(Input)
hm2/hm2_7i80.0: IO Pin 003 (P1-07): Muxed Encoder #1, pin Muxed A (Input)
hm2/hm2_7i80.0: IO Pin 004 (P1-09): Muxed Encoder #1, pin Muxed B (Input)
hm2/hm2_7i80.0: IO Pin 005 (P1-11): Muxed Encoder #1, pin Muxed Index 
(Input)
hm2/hm2_7i80.0: IO Pin 006 (P1-13): Muxed Encoder #2, pin Muxed A (Input)
hm2/hm2_7i80.0: IO Pin 007 (P1-15): Muxed Encoder #2, pin Muxed B (Input)
hm2/hm2_7i80.0: IO Pin 008 (P1-17): Muxed Encoder #2, pin Muxed Index 
(Input)
hm2/hm2_7i80.0: IO Pin 009 (P1-19): Muxed Encoder #3, pin Muxed A (Input)
hm2/hm2_7i80.0: IO Pin 010 (P1-21): Muxed Encoder #3, pin Muxed B (Input)
hm2/hm2_7i80.0: IO Pin 011 (P1-23): Muxed Encoder #3, pin Muxed Index 
(Input)
hm2/hm2_7i80.0: IO Pin 012 (P1-25): IOPort
hm2/hm2_7i80.0: IO Pin 013 (P1-27): Muxed Encoder Select #0, pin Mux Select 
0 (Output)
hm2/hm2_7i80.0: IO Pin 014 (P1-29): Buffered SPI Interface #0, pin /Frame 
(Output)
hm2/hm2_7i80.0: IO Pin 015 (P1-31): Buffered SPI Interface #0, pin Serial 
Out (Output)
hm2/hm2_7i80.0: IO Pin 016 (P1-33): Buffered SPI Interface #0, pin Clock 
(Output)
hm2/hm2_7i80.0: IO Pin 017 (P1-35): Buffered SPI Interface #0, pin Serial 
In (Input)
hm2/hm2_7i80.0: IO Pin 018 (P1-37): Buffered SPI Interface #0, pin CS2 
(Output)
hm2/hm2_7i80.0: IO Pin 019 (P1-39): Buffered SPI Interface #0, pin CS1 
(Output)
hm2/hm2_7i80.0: IO Pin 020 (P1-41): Buffered SPI Interface #0, pin CS0 
(Output)
hm2/hm2_7i80.0: IO Pin 021 (P1-43): IOPort
hm2/hm2_7i80.0: IO Pin 022 (P1-45): IOPort
hm2/hm2_7i80.0: IO Pin 023 (P1-47): IOPort
hm2/hm2_7i80.0: IO Pin 024 (P2-01): Muxed Encoder #4, pin Muxed A (Input)
hm2/hm2_7i80.0: IO Pin 025 (P2-03): Muxed Encoder #4, pin Muxed B (Input)
hm2/hm2_7i80.0: IO Pin 026 (P2-05): Muxed Encoder #4, pin Muxed Index 
(Input)
hm2/hm2_7i80.0: IO Pin 027 (P2-07): Muxed Encoder #5, pin Muxed A (Input)
hm2/hm2_7i80.0: IO Pin 028 (P2-09): Muxed Encoder #5, pin Muxed B (Input)
hm2/hm2_7i80.0: IO Pin 029 (P2-11): Muxed Encoder #5, pin Muxed Index 
(Input)
hm2/hm2_7i80.0: IO Pin 030 (P2-13): Muxed Encoder #6, pin Muxed A (Input)
hm2/hm2_7i80.0: IO Pin 031 (P2-15): Muxed Encoder #6, pin Muxed B (Input)
hm2/hm2_7i80.0: IO Pin 032 (P2-17): Muxed Encoder #6, pin Muxed Index 
(Input)
hm2/hm2_7i80.0: IO Pin 033 (P2-19): Muxed Encoder #7, pin Muxed A (Input)
hm2/hm2_7i80.0: IO Pin 034 (P2-21): Muxed Encoder #7, pin Muxed B (Input)
hm2/hm2_7i80.0: IO Pin 035 (P2-23): Muxed Encoder #7, pin Muxed Index 
(Input)
hm2/hm2_7i80.0: IO Pin 036 (P2-25): IOPort
hm2/hm2_7i80.0: IO Pin 037 (P2-27): Muxed Encoder Select #8, pin Mux Select 
0 (Output)
hm2/hm2_7i80.0: IO Pin 038 (P2-29): Buffered SPI Interface #1, pin /Frame 
(Output)
hm2/hm2_7i80.0: IO Pin 039 (P2-31): Buffered SPI Interface #1, pin Serial 
Out (Output)
hm2/hm2_7i80.0: IO Pin 040 (P2-33): Buffered SPI Interface #1, pin Clock 
(Output)
hm2/hm2_7i80.0: IO Pin 041 (P2-35): Buffered SPI Interface #1, pin Serial 
In (Input)
hm2/hm2_7i80.0: IO Pin 042 (P2-37): Buffered SPI Interface #1, p

Re: [Emc-users] mesa 7i80 configuration

2022-01-27 Thread John Figie

>
> 7i80hd_25_2x7i65.bit has 2x BSPI and 16 muxed encoders
>
> (which would work for testing even if
> you don't have muxed interface hardware)
>
> It sounds like you would want custom formware
>
>
> mesaflash --device 7i80 --addr 10.10.10.10 --write  7i80hd_25_2x7i65.bit
it writes and verifies but then in halrun I get a different error. I tried
this several times.

hm2/hm2_7i80.0 Low level init 0.15
hm2/hm2_7i80.0 invalid IDROM type 65535, expected 2 or 3 aborting load
board fails HM2_registration

also when you say 16 muxed encoders how are these muxed?

regards,

John

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Re: [Emc-users] mesa 7i80 configuration

2022-01-27 Thread Peter C. Wallace

On Thu, 27 Jan 2022, John Figie wrote:

Date: Thu, 27 Jan 2022 16:12:43 -0600
From: John Figie 
Reply-To: "Enhanced Machine Controller (EMC)"

To: "Enhanced Machine Controller (EMC)" 
Subject: Re: [Emc-users] mesa 7i80 configuration

which is not supported by LinuxCNC. The only SPI module supported by
LinuxCNC
is the buffered SPI module: BSPI. If you want to experiment with the BSPI
module, the 7i65 configurations contain that module.

OK that makes sense but where are these 7i65 configurations?
That is why I was asking about pin files a few days ago. In order to figure
out what these
bit files are I have to load them into the card and then read the config
out.

Are there any configurations that
have encoder inputs and BSPI channels?

regards,

John FIgie

7i80hd_25_2x7i65.bit has 2x BSPI and 16 muxed encoders

(which would work for testing even if
you don't have muxed interface hardware)

It sounds like you would want custom formware

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Peter Wallace
Mesa Electronics

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Re: [Emc-users] mesa 7i80 configuration

2022-01-27 Thread John Figie

> which is not supported by LinuxCNC. The only SPI module supported by
> LinuxCNC
> is the buffered SPI module: BSPI. If you want to experiment with the BSPI
> module, the 7i65 configurations contain that module.
>
>
OK that makes sense but where are these 7i65 configurations?
That is why I was asking about pin files a few days ago. In order to figure
out what these
bit files are I have to load them into the card and then read the config
out.

Are there any configurations that
have encoder inputs and BSPI channels?

regards,

John FIgie

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Re: [Emc-users] mesa 7i80 configuration

2022-01-27 Thread Peter C. Wallace

On Thu, 27 Jan 2022, John Figie wrote:

Date: Thu, 27 Jan 2022 15:39:31 -0600
From: John Figie 
Reply-To: "Enhanced Machine Controller (EMC)"

To: emc-users 
Subject: [Emc-users] mesa 7i80 configuration

I am running out of ideas about why linuxcnc is unhappy with my 7i80

first I loaded the bit file 7i80hd_25_svsp8_6.bit and that loaded without
issue using mesaflash
next I try to make a simple hal file to instantiate the 7i80 but I get an
error?

hm2: Firmware contains unknown function (gtag-7)

my terminal and hal file look like this:
terminal window output and hal file
<https://drive.google.com/file/d/1L8AxeHAxnYuVpXUoeANMTX58nu6TrZjP/view?usp=sharing>

any help will be appreciated

regards,

John Figie

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That bitfile contains multiple instances of the "SimpleSPI" module (GTag 7)
which is not supported by LinuxCNC. The only SPI module supported by LinuxCNC
is the buffered SPI module: BSPI. If you want to experiment with the BSPI 
module, the 7i65 configurations contain that module.

Peter Wallace
Mesa Electronics

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Re: [Emc-users] mesa 7i80 configuration

2022-01-27 Thread andy pugh

On Thu, 27 Jan 2022 at 21:42, John Figie  wrote:

>  hm2: Firmware contains unknown function (gtag-7)

GTAG 7 is SPI:
https://github.com/LinuxCNC/linuxcnc/blob/master/src/hal/drivers/mesa-hostmot2/hostmot2.h#L94

Do you need SPI?

-- 
atp
"A motorcycle is a bicycle with a pandemonium attachment and is
designed for the especial use of mechanical geniuses, daredevils and
lunatics."
— George Fitch, Atlanta Constitution Newspaper, 1912


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[Emc-users] mesa 7i80 configuration

2022-01-27 Thread John Figie

I am running out of ideas about why linuxcnc is unhappy with my 7i80

first I loaded the bit file 7i80hd_25_svsp8_6.bit and that loaded without
issue using mesaflash
next I try to make a simple hal file to instantiate the 7i80 but I get an
error?

 hm2: Firmware contains unknown function (gtag-7)

my terminal and hal file look like this:
terminal window output and hal file


any help will be appreciated

regards,

John Figie

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