On Fri, 7 Apr 2023 at 15:52, Stefan Reinauer
wrote:
> You should also be able to just say "make flashrom" instead of just "make"
> or "make all"
>
Stefan,
I think the longer term intent is to EOL the Makefile in favour of meson.
The last release was about feature parity between the two build
CC: Thomas who knows this part best.
Hey Alex, Thanks for the report! My impression was that if the dependencies
are not found documentation should not be built, it should be optional.
Was this via the Makefile or meson and was this Tip of Tree or a release
tarball? Could you also provide a log
Have you tried a newer flashrom version? ch341a_spi looks like it failed
from a USB timeout.
On Sat, 11 Mar 2023 at 11:28, Eric G wrote:
> Hi,
> My chip is in an unknown state after trying to write. I tried ch341a_spi
> and linux_spi. I have three log files.
>
> Write Protect does NOT work.
The required writeprotect bits are missing from the flashchip definition.
If you can determine them from the datasheet please add them and retry?
On Sat, 4 Mar 2023 at 18:46, Anastasia Klimchuk wrote:
> I have created a patch for this chip:
>
A good starter project in this area would be to perhaps start moving
drivers (apart from internal and a few exceptions) into drivers/{spi,
parallel, opaque}/.
Cheers,
Edward.
On Fri, 24 Feb 2023 at 06:45, Prakhar Agrawal
wrote:
> I looked into meson. It's awesome!
>
> It provides all the tools
Love it and thank you for taking on the work to modernise flashrom
documentation Thomas! This is long overdue.
Kindest regards,
Edward.
On Tue, 14 Feb 2023 at 04:27, Thomas Heijligen wrote:
> Hi flashromers,
>
> For all the time I'm now working on flashrom I've avoided to touch the
> man-page.
G'day flashrom'ers,
Does anyone use or still need the wbsio spi path specifically used for the
Intel D201GLY board? I wish to remove this code
https://review.coreboot.org/c/flashrom/+/72828 if at all possible.
The reasoning is that a lot of board_enable changes would be required to
allow for the
I very much like Richard's pragmatic approach here.
It would be my view that we should re-evaluate branch critical bugs
(sb600spi map issue + build system stuff are the two the most prominent in
my mind at the moment) and just cut a release branch, stabilise that with
some cherry-picks of any
Hello,
While refactoring flashrom.c to move towards a reentrant flashrom a
pragmatic choice of utilising NULLity to represent the default state of a
struct at instiation was used in the following and related commits -
https://review.coreboot.org/c/flashrom/+/67391/
It was brought to my attention
Hi,
You may wish to give the following two patches a go
https://review.coreboot.org/c/flashrom/+/65238/
Cheers,
Edward.
On Tue, 28 Jun 2022 at 02:24, Armin via flashrom
wrote:
> Hi,
>
> here is a report of an unsupported EEPROM/flash device:
>
> *flashrom output:*
>
> flashrom v1.2 on Linux
Relax. Update the corresponding bugs with what you see as an actual issue
so it can be fixed. :)
Cheers Nico,
Edward.
On Tue, 28 Jun 2022 at 04:19, Nico Huber wrote:
> On 27.06.22 04:18, Edward O'Callaghan wrote:
> > On Sun, 26 Jun 2022 at 10:10, Nico Huber wrote:
> >
> >> Hi Anastasia,
> >>
On Sun, 26 Jun 2022 at 10:10, Nico Huber wrote:
> Hi Anastasia,
>
Probably not suitable to laser Anastasia in particular. Peter owns the i2c
set of drivers.
>
> I've seen you put some questions about the programmer tickets[1-4] on
> the meeting agenda. I hope I can provide some answers
It is probably a good idea to create two branches but probably more for the
sake of very old hardware not so easily accessible, par masters springs
most to mind. Exceedingly old Intel/VIA could also be included although I
am not sure which year to pick as the line in the sand there for 'old'?
Hi James,
These differences are being actively worked on James. Although as you noted
there are some key areas of difference that are not easy to upstream as
they currently are.
I believe two key areas you may run into is lack of cros_ec support for
updating the EC and lack of a ignore_error
On Sun, 28 Feb 2021 at 09:45, Drew Fustini wrote:
>
> Add support for GD25LQ256D [1]. I have tested both reading and writing
> complete ROM to this device using FT2232H (Tigard board) [2] connected
> to the GD25LQ256D on the BeagleV dev board [3].
>
> [1]
Hey Carl-Daniel,
I think it would be great if we could think up more areas of the code
base to write some additional unit-tests for? Those tests now run as
part of gerrit review however our coverage at the moment is not
significant enough to be useful in a reasonable sense. We should set
about
Hey Richard,
I like the general idea and mostly the interface however not so much
the singleton in the API. Rather, I think we should pack and carry
state within the flashctx as it is a more reentrant design that lends
well to writing unit-tests for which I would like to see more of in
Flashrom.
Hey Pete,
Send the patch to gerrit, some support seems better than no support imho.
Kind regards,
Edward.
On Sat, 9 Jan 2021 at 08:06, Pete Smith via flashrom
wrote:
>
> Hi,
>
> I have a a GIGABYTE GA-H270N-WIFI motherboard with DualBIOS feature.
> Flashrom 1.2 is unable to select between the
On Tue, 22 Dec 2020 at 08:40, Clay Daniels wrote:
>
> Lac, you probably installed flashrom from a binary package. The fix Edward
> gives is intended to go into a source file sb600spi.c and then compiled to
> produce the executable binary on your Lenovo Ideapad 3.
Thanks Clay for helping to
Hi,
Please try the following
https://review.coreboot.org/c/flashrom/+/48779 and let me know if it
works for you?
Kind regards,
Edward.
On Mon, 21 Dec 2020 at 12:03, Lac Onis wrote:
>
> From a Lenovo Ideapad 3 15are05, on Ubuntu 20.04
> As suggested, I report the following log.
>
> I'd be
I just noticed this email while searching for 0x61 and thought I would
mention that the support for Ryzen style FCH's is actually done and has
merged. Feel free to give the tip of the tree a go for your board and let
me know if you have any issues with it!
Kind regards,
Edward.
On Wed, 16 Dec
Hi Mike,
Seems reasonable to me to prepare a patch to mark it as tested in that case?
Cheers,
Edward.
On Tue, 1 Dec 2020 at 08:27, Mike Brown wrote:
> I have tested both erase and write functionality on this chip and it
> is working properly. verified md5sum of the image I flashed as well as
Hey guys,
Sorry for the delays in response due to local issues here..
Thanks for spotting this issue that slipped through the cracks. I actually
think this came about from a local merge conflict resolution. We had
breakages internally for all sorts of random reasons as well while trying
the
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