CPU: Cyrix 486DX2 (486-class CPU)
Origin = CyrixInstead DIR=0xa01b Stepping=10 Revision=0
# ./pausetest
Testing PAUSE instruction:
Register esp changed: 0xbfbffd04 - 0xbfbffcc8
--
Bob Bishop +44 (0)118 977 4017
[EMAIL PROTECTED]fax +44 (0)118 989 4254
To
Hey gang, although Intel's document seems to claim that they tested
proper operation of pause I'd like people with non-Intel processors
to verify that it actually works. Please compile the attached test
program and run it. The output should look like this:
./pt
Testing PAUSE instruction:
I tested this on my T-bird athlon 800, and this is the result:
Testing PAUSE instruction:
Register esp changed: 0xbfbffb38 - 0xbfbffafc
So I guess there's no problem.
Ken
On Fri, 24 May 2002, John Baldwin wrote:
Hey gang, although Intel's document seems to claim that they tested
proper
CPU: Cyrix 6x86MX (166.19-MHz 686-class CPU)
Origin = CyrixInstead Id = 0x600 Stepping = 0 DIR=0x0452
Features=0x80a135FPU,DE,TSC,MSR,CX8,PGE,CMOV,MMX
spambox2% ./pausetest
Testing PAUSE instruction:
Register esp changed: 0xbfbffbbc - 0xbfbffb80
CPU: AMD Duron(tm) Processor (995.77-MHz
On 24 Mai, John Baldwin wrote:
Hey gang, although Intel's document seems to claim that they tested
proper operation of pause I'd like people with non-Intel processors
to verify that it actually works. Please compile the attached test
program and run it. The output should look like this:
On 2002-05-24 10:25, John Baldwin wrote:
Please compile the attached test program and run it. The output
should look like this:
./pt
Testing PAUSE instruction:
Register esp changed: 0xbfbff9fc - 0xbfbff9c0
Intel Pentium 133 here, the output looks fine:
hades+charon:/tmp$ cc -o pausetest
$ dmesg | head | tail -4
CPU: AMD Athlon(tm) XP 1700+ (1466.51-MHz 686-class CPU)
Origin = AuthenticAMD Id = 0x662 Stepping = 2
Features=0x383f9ffFPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,MMX,FXSR,SSE
AMD Features=0xc048b19,AMIE,DSP,3DNow!
$ ./pt
Testing
On Fri, 24 May 2002, John Baldwin wrote:
Hey gang, although Intel's document seems to claim that they tested
proper operation of pause I'd like people with non-Intel processors
to verify that it actually works. Please compile the attached test
program and run it.
The only non-intel or AMD
On Fri, May 24, 2002 at 10:25:53AM -0400, John Baldwin wrote:
Hey gang, although Intel's document seems to claim that they tested
proper operation of pause I'd like people with non-Intel processors
to verify that it actually works. Please compile the attached test
program and run it. The
CPU: AMD Athlon(tm) MP Processor (1194.68-MHz 686-class CPU)
Origin = AuthenticAMD Id = 0x661 Stepping = 1
Features=0x383fbffFPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CM
OV,PAT,PSE36,MMX,FXSR,SSE
AMD Features=0xc044RSVD,AMIE,DSP,3DNow!
(%:~)- ./pausetest
Testing PAUSE
Itanium running x86 binaries:
CPU: Itanium (800.03-Mhz)
Origin = GenuineIntel Model = 0 Revision = 4
Features = 0x0
ia64# ./pausetest
Testing PAUSE instruction:
Register esp changed: 0xdbc4 - 0xdb88
ia64# file ./pausetest
./pausetest: ELF 32-bit LSB executable, Intel 80386,
At Fri, 24 May 2002 10:25:53 -0400 (EDT), John Baldwin wrote:
Hey gang, although Intel's document seems to claim that they tested
proper operation of pause I'd like people with non-Intel processors
to verify that it actually works.
It works fine on my Transmeta Crusoe TM5600, about as
On 24-May-2002 (14:25:53/GMT) John Baldwin wrote:
Please compile the attached test program and run it...
FreeBSD 5.0-CURRENT #34: Wed May 8 02:31:46 CEST 2002
CPU: Pentium III/Pentium III Xeon/Celeron (501.14-MHz 686-class CPU)
Origin = GenuineIntel Id = 0x672 Stepping = 2
* John Baldwin [EMAIL PROTECTED] [2002-05-24 08:27]:
Hey gang, although Intel's document seems to claim that they tested
proper operation of pause I'd like people with non-Intel processors
to verify that it actually works. Please compile the attached test
program and run it. The output
On Fri, 24 May 2002 10:25:53 -0400 (EDT)
John Baldwin [EMAIL PROTECTED] wrote:
Hey gang, although Intel's document seems to claim that they tested
proper operation of pause I'd like people with non-Intel processors
to verify that it actually works. Please compile the attached test
program
I get:
stylus:~$ cc pausetest.c
stylus:~$ ./a.out
Testing PAUSE instruction:
Register esp changed: 0xbfbff79c - 0xbfbff760
.. I assume this is functional. =)
I have:
CPU: AMD Athlon(tm) MP 1900+ (1592.90-MHz 686-class CPU)
Origin = AuthenticAMD Id = 0x662 Stepping = 2
16 matches
Mail list logo
