On 6/24/2023 8:03 AM, Dmitry Baryshkov wrote:
On 24/06/2023 17:17, Abhinav Kumar wrote:
On 6/24/2023 5:07 AM, Dmitry Baryshkov wrote:
On 24/06/2023 03:09, Abhinav Kumar wrote:
On 6/22/2023 5:13 PM, Dmitry Baryshkov wrote:
On 23/06/2023 02:48, Ryan McCann wrote:
Currently, the device
On 24/06/2023 17:17, Abhinav Kumar wrote:
On 6/24/2023 5:07 AM, Dmitry Baryshkov wrote:
On 24/06/2023 03:09, Abhinav Kumar wrote:
On 6/22/2023 5:13 PM, Dmitry Baryshkov wrote:
On 23/06/2023 02:48, Ryan McCann wrote:
Currently, the device core dump mechanism does not dump registers
of sub
On 6/24/2023 5:07 AM, Dmitry Baryshkov wrote:
On 24/06/2023 03:09, Abhinav Kumar wrote:
On 6/22/2023 5:13 PM, Dmitry Baryshkov wrote:
On 23/06/2023 02:48, Ryan McCann wrote:
Currently, the device core dump mechanism does not dump registers of
sub
blocks within the DSPP, SSPP, DSC, and
On 24/06/2023 03:41, Marijn Suijten wrote:
Enable and configure the dispcc node on SM6125 for consumption by MDSS
later on.
Signed-off-by: Marijn Suijten
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 23 +++
1 file changed, 23 insertions(+)
diff --git
On 24/06/2023 04:49, Konrad Dybcio wrote:
On 24.06.2023 02:41, Marijn Suijten wrote:
SM6125 features only a single PHY (despite a secondary PHY PLL source
being available to the disp_cc_mdss_pclk0_clk_src clock), and downstream
sources for this "trinket" SoC do not define the typical "vcca"
On 24/06/2023 03:41, Marijn Suijten wrote:
Document availability of the 14nm DSI PHY on SM6125.
Signed-off-by: Marijn Suijten
---
Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
On 23/06/2023 02:48, Ryan McCann wrote:
Currently, the device core dump mechanism does not dump registers of sub
blocks within the DSPP, SSPP, DSC, and PINGPONG blocks. Add wrapper
function to dump hardware blocks that contain sub blocks.
Signed-off-by: Ryan McCann
---
On 24/06/2023 04:23, Jessica Zhang wrote:
On 6/23/2023 5:09 PM, Abhinav Kumar wrote:
On 6/22/2023 5:13 PM, Dmitry Baryshkov wrote:
On 23/06/2023 02:48, Ryan McCann wrote:
Currently, the device core dump mechanism does not dump registers of
sub
blocks within the DSPP, SSPP, DSC, and
On 24/06/2023 03:09, Abhinav Kumar wrote:
On 6/22/2023 5:13 PM, Dmitry Baryshkov wrote:
On 23/06/2023 02:48, Ryan McCann wrote:
Currently, the device core dump mechanism does not dump registers of sub
blocks within the DSPP, SSPP, DSC, and PINGPONG blocks. Add wrapper
function to dump
On 24/06/2023 02:41, Marijn Suijten wrote:
> Document availability of the 14nm DSI PHY on SM6125.
>
> Signed-off-by: Marijn Suijten
> ---
> Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
On 24/06/2023 02:41, Marijn Suijten wrote:
> Document the SM6125 MDSS.
>
> Signed-off-by: Marijn Suijten
> ---
Reviewed-by: Krzysztof Kozlowski
Best regards,
Krzysztof
On 24/06/2023 02:41, Marijn Suijten wrote:
> SM6125 is identical to SM6375 except that while downstream also defines
> a throttle clock, its presence results in timeouts whereas SM6375
> requires it to not observe any timeouts.
Then it should not be allowed, so you need either "else:" block or
On 24/06/2023 02:41, Marijn Suijten wrote:
> Document general compatibility of the DSI controller on SM6125.
>
> Signed-off-by: Marijn Suijten
> ---
> Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++
> 1 file changed, 2 insertions(+)
Reviewed-by: Krzysztof
On 24/06/2023 02:41, Marijn Suijten wrote:
> On SM6125 the dispcc block is gated behind VDDCX: allow this domain to
> be configured.
>
> Signed-off-by: Marijn Suijten
> ---
> Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml | 5 +
> 1 file changed, 5 insertions(+)
On 24/06/2023 03:45, Konrad Dybcio wrote:
> On 24.06.2023 02:41, Marijn Suijten wrote:
>> The "gcc_disp_gpll0_div_clk_src" clock is consumed by the driver, will
>> be passed from DT, and should be required by the bindings.
>>
>> Fixes: 8397c9c0c26b ("dt-bindings: clock: add QCOM SM6125 display
On 24/06/2023 02:41, Marijn Suijten wrote:
> The downsteam driver for dispcc only ever gets and puts this clock
> without ever using it in the clocktree; this unnecessary workaround was
> never ported to mainline, hence the driver doesn't consume this clock
> and shouldn't be required by the
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